Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

crypto: cavium/nitrox - Allocate asymmetric crypto command queues

This patch adds support to allocate CNN55XX device AQMQ command queues
required for submitting asymmetric crypto requests.

Signed-off-by: Phani Kiran Hemadri <phemadri@marvell.com>
Reviewed-by: Srikanth Jampala <jsrikanth@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Phani Kiran Hemadri and committed by
Herbert Xu
b31c17c8 43b970fa

+99 -1
+4
drivers/crypto/cavium/nitrox/nitrox_dev.h
··· 10 10 #define VERSION_LEN 32 11 11 /* Maximum queues in PF mode */ 12 12 #define MAX_PF_QUEUES 64 13 + /* Maximum device queues */ 14 + #define MAX_DEV_QUEUES (MAX_PF_QUEUES) 13 15 /* Maximum UCD Blocks */ 14 16 #define CNN55XX_MAX_UCD_BLOCKS 8 15 17 ··· 210 208 * @mode: Device mode PF/VF 211 209 * @ctx_pool: DMA pool for crypto context 212 210 * @pkt_inq: Packet input rings 211 + * @aqmq: AQM command queues 213 212 * @qvec: MSI-X queue vectors information 214 213 * @iov: SR-IOV informatin 215 214 * @num_vecs: number of MSI-X vectors ··· 237 234 238 235 struct dma_pool *ctx_pool; 239 236 struct nitrox_cmdq *pkt_inq; 237 + struct nitrox_cmdq *aqmq[MAX_DEV_QUEUES] ____cacheline_aligned_in_smp; 240 238 241 239 struct nitrox_q_vector *qvec; 242 240 struct nitrox_iov iov;
+65 -1
drivers/crypto/cavium/nitrox/nitrox_lib.c
··· 19 19 20 20 /* packet inuput ring alignments */ 21 21 #define PKTIN_Q_ALIGN_BYTES 16 22 + /* AQM Queue input alignments */ 23 + #define AQM_Q_ALIGN_BYTES 32 22 24 23 25 static int nitrox_cmdq_init(struct nitrox_cmdq *cmdq, int align_bytes) 24 26 { ··· 59 57 60 58 static void nitrox_cmdq_cleanup(struct nitrox_cmdq *cmdq) 61 59 { 62 - struct nitrox_device *ndev = cmdq->ndev; 60 + struct nitrox_device *ndev; 61 + 62 + if (!cmdq) 63 + return; 63 64 64 65 if (!cmdq->unalign_base) 65 66 return; 66 67 68 + ndev = cmdq->ndev; 67 69 cancel_work_sync(&cmdq->backlog_qflush); 68 70 69 71 dma_free_coherent(DEV(ndev), cmdq->qsize, ··· 82 76 cmdq->dma = 0; 83 77 cmdq->qsize = 0; 84 78 cmdq->instr_size = 0; 79 + } 80 + 81 + static void nitrox_free_aqm_queues(struct nitrox_device *ndev) 82 + { 83 + int i; 84 + 85 + for (i = 0; i < ndev->nr_queues; i++) { 86 + nitrox_cmdq_cleanup(ndev->aqmq[i]); 87 + kzfree(ndev->aqmq[i]); 88 + ndev->aqmq[i] = NULL; 89 + } 90 + } 91 + 92 + static int nitrox_alloc_aqm_queues(struct nitrox_device *ndev) 93 + { 94 + int i, err; 95 + 96 + for (i = 0; i < ndev->nr_queues; i++) { 97 + struct nitrox_cmdq *cmdq; 98 + u64 offset; 99 + 100 + cmdq = kzalloc_node(sizeof(*cmdq), GFP_KERNEL, ndev->node); 101 + if (!cmdq) { 102 + err = -ENOMEM; 103 + goto aqmq_fail; 104 + } 105 + 106 + cmdq->ndev = ndev; 107 + cmdq->qno = i; 108 + cmdq->instr_size = sizeof(struct aqmq_command_s); 109 + 110 + /* AQM Queue Doorbell Counter Register Address */ 111 + offset = AQMQ_DRBLX(i); 112 + cmdq->dbell_csr_addr = NITROX_CSR_ADDR(ndev, offset); 113 + /* AQM Queue Commands Completed Count Register Address */ 114 + offset = AQMQ_CMD_CNTX(i); 115 + cmdq->compl_cnt_csr_addr = NITROX_CSR_ADDR(ndev, offset); 116 + 117 + err = nitrox_cmdq_init(cmdq, AQM_Q_ALIGN_BYTES); 118 + if (err) { 119 + kzfree(cmdq); 120 + goto aqmq_fail; 121 + } 122 + ndev->aqmq[i] = cmdq; 123 + } 124 + 125 + return 0; 126 + 127 + aqmq_fail: 128 + nitrox_free_aqm_queues(ndev); 129 + return err; 85 130 } 86 131 87 132 static void nitrox_free_pktin_queues(struct nitrox_device *ndev) ··· 279 222 if (err) 280 223 destroy_crypto_dma_pool(ndev); 281 224 225 + err = nitrox_alloc_aqm_queues(ndev); 226 + if (err) { 227 + nitrox_free_pktin_queues(ndev); 228 + destroy_crypto_dma_pool(ndev); 229 + } 230 + 282 231 return err; 283 232 } 284 233 ··· 294 231 */ 295 232 void nitrox_common_sw_cleanup(struct nitrox_device *ndev) 296 233 { 234 + nitrox_free_aqm_queues(ndev); 297 235 nitrox_free_pktin_queues(ndev); 298 236 destroy_crypto_dma_pool(ndev); 299 237 }
+30
drivers/crypto/cavium/nitrox/nitrox_req.h
··· 400 400 }; 401 401 402 402 /** 403 + * struct aqmq_command_s - The 32 byte command for AE processing. 404 + * @opcode: Request opcode 405 + * @param1: Request control parameter 1 406 + * @param2: Request control parameter 2 407 + * @dlen: Input length 408 + * @dptr: Input pointer points to buffer in remote host 409 + * @rptr: Result pointer points to buffer in remote host 410 + * @grp: AQM Group (0..7) 411 + * @cptr: Context pointer 412 + */ 413 + struct aqmq_command_s { 414 + __be16 opcode; 415 + __be16 param1; 416 + __be16 param2; 417 + __be16 dlen; 418 + __be64 dptr; 419 + __be64 rptr; 420 + union { 421 + __be64 word3; 422 + #if defined(__BIG_ENDIAN_BITFIELD) 423 + u64 grp : 3; 424 + u64 cptr : 61; 425 + #else 426 + u64 cptr : 61; 427 + u64 grp : 3; 428 + #endif 429 + }; 430 + }; 431 + 432 + /** 403 433 * struct ctx_hdr - Book keeping data about the crypto context 404 434 * @pool: Pool used to allocate crypto context 405 435 * @dma: Base DMA address of the cypto context