tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
soundwire: qcom: adding support for v3.1.0
Add support for controller version v3.1.0, which has changes in
register layout and some register fields compared to v2.0.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Tested-by: Alexey Klimov <alexey.klimov@linaro.org> # sm8550
Link: https://patch.msgid.link/20250912083225.228778-8-srinivas.kandagatla@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Srinivas Kandagatla
and committed by
Vinod Koul
b2bfe0fa
66eca4b7
+36
-1
+36
-1
drivers/soundwire/qcom.c
+36
-1
drivers/soundwire/qcom.c
···
31
31
#define SWRM_VERSION_1_5_1 0x01050001
32
32
#define SWRM_VERSION_1_7_0 0x01070000
33
33
#define SWRM_VERSION_2_0_0 0x02000000
34
+
#define SWRM_VERSION_3_1_0 0x03010000
34
35
#define SWRM_COMP_HW_VERSION 0x00
35
36
#define SWRM_COMP_CFG_ADDR 0x04
36
37
#define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
···
41
40
#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15)
42
41
#define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
43
42
#define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
43
+
#define SWRM_V3_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(17, 10)
44
+
#define SWRM_V3_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(23, 18)
45
+
44
46
#define SWRM_COMP_MASTER_ID 0x104
45
47
#define SWRM_V1_3_INTERRUPT_STATUS 0x200
46
48
#define SWRM_V2_0_INTERRUPT_STATUS 0x5000
···
300
296
.reg_layout = swrm_v2_0_reg_layout,
301
297
};
302
298
299
+
static const unsigned int swrm_v3_0_reg_layout[] = {
300
+
[SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS,
301
+
[SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS,
302
+
[SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
303
+
[SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR,
304
+
[SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN,
305
+
[SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD,
306
+
[SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
307
+
[SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
308
+
[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
309
+
[SWRM_OFFSET_DP_PORT_CTRL_BANK] = 0x1224,
310
+
[SWRM_OFFSET_DP_PORT_CTRL_2_BANK] = 0x1228,
311
+
[SWRM_OFFSET_DP_BLOCK_CTRL_1] = 0x122c,
312
+
[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK] = 0x1230,
313
+
[SWRM_OFFSET_DP_PORT_HCTRL_BANK] = 0x1234,
314
+
[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK] = 0x1238,
315
+
[SWRM_OFFSET_DP_SAMPLECTRL2_BANK] = 0x123c,
316
+
};
317
+
318
+
static const struct qcom_swrm_data swrm_v3_0_data = {
319
+
.default_rows = 50,
320
+
.default_cols = 16,
321
+
.sw_clk_gate_required = true,
322
+
.max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR,
323
+
.reg_layout = swrm_v3_0_reg_layout,
324
+
};
303
325
#define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
304
326
305
327
static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
···
949
919
swrm_wait_for_frame_gen_enabled(ctrl);
950
920
ctrl->slave_status = 0;
951
921
ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
952
-
ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
922
+
923
+
if (ctrl->version >= SWRM_VERSION_3_1_0)
924
+
ctrl->wr_fifo_depth = FIELD_GET(SWRM_V3_COMP_PARAMS_WR_FIFO_DEPTH, val);
925
+
else
926
+
ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
953
927
954
928
return 0;
955
929
}
···
1819
1785
{ .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1820
1786
{ .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
1821
1787
{ .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data },
1788
+
{ .compatible = "qcom,soundwire-v3.1.0", .data = &swrm_v3_0_data },
1822
1789
{/* sentinel */},
1823
1790
};
1824
1791