tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mvebu-dt64-4.15-1' of git://git.infradead.org/linux-mvebu into next/dt
Pull "mvebu dt64 for 4.15 (part 1)" from Gregory CLEMENT:
On Armada 7K/8k:
- Improve network support at SoC and board level
- Enable watchdog
- Add UART muxing
- On 7040 DB: add CD SDIO and NAND support
- On 8040 DB: add PCIE more ports and SPI1
On Armada 37xx:
- Fix UART register size
- Add vmmc regulator for SD on 3720 DB
* tag 'mvebu-dt64-4.15-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: 7040-db: Add the carrier detect pin for SD card on CP
arm64: dts: marvell: 7040-db: Document the gpio expander
arm64: dts: marvell: enable additional PCIe ports on Armada 8040 DB
arm64: dts: marvell: add NAND support on the 7040-DB board
arm64: dts: marvell: Enable Armada-8040-DB CPS SPI1
arm64: dts: marvell: 8040-db: enable the SFP ports
arm64: dts: marvell: 7040-db: enable the SFP port
arm64: dts: marvell: 7040-db: add comphy reference to Ethernet port
arm64: dts: marvell: mcbin: add comphy references to Ethernet ports
arm64: dts: marvell: 37xx: remove empty line
arm64: dts: marvell: cp110: add PPv2 port interrupts
arm64: dts: marvell: add comphy nodes on cp110 master and slave
arm64: dts: marvell: extend the cp110 syscon register area length
arm64: dts: marvell: enable AP806 watchdog
arm64: dts: marvell: Fix A37xx UART0 register size
arm64: dts: marvell: armada-3720-db: Add vmmc regulator for SD slot
arm64: dts: marvell: add UART muxing on Armada 7K/8K
+261
-20
+1
-1
Documentation/devicetree/bindings/serial/mvebu-uart.txt
+1
-1
Documentation/devicetree/bindings/serial/mvebu-uart.txt
+11
arch/arm64/boot/dts/marvell/armada-3720-db.dts
+11
arch/arm64/boot/dts/marvell/armada-3720-db.dts
···
94
94
3300000 0x0>;
95
95
enable-active-high;
96
96
};
97
+
98
+
vcc_sd_reg2: regulator-vmcc {
99
+
compatible = "regulator-fixed";
100
+
regulator-name = "vcc_sd2";
101
+
regulator-min-microvolt = <3300000>;
102
+
regulator-max-microvolt = <3300000>;
103
+
regulator-boot-on;
104
+
enable-active-high;
105
+
gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
106
+
};
97
107
};
98
108
99
109
/* Gigabit module on CON19(V2.0)/CON21(V1.4) */
···
189
179
bus-width = <4>;
190
180
marvell,pad-type = "sd";
191
181
vqmmc-supply = <&vcc_sd_reg1>;
182
+
vmmc-supply = <&vcc_sd_reg2>;
192
183
status = "okay";
193
184
};
194
185
+1
-2
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+1
-2
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
···
134
134
135
135
uart0: serial@12000 {
136
136
compatible = "marvell,armada-3700-uart";
137
-
reg = <0x12000 0x400>;
137
+
reg = <0x12000 0x200>;
138
138
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
139
139
status = "disabled";
140
140
};
···
183
183
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
184
184
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
185
185
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
186
-
187
186
};
188
187
189
188
xtalclk: xtal-clk {
+54
-1
arch/arm64/boot/dts/marvell/armada-7040-db.dts
+54
-1
arch/arm64/boot/dts/marvell/armada-7040-db.dts
···
124
124
125
125
&uart0 {
126
126
status = "okay";
127
+
pinctrl-0 = <&uart0_pins>;
128
+
pinctrl-names = "default";
127
129
};
128
130
129
131
···
143
141
gpio-controller;
144
142
#gpio-cells = <2>;
145
143
reg = <0x21>;
144
+
/*
145
+
* IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect
146
+
* IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit
147
+
* IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN
148
+
* IO0_3: USB2_DEVICE_DETECT
149
+
* IO0_4: GPIO_0 IO1_4: SD_Status
150
+
* IO0_5: GPIO_1 IO1_5: LDO_5V_Enable
151
+
* IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC
152
+
* IO0_7: IO1_7: SDIO_Vcntrl
153
+
*/
146
154
};
147
155
};
156
+
157
+
&cpm_nand {
158
+
/*
159
+
* SPI on CPM and NAND have common pins on this board. We can
160
+
* use only one at a time. To enable the NAND (whihch will
161
+
* disable the SPI), the "status = "okay";" line have to be
162
+
* added here.
163
+
*/
164
+
num-cs = <1>;
165
+
pinctrl-0 = <&nand_pins>, <&nand_rb>;
166
+
pinctrl-names = "default";
167
+
nand-ecc-strength = <4>;
168
+
nand-ecc-step-size = <512>;
169
+
marvell,nand-enable-arbiter;
170
+
nand-on-flash-bbt;
171
+
172
+
partition@0 {
173
+
label = "U-Boot";
174
+
reg = <0 0x200000>;
175
+
};
176
+
partition@200000 {
177
+
label = "Linux";
178
+
reg = <0x200000 0xe00000>;
179
+
};
180
+
partition@1000000 {
181
+
label = "Filesystem";
182
+
reg = <0x1000000 0x3f000000>;
183
+
};
184
+
};
185
+
148
186
149
187
&cpm_spi1 {
150
188
status = "okay";
···
239
197
status = "okay";
240
198
bus-width = <4>;
241
199
no-1-8-v;
242
-
non-removable;
200
+
cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
243
201
};
244
202
245
203
&cpm_mdio {
···
257
215
status = "okay";
258
216
};
259
217
218
+
&cpm_eth0 {
219
+
status = "okay";
220
+
/* Network PHY */
221
+
phy-mode = "10gbase-kr";
222
+
/* Generic PHY, providing serdes lanes */
223
+
phys = <&cpm_comphy2 0>;
224
+
};
225
+
260
226
&cpm_eth1 {
261
227
status = "okay";
228
+
/* Network PHY */
262
229
phy = <&phy0>;
263
230
phy-mode = "sgmii";
231
+
/* Generic PHY, providing serdes lanes */
232
+
phys = <&cpm_comphy0 1>;
264
233
};
265
234
266
235
&cpm_eth2 {
+14
arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+14
arch/arm64/boot/dts/marvell/armada-70x0.dtsi
···
64
64
&cpm_syscon0 {
65
65
cpm_pinctrl: pinctrl {
66
66
compatible = "marvell,armada-7k-pinctrl";
67
+
68
+
nand_pins: nand-pins {
69
+
marvell,pins =
70
+
"mpp15", "mpp16", "mpp17", "mpp18",
71
+
"mpp19", "mpp20", "mpp21", "mpp22",
72
+
"mpp23", "mpp24", "mpp25", "mpp26",
73
+
"mpp27";
74
+
marvell,function = "dev";
75
+
};
76
+
77
+
nand_rb: nand-rb {
78
+
marvell,pins = "mpp13";
79
+
marvell,function = "nf";
80
+
};
67
81
};
68
82
};
+57
arch/arm64/boot/dts/marvell/armada-8040-db.dts
+57
arch/arm64/boot/dts/marvell/armada-8040-db.dts
···
139
139
/* Accessible over the mini-USB CON9 connector on the main board */
140
140
&uart0 {
141
141
status = "okay";
142
+
pinctrl-0 = <&uart0_pins>;
143
+
pinctrl-names = "default";
142
144
};
143
145
146
+
/* CON6 on CP0 expansion */
147
+
&cpm_pcie0 {
148
+
status = "okay";
149
+
};
144
150
145
151
/* CON5 on CP0 expansion */
146
152
&cpm_pcie2 {
···
206
200
status = "okay";
207
201
};
208
202
203
+
&cpm_eth0 {
204
+
status = "okay";
205
+
phy-mode = "10gbase-kr";
206
+
};
207
+
209
208
&cpm_eth2 {
210
209
status = "okay";
211
210
phy = <&phy1>;
212
211
phy-mode = "rgmii-id";
212
+
};
213
+
214
+
/* CON6 on CP1 expansion */
215
+
&cps_pcie0 {
216
+
status = "okay";
217
+
};
218
+
219
+
/* CON7 on CP1 expansion */
220
+
&cps_pcie1 {
221
+
status = "okay";
213
222
};
214
223
215
224
/* CON5 on CP1 expansion */
···
235
214
&cps_i2c0 {
236
215
status = "okay";
237
216
clock-frequency = <100000>;
217
+
};
218
+
219
+
&cps_spi1 {
220
+
status = "okay";
221
+
222
+
spi-flash@0 {
223
+
#address-cells = <0x1>;
224
+
#size-cells = <0x1>;
225
+
compatible = "jedec,spi-nor";
226
+
reg = <0x0>;
227
+
spi-max-frequency = <20000000>;
228
+
229
+
partitions {
230
+
compatible = "fixed-partitions";
231
+
#address-cells = <1>;
232
+
#size-cells = <1>;
233
+
234
+
partition@0 {
235
+
label = "Boot";
236
+
reg = <0x0 0x200000>;
237
+
};
238
+
partition@200000 {
239
+
label = "Filesystem";
240
+
reg = <0x200000 0xd00000>;
241
+
};
242
+
partition@f00000 {
243
+
label = "Boot_2nd";
244
+
reg = <0xf00000 0x100000>;
245
+
};
246
+
};
247
+
};
238
248
};
239
249
240
250
/* CON4 on CP1 expansion */
···
294
242
295
243
&cps_ethernet {
296
244
status = "okay";
245
+
};
246
+
247
+
&cps_eth0 {
248
+
status = "okay";
249
+
phy-mode = "10gbase-kr";
297
250
};
298
251
299
252
&cps_eth1 {
+11
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+11
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
···
101
101
102
102
&uart0 {
103
103
status = "okay";
104
+
pinctrl-0 = <&uart0_pins>;
105
+
pinctrl-names = "default";
104
106
};
105
107
106
108
&ap_sdhci0 {
···
224
222
225
223
&cpm_eth0 {
226
224
status = "okay";
225
+
/* Network PHY */
227
226
phy = <&phy0>;
228
227
phy-mode = "10gbase-kr";
228
+
/* Generic PHY, providing serdes lanes */
229
+
phys = <&cpm_comphy4 0>;
229
230
};
230
231
231
232
&cpm_sata0 {
···
262
257
263
258
&cps_eth0 {
264
259
status = "okay";
260
+
/* Network PHY */
265
261
phy = <&phy8>;
266
262
phy-mode = "10gbase-kr";
263
+
/* Generic PHY, providing serdes lanes */
264
+
phys = <&cps_comphy4 0>;
267
265
};
268
266
269
267
&cps_eth1 {
270
268
/* CPS Lane 0 - J5 (Gigabit RJ45) */
271
269
status = "okay";
270
+
/* Network PHY */
272
271
phy = <&ge_phy>;
273
272
phy-mode = "sgmii";
273
+
/* Generic PHY, providing serdes lanes */
274
+
phys = <&cps_comphy0 1>;
274
275
};
275
276
276
277
&cps_pinctrl {
+11
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+11
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
···
241
241
242
242
};
243
243
244
+
watchdog: watchdog@600000 {
245
+
compatible = "arm,sbsa-gwdt";
246
+
reg = <0x610000 0x1000>, <0x600000 0x1000>;
247
+
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
248
+
};
249
+
244
250
ap_sdhci0: sdhci@6e0000 {
245
251
compatible = "marvell,armada-ap806-sdhci";
246
252
reg = <0x6e0000 0x300>;
···
269
263
270
264
ap_pinctrl: pinctrl {
271
265
compatible = "marvell,ap806-pinctrl";
266
+
267
+
uart0_pins: uart0-pins {
268
+
marvell,pins = "mpp11", "mpp19";
269
+
marvell,function = "uart0";
270
+
};
272
271
};
273
272
274
273
ap_gpio: gpio@1040 {
+51
-8
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+51
-8
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
···
74
74
<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
75
75
<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
76
76
<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
77
-
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
77
+
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
78
+
<ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
78
79
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
79
-
"tx-cpu3", "rx-shared";
80
+
"tx-cpu3", "rx-shared", "link";
80
81
port-id = <0>;
81
82
gop-port-id = <0>;
82
83
status = "disabled";
···
88
87
<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
89
88
<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
90
89
<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
91
-
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
90
+
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
91
+
<ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
92
92
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
93
-
"tx-cpu3", "rx-shared";
93
+
"tx-cpu3", "rx-shared", "link";
94
94
port-id = <1>;
95
95
gop-port-id = <2>;
96
96
status = "disabled";
···
102
100
<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
103
101
<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
104
102
<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
105
-
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
103
+
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
104
+
<ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
106
105
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
107
-
"tx-cpu3", "rx-shared";
106
+
"tx-cpu3", "rx-shared", "link";
108
107
port-id = <2>;
109
108
gop-port-id = <3>;
110
109
status = "disabled";
110
+
};
111
+
};
112
+
113
+
cpm_comphy: phy@120000 {
114
+
compatible = "marvell,comphy-cp110";
115
+
reg = <0x120000 0x6000>;
116
+
marvell,system-controller = <&cpm_syscon0>;
117
+
#address-cells = <1>;
118
+
#size-cells = <0>;
119
+
120
+
cpm_comphy0: phy@0 {
121
+
reg = <0>;
122
+
#phy-cells = <1>;
123
+
};
124
+
125
+
cpm_comphy1: phy@1 {
126
+
reg = <1>;
127
+
#phy-cells = <1>;
128
+
};
129
+
130
+
cpm_comphy2: phy@2 {
131
+
reg = <2>;
132
+
#phy-cells = <1>;
133
+
};
134
+
135
+
cpm_comphy3: phy@3 {
136
+
reg = <3>;
137
+
#phy-cells = <1>;
138
+
};
139
+
140
+
cpm_comphy4: phy@4 {
141
+
reg = <4>;
142
+
#phy-cells = <1>;
143
+
};
144
+
145
+
cpm_comphy5: phy@5 {
146
+
reg = <5>;
147
+
#phy-cells = <1>;
111
148
};
112
149
};
113
150
···
184
143
185
144
cpm_syscon0: system-controller@440000 {
186
145
compatible = "syscon", "simple-mfd";
187
-
reg = <0x440000 0x1000>;
146
+
reg = <0x440000 0x2000>;
188
147
189
148
cpm_clk: clock {
190
149
compatible = "marvell,cp110-clock";
···
315
274
* this controller is only usable on the CPM
316
275
* for A7K and on the CPS for A8K.
317
276
*/
318
-
compatible = "marvell,armada370-nand";
277
+
compatible = "marvell,armada-8k-nand",
278
+
"marvell,armada370-nand";
319
279
reg = <0x720000 0x54>;
320
280
#address-cells = <1>;
321
281
#size-cells = <1>;
322
282
interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
323
283
clocks = <&cpm_clk 1 2>;
284
+
marvell,system-controller = <&cpm_syscon0>;
324
285
status = "disabled";
325
286
};
326
287
+50
-8
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+50
-8
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
···
74
74
<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
75
75
<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
76
76
<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
77
-
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
77
+
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
78
+
<ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
78
79
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
79
-
"tx-cpu3", "rx-shared";
80
+
"tx-cpu3", "rx-shared", "link";
80
81
port-id = <0>;
81
82
gop-port-id = <0>;
82
83
status = "disabled";
···
88
87
<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
89
88
<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
90
89
<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
91
-
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
90
+
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
91
+
<ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
92
92
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
93
-
"tx-cpu3", "rx-shared";
93
+
"tx-cpu3", "rx-shared", "link";
94
94
port-id = <1>;
95
95
gop-port-id = <2>;
96
96
status = "disabled";
···
102
100
<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
103
101
<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
104
102
<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
105
-
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
103
+
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
104
+
<ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
106
105
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
107
-
"tx-cpu3", "rx-shared";
106
+
"tx-cpu3", "rx-shared", "link";
108
107
port-id = <2>;
109
108
gop-port-id = <3>;
110
109
status = "disabled";
110
+
};
111
+
};
112
+
113
+
cps_comphy: phy@120000 {
114
+
compatible = "marvell,comphy-cp110";
115
+
reg = <0x120000 0x6000>;
116
+
marvell,system-controller = <&cps_syscon0>;
117
+
#address-cells = <1>;
118
+
#size-cells = <0>;
119
+
120
+
cps_comphy0: phy@0 {
121
+
reg = <0>;
122
+
#phy-cells = <1>;
123
+
};
124
+
125
+
cps_comphy1: phy@1 {
126
+
reg = <1>;
127
+
#phy-cells = <1>;
128
+
};
129
+
130
+
cps_comphy2: phy@2 {
131
+
reg = <2>;
132
+
#phy-cells = <1>;
133
+
};
134
+
135
+
cps_comphy3: phy@3 {
136
+
reg = <3>;
137
+
#phy-cells = <1>;
138
+
};
139
+
140
+
cps_comphy4: phy@4 {
141
+
reg = <4>;
142
+
#phy-cells = <1>;
143
+
};
144
+
145
+
cps_comphy5: phy@5 {
146
+
reg = <5>;
147
+
#phy-cells = <1>;
111
148
};
112
149
};
113
150
···
184
143
185
144
cps_syscon0: system-controller@440000 {
186
145
compatible = "syscon", "simple-mfd";
187
-
reg = <0x440000 0x1000>;
146
+
reg = <0x440000 0x2000>;
188
147
189
148
cps_clk: clock {
190
149
compatible = "marvell,cp110-clock";
···
316
275
* this controller is only usable on the CPM
317
276
* for A7K and on the CPS for A8K.
318
277
*/
319
-
compatible = "marvell,armada370-nand";
278
+
compatible = "marvell,armada370-nand",
279
+
"marvell,armada370-nand";
320
280
reg = <0x720000 0x54>;
321
281
#address-cells = <1>;
322
282
#size-cells = <1>;