Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

arm: dts: Update cache properties for broadcom

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221122163208.3810985-2-pierre.gondois@arm.com
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

authored by

Pierre Gondois and committed by
Florian Fainelli
b2302467 af84101e

+10
+1
arch/arm/boot/dts/bcm2711.dtsi
··· 536 536 */ 537 537 l2: l2-cache0 { 538 538 compatible = "cache"; 539 + cache-unified; 539 540 cache-size = <0x100000>; 540 541 cache-line-size = <64>; 541 542 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
+1
arch/arm/boot/dts/bcm2836.dtsi
··· 112 112 */ 113 113 l2: l2-cache0 { 114 114 compatible = "cache"; 115 + cache-unified; 115 116 cache-size = <0x80000>; 116 117 cache-line-size = <64>; 117 118 cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
+1
arch/arm/boot/dts/bcm2837.dtsi
··· 114 114 */ 115 115 l2: l2-cache0 { 116 116 compatible = "cache"; 117 + cache-unified; 117 118 cache-size = <0x80000>; 118 119 cache-line-size = <64>; 119 120 cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
+1
arch/arm/boot/dts/bcm47622.dtsi
··· 51 51 52 52 L2_0: l2-cache0 { 53 53 compatible = "cache"; 54 + cache-level = <2>; 54 55 }; 55 56 }; 56 57
+1
arch/arm/boot/dts/bcm63148.dtsi
··· 35 35 36 36 L2_0: l2-cache0 { 37 37 compatible = "cache"; 38 + cache-level = <2>; 38 39 }; 39 40 }; 40 41
+1
arch/arm/boot/dts/bcm63178.dtsi
··· 43 43 44 44 L2_0: l2-cache0 { 45 45 compatible = "cache"; 46 + cache-level = <2>; 46 47 }; 47 48 }; 48 49
+1
arch/arm/boot/dts/bcm6756.dtsi
··· 51 51 52 52 L2_0: l2-cache0 { 53 53 compatible = "cache"; 54 + cache-level = <2>; 54 55 }; 55 56 }; 56 57
+1
arch/arm/boot/dts/bcm6846.dtsi
··· 35 35 36 36 L2_0: l2-cache0 { 37 37 compatible = "cache"; 38 + cache-level = <2>; 38 39 }; 39 40 }; 40 41
+1
arch/arm/boot/dts/bcm6855.dtsi
··· 43 43 44 44 L2_0: l2-cache0 { 45 45 compatible = "cache"; 46 + cache-level = <2>; 46 47 }; 47 48 }; 48 49
+1
arch/arm/boot/dts/bcm6878.dtsi
··· 35 35 36 36 L2_0: l2-cache0 { 37 37 compatible = "cache"; 38 + cache-level = <2>; 38 39 }; 39 40 }; 40 41