tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
sh: Add SH-2A platform headers.
Mostly SH-2 wrappers..
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
authored by
Yoshinori Sato
and committed by
Paul Mundt
b229632a
de398406
+415
-9
+5
-1
include/asm-sh/bugs.h
+5
-1
include/asm-sh/bugs.h
···
23
23
cpu_data->loops_per_jiffy = loops_per_jiffy;
24
24
25
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switch (cpu_data->type) {
26
-
case CPU_SH7604:
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+
case CPU_SH7604 ... CPU_SH7619:
27
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*p++ = '2';
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+
break;
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+
case CPU_SH7206:
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*p++ = '2';
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+
*p++ = 'a';
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break;
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case CPU_SH7705 ... CPU_SH7300:
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*p++ = '3';
+22
include/asm-sh/cpu-sh2/cache.h
+22
include/asm-sh/cpu-sh2/cache.h
···
12
12
13
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#define L1_CACHE_SHIFT 4
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+
#if defined(CONFIG_CPU_SUBTYPE_SH7604)
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#define CCR 0xfffffe92 /* Address of Cache Control Register */
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#define CCR_CACHE_CE 0x01 /* Cache enable */
···
28
27
#define CCR_CACHE_ORA CCR_CACHE_TW
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#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */
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+
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
31
+
#define CCR1 0xffffffec
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#define CCR CCR1
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+
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#define CCR_CACHE_CE 0x01 /* Cache enable */
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+
#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */
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/* 0x00000000-0x7fffffff: Write-through */
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/* 0x80000000-0x9fffffff: Write-back */
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+
/* 0xc0000000-0xdfffffff: Write-through */
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#define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */
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/* 0x00000000-0x7fffffff: Write-back */
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/* 0x80000000-0x9fffffff: Write-through */
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/* 0xc0000000-0xdfffffff: Write-back */
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#define CCR_CACHE_CF 0x08 /* Cache invalidate */
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+
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#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
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#define CACHE_OC_DATA_ARRAY 0xf1000000
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+
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#define CCR_CACHE_ENABLE CCR_CACHE_CE
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#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
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#endif
31
51
#endif /* __ASM_CPU_SH2_CACHE_H */
32
52
+18
include/asm-sh/cpu-sh2/freq.h
+18
include/asm-sh/cpu-sh2/freq.h
···
1
+
/*
2
+
* include/asm-sh/cpu-sh2/freq.h
3
+
*
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+
* Copyright (C) 2006 Yoshinori Sato
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*
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* This file is subject to the terms and conditions of the GNU General Public
7
+
* License. See the file "COPYING" in the main directory of this archive
8
+
* for more details.
9
+
*/
10
+
#ifndef __ASM_CPU_SH2_FREQ_H
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#define __ASM_CPU_SH2_FREQ_H
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+
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#if defined(CONFIG_CPU_SUBTYPE_SH7619)
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#define FREQCR 0xf815ff80
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#endif
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+
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#endif /* __ASM_CPU_SH2_FREQ_H */
18
+
+84
include/asm-sh/cpu-sh2/irq.h
+84
include/asm-sh/cpu-sh2/irq.h
···
1
+
#ifndef __ASM_SH_CPU_SH2_IRQ_H
2
+
#define __ASM_SH_CPU_SH2_IRQ_H
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+
4
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/*
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*
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* linux/include/asm-sh/cpu-sh2/irq.h
7
+
*
8
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9
+
* Copyright (C) 2000 Kazumoto Kojima
10
+
* Copyright (C) 2003 Paul Mundt
11
+
*
12
+
*/
13
+
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#include <linux/config.h>
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+
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#if defined(CONFIG_CPU_SUBTYPE_SH7044)
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#define INTC_IPRA 0xffff8348UL
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#define INTC_IPRB 0xffff834aUL
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#define INTC_IPRC 0xffff834cUL
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#define INTC_IPRD 0xffff834eUL
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#define INTC_IPRE 0xffff8350UL
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#define INTC_IPRF 0xffff8352UL
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+
#define INTC_IPRG 0xffff8354UL
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#define INTC_IPRH 0xffff8356UL
25
+
26
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#define INTC_ICR 0xffff8358UL
27
+
#define INTC_ISR 0xffff835aUL
28
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
29
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#define INTC_IPRA 0xfffffee2UL
30
+
#define INTC_IPRB 0xfffffe60UL
31
+
32
+
#define INTC_VCRA 0xfffffe62UL
33
+
#define INTC_VCRB 0xfffffe64UL
34
+
#define INTC_VCRC 0xfffffe66UL
35
+
#define INTC_VCRD 0xfffffe68UL
36
+
37
+
#define INTC_VCRWDT 0xfffffee4UL
38
+
#define INTC_VCRDIV 0xffffff0cUL
39
+
#define INTC_VCRDMA0 0xffffffa0UL
40
+
#define INTC_VCRDMA1 0xffffffa8UL
41
+
42
+
#define INTC_ICR 0xfffffee0UL
43
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
44
+
#define INTC_IPRA 0xf8140006UL
45
+
#define INTC_IPRB 0xf8140008UL
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+
#define INTC_IPRC 0xf8080000UL
47
+
#define INTC_IPRD 0xf8080002UL
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+
#define INTC_IPRE 0xf8080004UL
49
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#define INTC_IPRF 0xf8080006UL
50
+
#define INTC_IPRG 0xf8080008UL
51
+
52
+
#define INTC_ICR0 0xf8140000UL
53
+
#define INTC_IRQCR 0xf8140002UL
54
+
#define INTC_IRQSR 0xf8140004UL
55
+
56
+
#define CMI0_IRQ 86
57
+
#define CMI1_IRQ 87
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+
59
+
#define SCIF_ERI_IRQ 88
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+
#define SCIF_RXI_IRQ 89
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#define SCIF_BRI_IRQ 90
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#define SCIF_TXI_IRQ 91
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#define SCIF_IPR_ADDR INTC_IPRD
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#define SCIF_IPR_POS 3
65
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#define SCIF_PRIORITY 3
66
+
67
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#define SCIF1_ERI_IRQ 92
68
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#define SCIF1_RXI_IRQ 93
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#define SCIF1_BRI_IRQ 94
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#define SCIF1_TXI_IRQ 95
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#define SCIF1_IPR_ADDR INTC_IPRD
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#define SCIF1_IPR_POS 2
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#define SCIF1_PRIORITY 3
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+
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#define SCIF2_BRI_IRQ 96
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#define SCIF2_RXI_IRQ 97
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#define SCIF2_ERI_IRQ 98
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#define SCIF2_TXI_IRQ 99
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#define SCIF2_IPR_ADDR INTC_IPRD
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#define SCIF2_IPR_POS 1
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#define SCIF2_PRIORITY 3
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#endif
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+
84
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#endif /* __ASM_SH_CPU_SH2_IRQ_H */
+16
include/asm-sh/cpu-sh2/mmu_context.h
+16
include/asm-sh/cpu-sh2/mmu_context.h
···
1
+
/*
2
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* include/asm-sh/cpu-sh2/mmu_context.h
3
+
*
4
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* Copyright (C) 2003 Paul Mundt
5
+
*
6
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* This file is subject to the terms and conditions of the GNU General Public
7
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* License. See the file "COPYING" in the main directory of this archive
8
+
* for more details.
9
+
*/
10
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#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
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#define __ASM_CPU_SH2_MMU_CONTEXT_H
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/* No MMU */
14
+
15
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#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */
16
+
+1
include/asm-sh/cpu-sh2a/addrspace.h
+1
include/asm-sh/cpu-sh2a/addrspace.h
···
1
+
#include <asm/cpu-sh2/addrspace.h>
+39
include/asm-sh/cpu-sh2a/cache.h
+39
include/asm-sh/cpu-sh2a/cache.h
···
1
+
/*
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* include/asm-sh/cpu-sh2a/cache.h
3
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*
4
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* Copyright (C) 2004 Paul Mundt
5
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*
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* This file is subject to the terms and conditions of the GNU General Public
7
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* License. See the file "COPYING" in the main directory of this archive
8
+
* for more details.
9
+
*/
10
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#ifndef __ASM_CPU_SH2A_CACHE_H
11
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#define __ASM_CPU_SH2A_CACHE_H
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+
13
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#define L1_CACHE_SHIFT 4
14
+
15
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#define CCR1 0xfffc1000
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#define CCR2 0xfffc1004
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+
18
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/* CCR1 behaves more like the traditional CCR */
19
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#define CCR CCR1
20
+
21
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/*
22
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* Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
23
+
* listed here are reserved.
24
+
*/
25
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#define CCR_CACHE_CB 0x0000 /* Hack */
26
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#define CCR_CACHE_OCE 0x0001
27
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#define CCR_CACHE_WT 0x0002
28
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#define CCR_CACHE_OCI 0x0008 /* OCF */
29
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#define CCR_CACHE_ICE 0x0100
30
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#define CCR_CACHE_ICI 0x0800 /* ICF */
31
+
32
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#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
33
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#define CACHE_OC_ADDRESS_ARRAY 0xf0800000
34
+
35
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#define CCR_CACHE_ENABLE (CCR_CACHE_OCE | CCR_CACHE_ICE)
36
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#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI | CCR_CACHE_ICI)
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+
38
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#endif /* __ASM_CPU_SH2A_CACHE_H */
39
+
+1
include/asm-sh/cpu-sh2a/cacheflush.h
+1
include/asm-sh/cpu-sh2a/cacheflush.h
···
1
+
#include <asm/cpu-sh2/cacheflush.h>
+1
include/asm-sh/cpu-sh2a/dma.h
+1
include/asm-sh/cpu-sh2a/dma.h
···
1
+
#include <asm/cpu-sh2/dma.h>
+18
include/asm-sh/cpu-sh2a/freq.h
+18
include/asm-sh/cpu-sh2a/freq.h
···
1
+
/*
2
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* include/asm-sh/cpu-sh2a/freq.h
3
+
*
4
+
* Copyright (C) 2006 Yoshinori Sato
5
+
*
6
+
* This file is subject to the terms and conditions of the GNU General Public
7
+
* License. See the file "COPYING" in the main directory of this archive
8
+
* for more details.
9
+
*/
10
+
#ifndef __ASM_CPU_SH2A_FREQ_H
11
+
#define __ASM_CPU_SH2A_FREQ_H
12
+
13
+
#if defined(CONFIG_CPU_SUBTYPE_SH7206)
14
+
#define FREQCR 0xfffe0010
15
+
#endif
16
+
17
+
#endif /* __ASM_CPU_SH2A_FREQ_H */
18
+
+75
include/asm-sh/cpu-sh2a/irq.h
+75
include/asm-sh/cpu-sh2a/irq.h
···
1
+
#ifndef __ASM_SH_CPU_SH2A_IRQ_H
2
+
#define __ASM_SH_CPU_SH2A_IRQ_H
3
+
4
+
#define INTC_IPR01 0xfffe0818UL
5
+
#define INTC_IPR02 0xfffe081aUL
6
+
#define INTC_IPR05 0xfffe0820UL
7
+
#define INTC_IPR06 0xfffe0c00UL
8
+
#define INTC_IPR07 0xfffe0c02UL
9
+
#define INTC_IPR08 0xfffe0c04UL
10
+
#define INTC_IPR09 0xfffe0c06UL
11
+
#define INTC_IPR10 0xfffe0c08UL
12
+
#define INTC_IPR11 0xfffe0c0aUL
13
+
#define INTC_IPR12 0xfffe0c0cUL
14
+
#define INTC_IPR13 0xfffe0c0eUL
15
+
#define INTC_IPR14 0xfffe0c10UL
16
+
17
+
#define INTC_ICR0 0xfffe0800UL
18
+
#define INTC_ICR1 0xfffe0802UL
19
+
#define INTC_ICR2 0xfffe0804UL
20
+
#define INTC_ISR 0xfffe0806UL
21
+
22
+
#define IRQ0_IRQ 64
23
+
#define IRQ1_IRQ 65
24
+
#define IRQ2_IRQ 66
25
+
#define IRQ3_IRQ 67
26
+
#define IRQ4_IRQ 68
27
+
#define IRQ5_IRQ 69
28
+
#define IRQ6_IRQ 70
29
+
#define IRQ7_IRQ 71
30
+
31
+
#define PINT0_IRQ 80
32
+
#define PINT1_IRQ 81
33
+
#define PINT2_IRQ 82
34
+
#define PINT3_IRQ 83
35
+
#define PINT4_IRQ 84
36
+
#define PINT5_IRQ 85
37
+
#define PINT6_IRQ 86
38
+
#define PINT7_IRQ 87
39
+
40
+
#define CMI0_IRQ 140
41
+
#define CMI1_IRQ 141
42
+
43
+
#define SCIF_BRI_IRQ 240
44
+
#define SCIF_ERI_IRQ 241
45
+
#define SCIF_RXI_IRQ 242
46
+
#define SCIF_TXI_IRQ 243
47
+
#define SCIF_IPR_ADDR INTC_IPR14
48
+
#define SCIF_IPR_POS 3
49
+
#define SCIF_PRIORITY 3
50
+
51
+
#define SCIF1_BRI_IRQ 244
52
+
#define SCIF1_ERI_IRQ 245
53
+
#define SCIF1_RXI_IRQ 246
54
+
#define SCIF1_TXI_IRQ 247
55
+
#define SCIF1_IPR_ADDR INTC_IPR14
56
+
#define SCIF1_IPR_POS 2
57
+
#define SCIF1_PRIORITY 3
58
+
59
+
#define SCIF2_BRI_IRQ 248
60
+
#define SCIF2_ERI_IRQ 249
61
+
#define SCIF2_RXI_IRQ 250
62
+
#define SCIF2_TXI_IRQ 251
63
+
#define SCIF2_IPR_ADDR INTC_IPR14
64
+
#define SCIF2_IPR_POS 1
65
+
#define SCIF2_PRIORITY 3
66
+
67
+
#define SCIF3_BRI_IRQ 252
68
+
#define SCIF3_ERI_IRQ 253
69
+
#define SCIF3_RXI_IRQ 254
70
+
#define SCIF3_TXI_IRQ 255
71
+
#define SCIF3_IPR_ADDR INTC_IPR14
72
+
#define SCIF3_IPR_POS 0
73
+
#define SCIF3_PRIORITY 3
74
+
75
+
#endif /* __ASM_SH_CPU_SH2A_IRQ_H */
+1
include/asm-sh/cpu-sh2a/mmu_context.h
+1
include/asm-sh/cpu-sh2a/mmu_context.h
···
1
+
#include <asm/cpu-sh2/mmu_context.h>
+1
include/asm-sh/cpu-sh2a/timer.h
+1
include/asm-sh/cpu-sh2a/timer.h
···
1
+
#include <asm/cpu-sh2/timer.h>
+1
include/asm-sh/cpu-sh2a/ubc.h
+1
include/asm-sh/cpu-sh2a/ubc.h
···
1
+
#include <asm/cpu-sh2/ubc.h>
+1
include/asm-sh/cpu-sh2a/watchdog.h
+1
include/asm-sh/cpu-sh2a/watchdog.h
···
1
+
#include <asm/cpu-sh2/watchdog.h>
+32
include/asm-sh/entry-macros.S
+32
include/asm-sh/entry-macros.S
···
1
+
! entry.S macro define
2
+
3
+
.macro cli
4
+
stc sr, r0
5
+
or #0xf0, r0
6
+
ldc r0, sr
7
+
.endm
8
+
9
+
.macro sti
10
+
mov #0xf0, r11
11
+
extu.b r11, r11
12
+
not r11, r11
13
+
stc sr, r10
14
+
and r11, r10
15
+
#ifdef CONFIG_HAS_SR_RB
16
+
stc k_g_imask, r11
17
+
or r11, r10
18
+
#endif
19
+
ldc r10, sr
20
+
.endm
21
+
22
+
.macro get_current_thread_info, ti, tmp
23
+
#ifdef CONFIG_HAS_SR_RB
24
+
stc r7_bank, \ti
25
+
#else
26
+
mov #((THREAD_SIZE - 1)>> 8) ^ 0xff, \tmp
27
+
shll8 \tmp
28
+
mov r15, \ti
29
+
and \tmp, \ti
30
+
#endif
31
+
.endm
32
+
+70
include/asm-sh/irq.h
+70
include/asm-sh/irq.h
···
14
14
#include <asm/machvec.h>
15
15
#include <asm/ptrace.h> /* for pt_regs */
16
16
17
+
#if defined(CONFIG_CPU_SH2)
18
+
#include <asm/cpu/irq.h>
19
+
#endif
20
+
17
21
#ifndef CONFIG_CPU_SUBTYPE_SH7780
18
22
19
23
#define INTC_DMAC0_MSK 0
···
32
28
#define INTC_IPRD 0xffd00010UL
33
29
#endif
34
30
31
+
#if defined(CONFIG_CPU_SUBTYPE_SH7206)
32
+
#ifdef CONFIG_SH_CMT
33
+
#define TIMER_IRQ CMI0_IRQ
34
+
#define TIMER_IPR_ADDR INTC_IPR08
35
+
#define TIMER_IPR_POS 3
36
+
#define TIMER_PRIORITY 2
37
+
38
+
#define TIMER1_IRQ CMI1_IRQ
39
+
#define TIMER1_IPR_ADDR INTC_IPR08
40
+
#define TIMER1_IPR_POS 2
41
+
#define TIMER1_PRIORITY 2
42
+
#endif
43
+
44
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
45
+
#define TIMER_IRQ CMI0_IRQ
46
+
#define TIMER_IPR_ADDR INTC_IPRC
47
+
#define TIMER_IPR_POS 1
48
+
#define TIMER_PRIORITY 2
49
+
50
+
#define TIMER1_IRQ CMI1_IRQ
51
+
#define TIMER1_IPR_ADDR INTC_IPRC
52
+
#define TIMER1_IPR_POS 0
53
+
#define TIMER1_PRIORITY 4
54
+
55
+
#else
35
56
#define TIMER_IRQ 16
36
57
#define TIMER_IPR_ADDR INTC_IPRA
37
58
#define TIMER_IPR_POS 3
···
66
37
#define TIMER1_IPR_ADDR INTC_IPRA
67
38
#define TIMER1_IPR_POS 2
68
39
#define TIMER1_PRIORITY 4
40
+
#endif
69
41
42
+
#if !defined(CONFIG_CPU_SH2)
70
43
#define RTC_IRQ 22
71
44
#define RTC_IPR_ADDR INTC_IPRA
72
45
#define RTC_IPR_POS 0
73
46
#define RTC_PRIORITY TIMER_PRIORITY
47
+
#endif
74
48
75
49
#if defined(CONFIG_CPU_SH3)
76
50
#define DMTE0_IRQ 48
···
297
265
# define ONCHIP_NR_IRQS 109
298
266
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
299
267
# define ONCHIP_NR_IRQS 111
268
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
269
+
# define ONCHIP_NR_IRQS 256
270
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
271
+
# define ONCHIP_NR_IRQS 128
300
272
#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
301
273
# define ONCHIP_NR_IRQS 144
302
274
#endif
···
357
321
*/
358
322
extern void make_maskreg_irq(unsigned int irq);
359
323
extern unsigned short *irq_mask_register;
324
+
325
+
#if defined(CONFIG_CPU_SUBTYPE_SH7619)
326
+
#define IRQ0_IRQ 16
327
+
#define IRQ1_IRQ 17
328
+
#define IRQ2_IRQ 18
329
+
#define IRQ3_IRQ 19
330
+
#define IRQ4_IRQ 32
331
+
#define IRQ5_IRQ 33
332
+
#define IRQ6_IRQ 34
333
+
#define IRQ7_IRQ 35
334
+
#elif !defined(CONFIG_CPU_SUBTYPE_SH7206)
335
+
#define IRQ0_IRQ 32
336
+
#define IRQ1_IRQ 33
337
+
#define IRQ2_IRQ 34
338
+
#define IRQ3_IRQ 35
339
+
#define IRQ4_IRQ 36
340
+
#define IRQ5_IRQ 37
341
+
#endif
342
+
343
+
#define IRQ0_PRIORITY 1
344
+
#define IRQ1_PRIORITY 1
345
+
#define IRQ2_PRIORITY 1
346
+
#define IRQ3_PRIORITY 1
347
+
#define IRQ4_PRIORITY 1
348
+
#define IRQ5_PRIORITY 1
349
+
350
+
#ifndef IRQ0_IPR_POS
351
+
#define IRQ0_IPR_POS 0
352
+
#define IRQ1_IPR_POS 1
353
+
#define IRQ2_IPR_POS 2
354
+
#define IRQ3_IPR_POS 3
355
+
#define IRQ4_IPR_POS 0
356
+
#define IRQ5_IPR_POS 1
357
+
#endif
360
358
361
359
/*
362
360
* PINT IRQs
+4
-1
include/asm-sh/processor.h
+4
-1
include/asm-sh/processor.h
+25
-7
include/asm-sh/unistd.h
+25
-7
include/asm-sh/unistd.h
···
349
349
return (type) (res); \
350
350
} while (0)
351
351
352
+
#if defined(__sh2__) || defined(__SH2E__) || defined(__SH2A__)
353
+
#define SYSCALL_ARG0 "trapa #0x20"
354
+
#define SYSCALL_ARG1 "trapa #0x21"
355
+
#define SYSCALL_ARG2 "trapa #0x22"
356
+
#define SYSCALL_ARG3 "trapa #0x23"
357
+
#define SYSCALL_ARG4 "trapa #0x24"
358
+
#define SYSCALL_ARG5 "trapa #0x25"
359
+
#define SYSCALL_ARG6 "trapa #0x26"
360
+
#else
361
+
#define SYSCALL_ARG0 "trapa #0x10"
362
+
#define SYSCALL_ARG1 "trapa #0x11"
363
+
#define SYSCALL_ARG2 "trapa #0x12"
364
+
#define SYSCALL_ARG3 "trapa #0x13"
365
+
#define SYSCALL_ARG4 "trapa #0x14"
366
+
#define SYSCALL_ARG5 "trapa #0x15"
367
+
#define SYSCALL_ARG6 "trapa #0x16"
368
+
#endif
369
+
352
370
/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
353
371
#define _syscall0(type,name) \
354
372
type name(void) \
355
373
{ \
356
374
register long __sc0 __asm__ ("r3") = __NR_##name; \
357
-
__asm__ __volatile__ ("trapa #0x10" \
375
+
__asm__ __volatile__ (SYSCALL_ARG0 \
358
376
: "=z" (__sc0) \
359
377
: "0" (__sc0) \
360
378
: "memory" ); \
···
384
366
{ \
385
367
register long __sc0 __asm__ ("r3") = __NR_##name; \
386
368
register long __sc4 __asm__ ("r4") = (long) arg1; \
387
-
__asm__ __volatile__ ("trapa #0x11" \
369
+
__asm__ __volatile__ (SYSCALL_ARG1 \
388
370
: "=z" (__sc0) \
389
371
: "0" (__sc0), "r" (__sc4) \
390
372
: "memory"); \
···
397
379
register long __sc0 __asm__ ("r3") = __NR_##name; \
398
380
register long __sc4 __asm__ ("r4") = (long) arg1; \
399
381
register long __sc5 __asm__ ("r5") = (long) arg2; \
400
-
__asm__ __volatile__ ("trapa #0x12" \
382
+
__asm__ __volatile__ (SYSCALL_ARG2 \
401
383
: "=z" (__sc0) \
402
384
: "0" (__sc0), "r" (__sc4), "r" (__sc5) \
403
385
: "memory"); \
···
411
393
register long __sc4 __asm__ ("r4") = (long) arg1; \
412
394
register long __sc5 __asm__ ("r5") = (long) arg2; \
413
395
register long __sc6 __asm__ ("r6") = (long) arg3; \
414
-
__asm__ __volatile__ ("trapa #0x13" \
396
+
__asm__ __volatile__ (SYSCALL_ARG3 \
415
397
: "=z" (__sc0) \
416
398
: "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6) \
417
399
: "memory"); \
···
426
408
register long __sc5 __asm__ ("r5") = (long) arg2; \
427
409
register long __sc6 __asm__ ("r6") = (long) arg3; \
428
410
register long __sc7 __asm__ ("r7") = (long) arg4; \
429
-
__asm__ __volatile__ ("trapa #0x14" \
411
+
__asm__ __volatile__ (SYSCALL_ARG4 \
430
412
: "=z" (__sc0) \
431
413
: "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), \
432
414
"r" (__sc7) \
···
443
425
register long __sc6 __asm__ ("r6") = (long) arg3; \
444
426
register long __sc7 __asm__ ("r7") = (long) arg4; \
445
427
register long __sc0 __asm__ ("r0") = (long) arg5; \
446
-
__asm__ __volatile__ ("trapa #0x15" \
428
+
__asm__ __volatile__ (SYSCALL_ARG5 \
447
429
: "=z" (__sc0) \
448
430
: "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \
449
431
"r" (__sc3) \
···
461
443
register long __sc7 __asm__ ("r7") = (long) arg4; \
462
444
register long __sc0 __asm__ ("r0") = (long) arg5; \
463
445
register long __sc1 __asm__ ("r1") = (long) arg6; \
464
-
__asm__ __volatile__ ("trapa #0x16" \
446
+
__asm__ __volatile__ (SYSCALL_ARG6 \
465
447
: "=z" (__sc0) \
466
448
: "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \
467
449
"r" (__sc3), "r" (__sc1) \