Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

mfd: tps80031: Remove driver

Driver was upstreamed in 2013 and never got a user, remove it.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211021192258.21968-4-digetx@gmail.com

authored by

Dmitry Osipenko and committed by
Lee Jones
b20cd02f 0cee0416

-1178
-14
drivers/mfd/Kconfig
··· 1624 1624 If you say yes here you get support for the TPS65912 series of 1625 1625 PM chips with SPI interface. 1626 1626 1627 - config MFD_TPS80031 1628 - bool "TI TPS80031/TPS80032 Power Management chips" 1629 - depends on I2C=y 1630 - select MFD_CORE 1631 - select REGMAP_I2C 1632 - select REGMAP_IRQ 1633 - help 1634 - If you say yes here you get support for the Texas Instruments 1635 - TPS80031/ TPS80032 Fully Integrated Power Management with Power 1636 - Path and Battery Charger. The device provides five configurable 1637 - step-down converters, 11 general purpose LDOs, USB OTG Module, 1638 - ADC, RTC, 2 PWM, System Voltage Regulator/Battery Charger with 1639 - Power Path from USB, 32K clock generator. 1640 - 1641 1627 config TWL4030_CORE 1642 1628 bool "TI TWL4030/TWL5030/TWL6030/TPS659x0 Support" 1643 1629 depends on I2C=y
-1
drivers/mfd/Makefile
··· 105 105 obj-$(CONFIG_MFD_TPS65912) += tps65912-core.o 106 106 obj-$(CONFIG_MFD_TPS65912_I2C) += tps65912-i2c.o 107 107 obj-$(CONFIG_MFD_TPS65912_SPI) += tps65912-spi.o 108 - obj-$(CONFIG_MFD_TPS80031) += tps80031.o 109 108 obj-$(CONFIG_MENELAUS) += menelaus.o 110 109 111 110 obj-$(CONFIG_TWL4030_CORE) += twl-core.o twl4030-irq.o twl6030-irq.o
-526
drivers/mfd/tps80031.c
··· 1 - /* 2 - * tps80031.c -- TI TPS80031/TPS80032 mfd core driver. 3 - * 4 - * MFD core driver for TI TPS80031/TPS80032 Fully Integrated 5 - * Power Management with Power Path and Battery Charger 6 - * 7 - * Copyright (c) 2012, NVIDIA Corporation. 8 - * 9 - * Author: Laxman Dewangan <ldewangan@nvidia.com> 10 - * 11 - * This program is free software; you can redistribute it and/or 12 - * modify it under the terms of the GNU General Public License as 13 - * published by the Free Software Foundation version 2. 14 - * 15 - * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, 16 - * whether express or implied; without even the implied warranty of 17 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 - * General Public License for more details. 19 - * 20 - * You should have received a copy of the GNU General Public License 21 - * along with this program; if not, write to the Free Software 22 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 23 - * 02111-1307, USA 24 - */ 25 - 26 - #include <linux/err.h> 27 - #include <linux/i2c.h> 28 - #include <linux/init.h> 29 - #include <linux/interrupt.h> 30 - #include <linux/irq.h> 31 - #include <linux/mfd/core.h> 32 - #include <linux/mfd/tps80031.h> 33 - #include <linux/pm.h> 34 - #include <linux/regmap.h> 35 - #include <linux/slab.h> 36 - 37 - static const struct resource tps80031_rtc_resources[] = { 38 - DEFINE_RES_IRQ(TPS80031_INT_RTC_ALARM), 39 - }; 40 - 41 - /* TPS80031 sub mfd devices */ 42 - static const struct mfd_cell tps80031_cell[] = { 43 - { 44 - .name = "tps80031-pmic", 45 - }, 46 - { 47 - .name = "tps80031-clock", 48 - }, 49 - { 50 - .name = "tps80031-rtc", 51 - .num_resources = ARRAY_SIZE(tps80031_rtc_resources), 52 - .resources = tps80031_rtc_resources, 53 - }, 54 - { 55 - .name = "tps80031-gpadc", 56 - }, 57 - { 58 - .name = "tps80031-fuel-gauge", 59 - }, 60 - { 61 - .name = "tps80031-charger", 62 - }, 63 - }; 64 - 65 - static int tps80031_slave_address[TPS80031_NUM_SLAVES] = { 66 - TPS80031_I2C_ID0_ADDR, 67 - TPS80031_I2C_ID1_ADDR, 68 - TPS80031_I2C_ID2_ADDR, 69 - TPS80031_I2C_ID3_ADDR, 70 - }; 71 - 72 - struct tps80031_pupd_data { 73 - u8 reg; 74 - u8 pullup_bit; 75 - u8 pulldown_bit; 76 - }; 77 - 78 - #define TPS80031_IRQ(_reg, _mask) \ 79 - { \ 80 - .reg_offset = (TPS80031_INT_MSK_LINE_##_reg) - \ 81 - TPS80031_INT_MSK_LINE_A, \ 82 - .mask = BIT(_mask), \ 83 - } 84 - 85 - static const struct regmap_irq tps80031_main_irqs[] = { 86 - [TPS80031_INT_PWRON] = TPS80031_IRQ(A, 0), 87 - [TPS80031_INT_RPWRON] = TPS80031_IRQ(A, 1), 88 - [TPS80031_INT_SYS_VLOW] = TPS80031_IRQ(A, 2), 89 - [TPS80031_INT_RTC_ALARM] = TPS80031_IRQ(A, 3), 90 - [TPS80031_INT_RTC_PERIOD] = TPS80031_IRQ(A, 4), 91 - [TPS80031_INT_HOT_DIE] = TPS80031_IRQ(A, 5), 92 - [TPS80031_INT_VXX_SHORT] = TPS80031_IRQ(A, 6), 93 - [TPS80031_INT_SPDURATION] = TPS80031_IRQ(A, 7), 94 - [TPS80031_INT_WATCHDOG] = TPS80031_IRQ(B, 0), 95 - [TPS80031_INT_BAT] = TPS80031_IRQ(B, 1), 96 - [TPS80031_INT_SIM] = TPS80031_IRQ(B, 2), 97 - [TPS80031_INT_MMC] = TPS80031_IRQ(B, 3), 98 - [TPS80031_INT_RES] = TPS80031_IRQ(B, 4), 99 - [TPS80031_INT_GPADC_RT] = TPS80031_IRQ(B, 5), 100 - [TPS80031_INT_GPADC_SW2_EOC] = TPS80031_IRQ(B, 6), 101 - [TPS80031_INT_CC_AUTOCAL] = TPS80031_IRQ(B, 7), 102 - [TPS80031_INT_ID_WKUP] = TPS80031_IRQ(C, 0), 103 - [TPS80031_INT_VBUSS_WKUP] = TPS80031_IRQ(C, 1), 104 - [TPS80031_INT_ID] = TPS80031_IRQ(C, 2), 105 - [TPS80031_INT_VBUS] = TPS80031_IRQ(C, 3), 106 - [TPS80031_INT_CHRG_CTRL] = TPS80031_IRQ(C, 4), 107 - [TPS80031_INT_EXT_CHRG] = TPS80031_IRQ(C, 5), 108 - [TPS80031_INT_INT_CHRG] = TPS80031_IRQ(C, 6), 109 - [TPS80031_INT_RES2] = TPS80031_IRQ(C, 7), 110 - }; 111 - 112 - static struct regmap_irq_chip tps80031_irq_chip = { 113 - .name = "tps80031", 114 - .irqs = tps80031_main_irqs, 115 - .num_irqs = ARRAY_SIZE(tps80031_main_irqs), 116 - .num_regs = 3, 117 - .status_base = TPS80031_INT_STS_A, 118 - .mask_base = TPS80031_INT_MSK_LINE_A, 119 - }; 120 - 121 - #define PUPD_DATA(_reg, _pulldown_bit, _pullup_bit) \ 122 - { \ 123 - .reg = TPS80031_CFG_INPUT_PUPD##_reg, \ 124 - .pulldown_bit = _pulldown_bit, \ 125 - .pullup_bit = _pullup_bit, \ 126 - } 127 - 128 - static const struct tps80031_pupd_data tps80031_pupds[] = { 129 - [TPS80031_PREQ1] = PUPD_DATA(1, BIT(0), BIT(1)), 130 - [TPS80031_PREQ2A] = PUPD_DATA(1, BIT(2), BIT(3)), 131 - [TPS80031_PREQ2B] = PUPD_DATA(1, BIT(4), BIT(5)), 132 - [TPS80031_PREQ2C] = PUPD_DATA(1, BIT(6), BIT(7)), 133 - [TPS80031_PREQ3] = PUPD_DATA(2, BIT(0), BIT(1)), 134 - [TPS80031_NRES_WARM] = PUPD_DATA(2, 0, BIT(2)), 135 - [TPS80031_PWM_FORCE] = PUPD_DATA(2, BIT(5), 0), 136 - [TPS80031_CHRG_EXT_CHRG_STATZ] = PUPD_DATA(2, 0, BIT(6)), 137 - [TPS80031_SIM] = PUPD_DATA(3, BIT(0), BIT(1)), 138 - [TPS80031_MMC] = PUPD_DATA(3, BIT(2), BIT(3)), 139 - [TPS80031_GPADC_START] = PUPD_DATA(3, BIT(4), 0), 140 - [TPS80031_DVSI2C_SCL] = PUPD_DATA(4, 0, BIT(0)), 141 - [TPS80031_DVSI2C_SDA] = PUPD_DATA(4, 0, BIT(1)), 142 - [TPS80031_CTLI2C_SCL] = PUPD_DATA(4, 0, BIT(2)), 143 - [TPS80031_CTLI2C_SDA] = PUPD_DATA(4, 0, BIT(3)), 144 - }; 145 - static struct tps80031 *tps80031_power_off_dev; 146 - 147 - int tps80031_ext_power_req_config(struct device *dev, 148 - unsigned long ext_ctrl_flag, int preq_bit, 149 - int state_reg_add, int trans_reg_add) 150 - { 151 - u8 res_ass_reg = 0; 152 - int preq_mask_bit = 0; 153 - int ret; 154 - 155 - if (!(ext_ctrl_flag & TPS80031_EXT_PWR_REQ)) 156 - return 0; 157 - 158 - if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ1) { 159 - res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3); 160 - preq_mask_bit = 5; 161 - } else if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ2) { 162 - res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3); 163 - preq_mask_bit = 6; 164 - } else if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ3) { 165 - res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3); 166 - preq_mask_bit = 7; 167 - } 168 - 169 - /* Configure REQ_ASS registers */ 170 - ret = tps80031_set_bits(dev, TPS80031_SLAVE_ID1, res_ass_reg, 171 - BIT(preq_bit & 0x7)); 172 - if (ret < 0) { 173 - dev_err(dev, "reg 0x%02x setbit failed, err = %d\n", 174 - res_ass_reg, ret); 175 - return ret; 176 - } 177 - 178 - /* Unmask the PREQ */ 179 - ret = tps80031_clr_bits(dev, TPS80031_SLAVE_ID1, 180 - TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit)); 181 - if (ret < 0) { 182 - dev_err(dev, "reg 0x%02x clrbit failed, err = %d\n", 183 - TPS80031_PHOENIX_MSK_TRANSITION, ret); 184 - return ret; 185 - } 186 - 187 - /* Switch regulator control to resource now */ 188 - if (ext_ctrl_flag & (TPS80031_PWR_REQ_INPUT_PREQ2 | 189 - TPS80031_PWR_REQ_INPUT_PREQ3)) { 190 - ret = tps80031_update(dev, TPS80031_SLAVE_ID1, state_reg_add, 191 - 0x0, TPS80031_STATE_MASK); 192 - if (ret < 0) 193 - dev_err(dev, "reg 0x%02x update failed, err = %d\n", 194 - state_reg_add, ret); 195 - } else { 196 - ret = tps80031_update(dev, TPS80031_SLAVE_ID1, trans_reg_add, 197 - TPS80031_TRANS_SLEEP_OFF, 198 - TPS80031_TRANS_SLEEP_MASK); 199 - if (ret < 0) 200 - dev_err(dev, "reg 0x%02x update failed, err = %d\n", 201 - trans_reg_add, ret); 202 - } 203 - return ret; 204 - } 205 - EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config); 206 - 207 - static void tps80031_power_off(void) 208 - { 209 - dev_info(tps80031_power_off_dev->dev, "switching off PMU\n"); 210 - tps80031_write(tps80031_power_off_dev->dev, TPS80031_SLAVE_ID1, 211 - TPS80031_PHOENIX_DEV_ON, TPS80031_DEVOFF); 212 - } 213 - 214 - static void tps80031_pupd_init(struct tps80031 *tps80031, 215 - struct tps80031_platform_data *pdata) 216 - { 217 - struct tps80031_pupd_init_data *pupd_init_data = pdata->pupd_init_data; 218 - int data_size = pdata->pupd_init_data_size; 219 - int i; 220 - 221 - for (i = 0; i < data_size; ++i) { 222 - struct tps80031_pupd_init_data *pupd_init = &pupd_init_data[i]; 223 - const struct tps80031_pupd_data *pupd = 224 - &tps80031_pupds[pupd_init->input_pin]; 225 - u8 update_value = 0; 226 - u8 update_mask = pupd->pulldown_bit | pupd->pullup_bit; 227 - 228 - if (pupd_init->setting == TPS80031_PUPD_PULLDOWN) 229 - update_value = pupd->pulldown_bit; 230 - else if (pupd_init->setting == TPS80031_PUPD_PULLUP) 231 - update_value = pupd->pullup_bit; 232 - 233 - tps80031_update(tps80031->dev, TPS80031_SLAVE_ID1, pupd->reg, 234 - update_value, update_mask); 235 - } 236 - } 237 - 238 - static int tps80031_init_ext_control(struct tps80031 *tps80031, 239 - struct tps80031_platform_data *pdata) 240 - { 241 - struct device *dev = tps80031->dev; 242 - int ret; 243 - int i; 244 - 245 - /* Clear all external control for this rail */ 246 - for (i = 0; i < 9; ++i) { 247 - ret = tps80031_write(dev, TPS80031_SLAVE_ID1, 248 - TPS80031_PREQ1_RES_ASS_A + i, 0); 249 - if (ret < 0) { 250 - dev_err(dev, "reg 0x%02x write failed, err = %d\n", 251 - TPS80031_PREQ1_RES_ASS_A + i, ret); 252 - return ret; 253 - } 254 - } 255 - 256 - /* Mask the PREQ */ 257 - ret = tps80031_set_bits(dev, TPS80031_SLAVE_ID1, 258 - TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5); 259 - if (ret < 0) { 260 - dev_err(dev, "reg 0x%02x set_bits failed, err = %d\n", 261 - TPS80031_PHOENIX_MSK_TRANSITION, ret); 262 - return ret; 263 - } 264 - return ret; 265 - } 266 - 267 - static int tps80031_irq_init(struct tps80031 *tps80031, int irq, int irq_base) 268 - { 269 - struct device *dev = tps80031->dev; 270 - int i, ret; 271 - 272 - /* 273 - * The MASK register used for updating status register when 274 - * interrupt occurs and LINE register used to pass the status 275 - * to actual interrupt line. As per datasheet: 276 - * When INT_MSK_LINE [i] is set to 1, the associated interrupt 277 - * number i is INT line masked, which means that no interrupt is 278 - * generated on the INT line. 279 - * When INT_MSK_LINE [i] is set to 0, the associated interrupt 280 - * number i is line enabled: An interrupt is generated on the 281 - * INT line. 282 - * In any case, the INT_STS [i] status bit may or may not be updated, 283 - * only linked to the INT_MSK_STS [i] configuration register bit. 284 - * 285 - * When INT_MSK_STS [i] is set to 1, the associated interrupt number 286 - * i is status masked, which means that no interrupt is stored in 287 - * the INT_STS[i] status bit. Note that no interrupt number i is 288 - * generated on the INT line, even if the INT_MSK_LINE [i] register 289 - * bit is set to 0. 290 - * When INT_MSK_STS [i] is set to 0, the associated interrupt number i 291 - * is status enabled: An interrupt status is updated in the INT_STS [i] 292 - * register. The interrupt may or may not be generated on the INT line, 293 - * depending on the INT_MSK_LINE [i] configuration register bit. 294 - */ 295 - for (i = 0; i < 3; i++) 296 - tps80031_write(dev, TPS80031_SLAVE_ID2, 297 - TPS80031_INT_MSK_STS_A + i, 0x00); 298 - 299 - ret = regmap_add_irq_chip(tps80031->regmap[TPS80031_SLAVE_ID2], irq, 300 - IRQF_ONESHOT, irq_base, 301 - &tps80031_irq_chip, &tps80031->irq_data); 302 - if (ret < 0) { 303 - dev_err(dev, "add irq failed, err = %d\n", ret); 304 - return ret; 305 - } 306 - return ret; 307 - } 308 - 309 - static bool rd_wr_reg_id0(struct device *dev, unsigned int reg) 310 - { 311 - switch (reg) { 312 - case TPS80031_SMPS1_CFG_FORCE ... TPS80031_SMPS2_CFG_VOLTAGE: 313 - return true; 314 - default: 315 - return false; 316 - } 317 - } 318 - 319 - static bool rd_wr_reg_id1(struct device *dev, unsigned int reg) 320 - { 321 - switch (reg) { 322 - case TPS80031_SECONDS_REG ... TPS80031_RTC_RESET_STATUS_REG: 323 - case TPS80031_VALIDITY0 ... TPS80031_VALIDITY7: 324 - case TPS80031_PHOENIX_START_CONDITION ... TPS80031_KEY_PRESS_DUR_CFG: 325 - case TPS80031_SMPS4_CFG_TRANS ... TPS80031_SMPS3_CFG_VOLTAGE: 326 - case TPS80031_BROADCAST_ADDR_ALL ... TPS80031_BROADCAST_ADDR_CLK_RST: 327 - case TPS80031_VANA_CFG_TRANS ... TPS80031_LDO7_CFG_VOLTAGE: 328 - case TPS80031_REGEN1_CFG_TRANS ... TPS80031_TMP_CFG_STATE: 329 - case TPS80031_PREQ1_RES_ASS_A ... TPS80031_PREQ3_RES_ASS_C: 330 - case TPS80031_SMPS_OFFSET ... TPS80031_BATDEBOUNCING: 331 - case TPS80031_CFG_INPUT_PUPD1 ... TPS80031_CFG_SMPS_PD: 332 - case TPS80031_BACKUP_REG: 333 - return true; 334 - default: 335 - return false; 336 - } 337 - } 338 - 339 - static bool is_volatile_reg_id1(struct device *dev, unsigned int reg) 340 - { 341 - switch (reg) { 342 - case TPS80031_SMPS4_CFG_TRANS ... TPS80031_SMPS3_CFG_VOLTAGE: 343 - case TPS80031_VANA_CFG_TRANS ... TPS80031_LDO7_CFG_VOLTAGE: 344 - case TPS80031_REGEN1_CFG_TRANS ... TPS80031_TMP_CFG_STATE: 345 - case TPS80031_PREQ1_RES_ASS_A ... TPS80031_PREQ3_RES_ASS_C: 346 - case TPS80031_SMPS_OFFSET ... TPS80031_BATDEBOUNCING: 347 - case TPS80031_CFG_INPUT_PUPD1 ... TPS80031_CFG_SMPS_PD: 348 - return true; 349 - default: 350 - return false; 351 - } 352 - } 353 - 354 - static bool rd_wr_reg_id2(struct device *dev, unsigned int reg) 355 - { 356 - switch (reg) { 357 - case TPS80031_USB_VENDOR_ID_LSB ... TPS80031_USB_OTG_REVISION: 358 - case TPS80031_GPADC_CTRL ... TPS80031_CTRL_P1: 359 - case TPS80031_RTCH0_LSB ... TPS80031_GPCH0_MSB: 360 - case TPS80031_TOGGLE1 ... TPS80031_VIBMODE: 361 - case TPS80031_PWM1ON ... TPS80031_PWM2OFF: 362 - case TPS80031_FG_REG_00 ... TPS80031_FG_REG_11: 363 - case TPS80031_INT_STS_A ... TPS80031_INT_MSK_STS_C: 364 - case TPS80031_CONTROLLER_CTRL2 ... TPS80031_LED_PWM_CTRL2: 365 - return true; 366 - default: 367 - return false; 368 - } 369 - } 370 - 371 - static bool rd_wr_reg_id3(struct device *dev, unsigned int reg) 372 - { 373 - switch (reg) { 374 - case TPS80031_GPADC_TRIM0 ... TPS80031_GPADC_TRIM18: 375 - return true; 376 - default: 377 - return false; 378 - } 379 - } 380 - 381 - static const struct regmap_config tps80031_regmap_configs[] = { 382 - { 383 - .reg_bits = 8, 384 - .val_bits = 8, 385 - .writeable_reg = rd_wr_reg_id0, 386 - .readable_reg = rd_wr_reg_id0, 387 - .max_register = TPS80031_MAX_REGISTER, 388 - }, 389 - { 390 - .reg_bits = 8, 391 - .val_bits = 8, 392 - .writeable_reg = rd_wr_reg_id1, 393 - .readable_reg = rd_wr_reg_id1, 394 - .volatile_reg = is_volatile_reg_id1, 395 - .max_register = TPS80031_MAX_REGISTER, 396 - }, 397 - { 398 - .reg_bits = 8, 399 - .val_bits = 8, 400 - .writeable_reg = rd_wr_reg_id2, 401 - .readable_reg = rd_wr_reg_id2, 402 - .max_register = TPS80031_MAX_REGISTER, 403 - }, 404 - { 405 - .reg_bits = 8, 406 - .val_bits = 8, 407 - .writeable_reg = rd_wr_reg_id3, 408 - .readable_reg = rd_wr_reg_id3, 409 - .max_register = TPS80031_MAX_REGISTER, 410 - }, 411 - }; 412 - 413 - static int tps80031_probe(struct i2c_client *client, 414 - const struct i2c_device_id *id) 415 - { 416 - struct tps80031_platform_data *pdata = dev_get_platdata(&client->dev); 417 - struct tps80031 *tps80031; 418 - int ret; 419 - uint8_t es_version; 420 - uint8_t ep_ver; 421 - int i; 422 - 423 - if (!pdata) { 424 - dev_err(&client->dev, "tps80031 requires platform data\n"); 425 - return -EINVAL; 426 - } 427 - 428 - tps80031 = devm_kzalloc(&client->dev, sizeof(*tps80031), GFP_KERNEL); 429 - if (!tps80031) 430 - return -ENOMEM; 431 - 432 - for (i = 0; i < TPS80031_NUM_SLAVES; i++) { 433 - if (tps80031_slave_address[i] == client->addr) 434 - tps80031->clients[i] = client; 435 - else 436 - tps80031->clients[i] = devm_i2c_new_dummy_device(&client->dev, 437 - client->adapter, tps80031_slave_address[i]); 438 - if (IS_ERR(tps80031->clients[i])) { 439 - dev_err(&client->dev, "can't attach client %d\n", i); 440 - return PTR_ERR(tps80031->clients[i]); 441 - } 442 - 443 - i2c_set_clientdata(tps80031->clients[i], tps80031); 444 - tps80031->regmap[i] = devm_regmap_init_i2c(tps80031->clients[i], 445 - &tps80031_regmap_configs[i]); 446 - if (IS_ERR(tps80031->regmap[i])) { 447 - ret = PTR_ERR(tps80031->regmap[i]); 448 - dev_err(&client->dev, 449 - "regmap %d init failed, err %d\n", i, ret); 450 - return ret; 451 - } 452 - } 453 - 454 - ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3, 455 - TPS80031_JTAGVERNUM, &es_version); 456 - if (ret < 0) { 457 - dev_err(&client->dev, 458 - "Silicon version number read failed: %d\n", ret); 459 - return ret; 460 - } 461 - 462 - ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3, 463 - TPS80031_EPROM_REV, &ep_ver); 464 - if (ret < 0) { 465 - dev_err(&client->dev, 466 - "Silicon eeprom version read failed: %d\n", ret); 467 - return ret; 468 - } 469 - 470 - dev_info(&client->dev, "ES version 0x%02x and EPROM version 0x%02x\n", 471 - es_version, ep_ver); 472 - tps80031->es_version = es_version; 473 - tps80031->dev = &client->dev; 474 - i2c_set_clientdata(client, tps80031); 475 - tps80031->chip_info = id->driver_data; 476 - 477 - ret = tps80031_irq_init(tps80031, client->irq, pdata->irq_base); 478 - if (ret) { 479 - dev_err(&client->dev, "IRQ init failed: %d\n", ret); 480 - return ret; 481 - } 482 - 483 - tps80031_pupd_init(tps80031, pdata); 484 - 485 - tps80031_init_ext_control(tps80031, pdata); 486 - 487 - ret = mfd_add_devices(tps80031->dev, -1, 488 - tps80031_cell, ARRAY_SIZE(tps80031_cell), 489 - NULL, 0, 490 - regmap_irq_get_domain(tps80031->irq_data)); 491 - if (ret < 0) { 492 - dev_err(&client->dev, "mfd_add_devices failed: %d\n", ret); 493 - goto fail_mfd_add; 494 - } 495 - 496 - if (pdata->use_power_off && !pm_power_off) { 497 - tps80031_power_off_dev = tps80031; 498 - pm_power_off = tps80031_power_off; 499 - } 500 - return 0; 501 - 502 - fail_mfd_add: 503 - regmap_del_irq_chip(client->irq, tps80031->irq_data); 504 - return ret; 505 - } 506 - 507 - static const struct i2c_device_id tps80031_id_table[] = { 508 - { "tps80031", TPS80031 }, 509 - { "tps80032", TPS80032 }, 510 - { } 511 - }; 512 - 513 - static struct i2c_driver tps80031_driver = { 514 - .driver = { 515 - .name = "tps80031", 516 - .suppress_bind_attrs = true, 517 - }, 518 - .probe = tps80031_probe, 519 - .id_table = tps80031_id_table, 520 - }; 521 - 522 - static int __init tps80031_init(void) 523 - { 524 - return i2c_add_driver(&tps80031_driver); 525 - } 526 - subsys_initcall(tps80031_init);
-637
include/linux/mfd/tps80031.h
··· 1 - /* 2 - * tps80031.h -- TI TPS80031 and TI TPS80032 PMIC driver. 3 - * 4 - * Copyright (c) 2012, NVIDIA Corporation. 5 - * 6 - * Author: Laxman Dewangan <ldewangan@nvidia.com> 7 - * 8 - * This program is free software; you can redistribute it and/or 9 - * modify it under the terms of the GNU General Public License as 10 - * published by the Free Software Foundation version 2. 11 - * 12 - * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, 13 - * whether express or implied; without even the implied warranty of 14 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 - * General Public License for more details. 16 - * 17 - * You should have received a copy of the GNU General Public License 18 - * along with this program; if not, write to the Free Software 19 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 20 - * 02111-1307, USA 21 - */ 22 - 23 - #ifndef __LINUX_MFD_TPS80031_H 24 - #define __LINUX_MFD_TPS80031_H 25 - 26 - #include <linux/device.h> 27 - #include <linux/regmap.h> 28 - 29 - /* Pull-ups/Pull-downs */ 30 - #define TPS80031_CFG_INPUT_PUPD1 0xF0 31 - #define TPS80031_CFG_INPUT_PUPD2 0xF1 32 - #define TPS80031_CFG_INPUT_PUPD3 0xF2 33 - #define TPS80031_CFG_INPUT_PUPD4 0xF3 34 - #define TPS80031_CFG_LDO_PD1 0xF4 35 - #define TPS80031_CFG_LDO_PD2 0xF5 36 - #define TPS80031_CFG_SMPS_PD 0xF6 37 - 38 - /* Real Time Clock */ 39 - #define TPS80031_SECONDS_REG 0x00 40 - #define TPS80031_MINUTES_REG 0x01 41 - #define TPS80031_HOURS_REG 0x02 42 - #define TPS80031_DAYS_REG 0x03 43 - #define TPS80031_MONTHS_REG 0x04 44 - #define TPS80031_YEARS_REG 0x05 45 - #define TPS80031_WEEKS_REG 0x06 46 - #define TPS80031_ALARM_SECONDS_REG 0x08 47 - #define TPS80031_ALARM_MINUTES_REG 0x09 48 - #define TPS80031_ALARM_HOURS_REG 0x0A 49 - #define TPS80031_ALARM_DAYS_REG 0x0B 50 - #define TPS80031_ALARM_MONTHS_REG 0x0C 51 - #define TPS80031_ALARM_YEARS_REG 0x0D 52 - #define TPS80031_RTC_CTRL_REG 0x10 53 - #define TPS80031_RTC_STATUS_REG 0x11 54 - #define TPS80031_RTC_INTERRUPTS_REG 0x12 55 - #define TPS80031_RTC_COMP_LSB_REG 0x13 56 - #define TPS80031_RTC_COMP_MSB_REG 0x14 57 - #define TPS80031_RTC_RESET_STATUS_REG 0x16 58 - 59 - /*PMC Master Module */ 60 - #define TPS80031_PHOENIX_START_CONDITION 0x1F 61 - #define TPS80031_PHOENIX_MSK_TRANSITION 0x20 62 - #define TPS80031_STS_HW_CONDITIONS 0x21 63 - #define TPS80031_PHOENIX_LAST_TURNOFF_STS 0x22 64 - #define TPS80031_VSYSMIN_LO_THRESHOLD 0x23 65 - #define TPS80031_VSYSMIN_HI_THRESHOLD 0x24 66 - #define TPS80031_PHOENIX_DEV_ON 0x25 67 - #define TPS80031_STS_PWR_GRP_STATE 0x27 68 - #define TPS80031_PH_CFG_VSYSLOW 0x28 69 - #define TPS80031_PH_STS_BOOT 0x29 70 - #define TPS80031_PHOENIX_SENS_TRANSITION 0x2A 71 - #define TPS80031_PHOENIX_SEQ_CFG 0x2B 72 - #define TPS80031_PRIMARY_WATCHDOG_CFG 0X2C 73 - #define TPS80031_KEY_PRESS_DUR_CFG 0X2D 74 - #define TPS80031_SMPS_LDO_SHORT_STS 0x2E 75 - 76 - /* PMC Slave Module - Broadcast */ 77 - #define TPS80031_BROADCAST_ADDR_ALL 0x31 78 - #define TPS80031_BROADCAST_ADDR_REF 0x32 79 - #define TPS80031_BROADCAST_ADDR_PROV 0x33 80 - #define TPS80031_BROADCAST_ADDR_CLK_RST 0x34 81 - 82 - /* PMC Slave Module SMPS Regulators */ 83 - #define TPS80031_SMPS4_CFG_TRANS 0x41 84 - #define TPS80031_SMPS4_CFG_STATE 0x42 85 - #define TPS80031_SMPS4_CFG_VOLTAGE 0x44 86 - #define TPS80031_VIO_CFG_TRANS 0x47 87 - #define TPS80031_VIO_CFG_STATE 0x48 88 - #define TPS80031_VIO_CFG_FORCE 0x49 89 - #define TPS80031_VIO_CFG_VOLTAGE 0x4A 90 - #define TPS80031_VIO_CFG_STEP 0x48 91 - #define TPS80031_SMPS1_CFG_TRANS 0x53 92 - #define TPS80031_SMPS1_CFG_STATE 0x54 93 - #define TPS80031_SMPS1_CFG_FORCE 0x55 94 - #define TPS80031_SMPS1_CFG_VOLTAGE 0x56 95 - #define TPS80031_SMPS1_CFG_STEP 0x57 96 - #define TPS80031_SMPS2_CFG_TRANS 0x59 97 - #define TPS80031_SMPS2_CFG_STATE 0x5A 98 - #define TPS80031_SMPS2_CFG_FORCE 0x5B 99 - #define TPS80031_SMPS2_CFG_VOLTAGE 0x5C 100 - #define TPS80031_SMPS2_CFG_STEP 0x5D 101 - #define TPS80031_SMPS3_CFG_TRANS 0x65 102 - #define TPS80031_SMPS3_CFG_STATE 0x66 103 - #define TPS80031_SMPS3_CFG_VOLTAGE 0x68 104 - 105 - /* PMC Slave Module LDO Regulators */ 106 - #define TPS80031_VANA_CFG_TRANS 0x81 107 - #define TPS80031_VANA_CFG_STATE 0x82 108 - #define TPS80031_VANA_CFG_VOLTAGE 0x83 109 - #define TPS80031_LDO2_CFG_TRANS 0x85 110 - #define TPS80031_LDO2_CFG_STATE 0x86 111 - #define TPS80031_LDO2_CFG_VOLTAGE 0x87 112 - #define TPS80031_LDO4_CFG_TRANS 0x89 113 - #define TPS80031_LDO4_CFG_STATE 0x8A 114 - #define TPS80031_LDO4_CFG_VOLTAGE 0x8B 115 - #define TPS80031_LDO3_CFG_TRANS 0x8D 116 - #define TPS80031_LDO3_CFG_STATE 0x8E 117 - #define TPS80031_LDO3_CFG_VOLTAGE 0x8F 118 - #define TPS80031_LDO6_CFG_TRANS 0x91 119 - #define TPS80031_LDO6_CFG_STATE 0x92 120 - #define TPS80031_LDO6_CFG_VOLTAGE 0x93 121 - #define TPS80031_LDOLN_CFG_TRANS 0x95 122 - #define TPS80031_LDOLN_CFG_STATE 0x96 123 - #define TPS80031_LDOLN_CFG_VOLTAGE 0x97 124 - #define TPS80031_LDO5_CFG_TRANS 0x99 125 - #define TPS80031_LDO5_CFG_STATE 0x9A 126 - #define TPS80031_LDO5_CFG_VOLTAGE 0x9B 127 - #define TPS80031_LDO1_CFG_TRANS 0x9D 128 - #define TPS80031_LDO1_CFG_STATE 0x9E 129 - #define TPS80031_LDO1_CFG_VOLTAGE 0x9F 130 - #define TPS80031_LDOUSB_CFG_TRANS 0xA1 131 - #define TPS80031_LDOUSB_CFG_STATE 0xA2 132 - #define TPS80031_LDOUSB_CFG_VOLTAGE 0xA3 133 - #define TPS80031_LDO7_CFG_TRANS 0xA5 134 - #define TPS80031_LDO7_CFG_STATE 0xA6 135 - #define TPS80031_LDO7_CFG_VOLTAGE 0xA7 136 - 137 - /* PMC Slave Module External Control */ 138 - #define TPS80031_REGEN1_CFG_TRANS 0xAE 139 - #define TPS80031_REGEN1_CFG_STATE 0xAF 140 - #define TPS80031_REGEN2_CFG_TRANS 0xB1 141 - #define TPS80031_REGEN2_CFG_STATE 0xB2 142 - #define TPS80031_SYSEN_CFG_TRANS 0xB4 143 - #define TPS80031_SYSEN_CFG_STATE 0xB5 144 - 145 - /* PMC Slave Module Internal Control */ 146 - #define TPS80031_NRESPWRON_CFG_TRANS 0xB7 147 - #define TPS80031_NRESPWRON_CFG_STATE 0xB8 148 - #define TPS80031_CLK32KAO_CFG_TRANS 0xBA 149 - #define TPS80031_CLK32KAO_CFG_STATE 0xBB 150 - #define TPS80031_CLK32KG_CFG_TRANS 0xBD 151 - #define TPS80031_CLK32KG_CFG_STATE 0xBE 152 - #define TPS80031_CLK32KAUDIO_CFG_TRANS 0xC0 153 - #define TPS80031_CLK32KAUDIO_CFG_STATE 0xC1 154 - #define TPS80031_VRTC_CFG_TRANS 0xC3 155 - #define TPS80031_VRTC_CFG_STATE 0xC4 156 - #define TPS80031_BIAS_CFG_TRANS 0xC6 157 - #define TPS80031_BIAS_CFG_STATE 0xC7 158 - #define TPS80031_VSYSMIN_HI_CFG_TRANS 0xC9 159 - #define TPS80031_VSYSMIN_HI_CFG_STATE 0xCA 160 - #define TPS80031_RC6MHZ_CFG_TRANS 0xCC 161 - #define TPS80031_RC6MHZ_CFG_STATE 0xCD 162 - #define TPS80031_TMP_CFG_TRANS 0xCF 163 - #define TPS80031_TMP_CFG_STATE 0xD0 164 - 165 - /* PMC Slave Module resources assignment */ 166 - #define TPS80031_PREQ1_RES_ASS_A 0xD7 167 - #define TPS80031_PREQ1_RES_ASS_B 0xD8 168 - #define TPS80031_PREQ1_RES_ASS_C 0xD9 169 - #define TPS80031_PREQ2_RES_ASS_A 0xDA 170 - #define TPS80031_PREQ2_RES_ASS_B 0xDB 171 - #define TPS80031_PREQ2_RES_ASS_C 0xDC 172 - #define TPS80031_PREQ3_RES_ASS_A 0xDD 173 - #define TPS80031_PREQ3_RES_ASS_B 0xDE 174 - #define TPS80031_PREQ3_RES_ASS_C 0xDF 175 - 176 - /* PMC Slave Module Miscellaneous */ 177 - #define TPS80031_SMPS_OFFSET 0xE0 178 - #define TPS80031_SMPS_MULT 0xE3 179 - #define TPS80031_MISC1 0xE4 180 - #define TPS80031_MISC2 0xE5 181 - #define TPS80031_BBSPOR_CFG 0xE6 182 - #define TPS80031_TMP_CFG 0xE7 183 - 184 - /* Battery Charging Controller and Indicator LED */ 185 - #define TPS80031_CONTROLLER_CTRL2 0xDA 186 - #define TPS80031_CONTROLLER_VSEL_COMP 0xDB 187 - #define TPS80031_CHARGERUSB_VSYSREG 0xDC 188 - #define TPS80031_CHARGERUSB_VICHRG_PC 0xDD 189 - #define TPS80031_LINEAR_CHRG_STS 0xDE 190 - #define TPS80031_CONTROLLER_INT_MASK 0xE0 191 - #define TPS80031_CONTROLLER_CTRL1 0xE1 192 - #define TPS80031_CONTROLLER_WDG 0xE2 193 - #define TPS80031_CONTROLLER_STAT1 0xE3 194 - #define TPS80031_CHARGERUSB_INT_STATUS 0xE4 195 - #define TPS80031_CHARGERUSB_INT_MASK 0xE5 196 - #define TPS80031_CHARGERUSB_STATUS_INT1 0xE6 197 - #define TPS80031_CHARGERUSB_STATUS_INT2 0xE7 198 - #define TPS80031_CHARGERUSB_CTRL1 0xE8 199 - #define TPS80031_CHARGERUSB_CTRL2 0xE9 200 - #define TPS80031_CHARGERUSB_CTRL3 0xEA 201 - #define TPS80031_CHARGERUSB_STAT1 0xEB 202 - #define TPS80031_CHARGERUSB_VOREG 0xEC 203 - #define TPS80031_CHARGERUSB_VICHRG 0xED 204 - #define TPS80031_CHARGERUSB_CINLIMIT 0xEE 205 - #define TPS80031_CHARGERUSB_CTRLLIMIT1 0xEF 206 - #define TPS80031_CHARGERUSB_CTRLLIMIT2 0xF0 207 - #define TPS80031_LED_PWM_CTRL1 0xF4 208 - #define TPS80031_LED_PWM_CTRL2 0xF5 209 - 210 - /* USB On-The-Go */ 211 - #define TPS80031_BACKUP_REG 0xFA 212 - #define TPS80031_USB_VENDOR_ID_LSB 0x00 213 - #define TPS80031_USB_VENDOR_ID_MSB 0x01 214 - #define TPS80031_USB_PRODUCT_ID_LSB 0x02 215 - #define TPS80031_USB_PRODUCT_ID_MSB 0x03 216 - #define TPS80031_USB_VBUS_CTRL_SET 0x04 217 - #define TPS80031_USB_VBUS_CTRL_CLR 0x05 218 - #define TPS80031_USB_ID_CTRL_SET 0x06 219 - #define TPS80031_USB_ID_CTRL_CLR 0x07 220 - #define TPS80031_USB_VBUS_INT_SRC 0x08 221 - #define TPS80031_USB_VBUS_INT_LATCH_SET 0x09 222 - #define TPS80031_USB_VBUS_INT_LATCH_CLR 0x0A 223 - #define TPS80031_USB_VBUS_INT_EN_LO_SET 0x0B 224 - #define TPS80031_USB_VBUS_INT_EN_LO_CLR 0x0C 225 - #define TPS80031_USB_VBUS_INT_EN_HI_SET 0x0D 226 - #define TPS80031_USB_VBUS_INT_EN_HI_CLR 0x0E 227 - #define TPS80031_USB_ID_INT_SRC 0x0F 228 - #define TPS80031_USB_ID_INT_LATCH_SET 0x10 229 - #define TPS80031_USB_ID_INT_LATCH_CLR 0x11 230 - #define TPS80031_USB_ID_INT_EN_LO_SET 0x12 231 - #define TPS80031_USB_ID_INT_EN_LO_CLR 0x13 232 - #define TPS80031_USB_ID_INT_EN_HI_SET 0x14 233 - #define TPS80031_USB_ID_INT_EN_HI_CLR 0x15 234 - #define TPS80031_USB_OTG_ADP_CTRL 0x16 235 - #define TPS80031_USB_OTG_ADP_HIGH 0x17 236 - #define TPS80031_USB_OTG_ADP_LOW 0x18 237 - #define TPS80031_USB_OTG_ADP_RISE 0x19 238 - #define TPS80031_USB_OTG_REVISION 0x1A 239 - 240 - /* Gas Gauge */ 241 - #define TPS80031_FG_REG_00 0xC0 242 - #define TPS80031_FG_REG_01 0xC1 243 - #define TPS80031_FG_REG_02 0xC2 244 - #define TPS80031_FG_REG_03 0xC3 245 - #define TPS80031_FG_REG_04 0xC4 246 - #define TPS80031_FG_REG_05 0xC5 247 - #define TPS80031_FG_REG_06 0xC6 248 - #define TPS80031_FG_REG_07 0xC7 249 - #define TPS80031_FG_REG_08 0xC8 250 - #define TPS80031_FG_REG_09 0xC9 251 - #define TPS80031_FG_REG_10 0xCA 252 - #define TPS80031_FG_REG_11 0xCB 253 - 254 - /* General Purpose ADC */ 255 - #define TPS80031_GPADC_CTRL 0x2E 256 - #define TPS80031_GPADC_CTRL2 0x2F 257 - #define TPS80031_RTSELECT_LSB 0x32 258 - #define TPS80031_RTSELECT_ISB 0x33 259 - #define TPS80031_RTSELECT_MSB 0x34 260 - #define TPS80031_GPSELECT_ISB 0x35 261 - #define TPS80031_CTRL_P1 0x36 262 - #define TPS80031_RTCH0_LSB 0x37 263 - #define TPS80031_RTCH0_MSB 0x38 264 - #define TPS80031_RTCH1_LSB 0x39 265 - #define TPS80031_RTCH1_MSB 0x3A 266 - #define TPS80031_GPCH0_LSB 0x3B 267 - #define TPS80031_GPCH0_MSB 0x3C 268 - 269 - /* SIM, MMC and Battery Detection */ 270 - #define TPS80031_SIMDEBOUNCING 0xEB 271 - #define TPS80031_SIMCTRL 0xEC 272 - #define TPS80031_MMCDEBOUNCING 0xED 273 - #define TPS80031_MMCCTRL 0xEE 274 - #define TPS80031_BATDEBOUNCING 0xEF 275 - 276 - /* Vibrator Driver and PWMs */ 277 - #define TPS80031_VIBCTRL 0x9B 278 - #define TPS80031_VIBMODE 0x9C 279 - #define TPS80031_PWM1ON 0xBA 280 - #define TPS80031_PWM1OFF 0xBB 281 - #define TPS80031_PWM2ON 0xBD 282 - #define TPS80031_PWM2OFF 0xBE 283 - 284 - /* Control Interface */ 285 - #define TPS80031_INT_STS_A 0xD0 286 - #define TPS80031_INT_STS_B 0xD1 287 - #define TPS80031_INT_STS_C 0xD2 288 - #define TPS80031_INT_MSK_LINE_A 0xD3 289 - #define TPS80031_INT_MSK_LINE_B 0xD4 290 - #define TPS80031_INT_MSK_LINE_C 0xD5 291 - #define TPS80031_INT_MSK_STS_A 0xD6 292 - #define TPS80031_INT_MSK_STS_B 0xD7 293 - #define TPS80031_INT_MSK_STS_C 0xD8 294 - #define TPS80031_TOGGLE1 0x90 295 - #define TPS80031_TOGGLE2 0x91 296 - #define TPS80031_TOGGLE3 0x92 297 - #define TPS80031_PWDNSTATUS1 0x93 298 - #define TPS80031_PWDNSTATUS2 0x94 299 - #define TPS80031_VALIDITY0 0x17 300 - #define TPS80031_VALIDITY1 0x18 301 - #define TPS80031_VALIDITY2 0x19 302 - #define TPS80031_VALIDITY3 0x1A 303 - #define TPS80031_VALIDITY4 0x1B 304 - #define TPS80031_VALIDITY5 0x1C 305 - #define TPS80031_VALIDITY6 0x1D 306 - #define TPS80031_VALIDITY7 0x1E 307 - 308 - /* Version number related register */ 309 - #define TPS80031_JTAGVERNUM 0x87 310 - #define TPS80031_EPROM_REV 0xDF 311 - 312 - /* GPADC Trimming Bits. */ 313 - #define TPS80031_GPADC_TRIM0 0xCC 314 - #define TPS80031_GPADC_TRIM1 0xCD 315 - #define TPS80031_GPADC_TRIM2 0xCE 316 - #define TPS80031_GPADC_TRIM3 0xCF 317 - #define TPS80031_GPADC_TRIM4 0xD0 318 - #define TPS80031_GPADC_TRIM5 0xD1 319 - #define TPS80031_GPADC_TRIM6 0xD2 320 - #define TPS80031_GPADC_TRIM7 0xD3 321 - #define TPS80031_GPADC_TRIM8 0xD4 322 - #define TPS80031_GPADC_TRIM9 0xD5 323 - #define TPS80031_GPADC_TRIM10 0xD6 324 - #define TPS80031_GPADC_TRIM11 0xD7 325 - #define TPS80031_GPADC_TRIM12 0xD8 326 - #define TPS80031_GPADC_TRIM13 0xD9 327 - #define TPS80031_GPADC_TRIM14 0xDA 328 - #define TPS80031_GPADC_TRIM15 0xDB 329 - #define TPS80031_GPADC_TRIM16 0xDC 330 - #define TPS80031_GPADC_TRIM17 0xDD 331 - #define TPS80031_GPADC_TRIM18 0xDE 332 - 333 - /* TPS80031_CONTROLLER_STAT1 bit fields */ 334 - #define TPS80031_CONTROLLER_STAT1_BAT_TEMP 0 335 - #define TPS80031_CONTROLLER_STAT1_BAT_REMOVED 1 336 - #define TPS80031_CONTROLLER_STAT1_VBUS_DET 2 337 - #define TPS80031_CONTROLLER_STAT1_VAC_DET 3 338 - #define TPS80031_CONTROLLER_STAT1_FAULT_WDG 4 339 - #define TPS80031_CONTROLLER_STAT1_LINCH_GATED 6 340 - /* TPS80031_CONTROLLER_INT_MASK bit filed */ 341 - #define TPS80031_CONTROLLER_INT_MASK_MVAC_DET 0 342 - #define TPS80031_CONTROLLER_INT_MASK_MVBUS_DET 1 343 - #define TPS80031_CONTROLLER_INT_MASK_MBAT_TEMP 2 344 - #define TPS80031_CONTROLLER_INT_MASK_MFAULT_WDG 3 345 - #define TPS80031_CONTROLLER_INT_MASK_MBAT_REMOVED 4 346 - #define TPS80031_CONTROLLER_INT_MASK_MLINCH_GATED 5 347 - 348 - #define TPS80031_CHARGE_CONTROL_SUB_INT_MASK 0x3F 349 - 350 - /* TPS80031_PHOENIX_DEV_ON bit field */ 351 - #define TPS80031_DEVOFF 0x1 352 - 353 - #define TPS80031_EXT_CONTROL_CFG_TRANS 0 354 - #define TPS80031_EXT_CONTROL_CFG_STATE 1 355 - 356 - /* State register field */ 357 - #define TPS80031_STATE_OFF 0x00 358 - #define TPS80031_STATE_ON 0x01 359 - #define TPS80031_STATE_MASK 0x03 360 - 361 - /* Trans register field */ 362 - #define TPS80031_TRANS_ACTIVE_OFF 0x00 363 - #define TPS80031_TRANS_ACTIVE_ON 0x01 364 - #define TPS80031_TRANS_ACTIVE_MASK 0x03 365 - #define TPS80031_TRANS_SLEEP_OFF 0x00 366 - #define TPS80031_TRANS_SLEEP_ON 0x04 367 - #define TPS80031_TRANS_SLEEP_MASK 0x0C 368 - #define TPS80031_TRANS_OFF_OFF 0x00 369 - #define TPS80031_TRANS_OFF_ACTIVE 0x10 370 - #define TPS80031_TRANS_OFF_MASK 0x30 371 - 372 - #define TPS80031_EXT_PWR_REQ (TPS80031_PWR_REQ_INPUT_PREQ1 | \ 373 - TPS80031_PWR_REQ_INPUT_PREQ2 | \ 374 - TPS80031_PWR_REQ_INPUT_PREQ3) 375 - 376 - /* TPS80031_BBSPOR_CFG bit field */ 377 - #define TPS80031_BBSPOR_CHG_EN 0x8 378 - #define TPS80031_MAX_REGISTER 0xFF 379 - 380 - struct i2c_client; 381 - 382 - /* Supported chips */ 383 - enum chips { 384 - TPS80031 = 0x00000001, 385 - TPS80032 = 0x00000002, 386 - }; 387 - 388 - enum { 389 - TPS80031_INT_PWRON, 390 - TPS80031_INT_RPWRON, 391 - TPS80031_INT_SYS_VLOW, 392 - TPS80031_INT_RTC_ALARM, 393 - TPS80031_INT_RTC_PERIOD, 394 - TPS80031_INT_HOT_DIE, 395 - TPS80031_INT_VXX_SHORT, 396 - TPS80031_INT_SPDURATION, 397 - TPS80031_INT_WATCHDOG, 398 - TPS80031_INT_BAT, 399 - TPS80031_INT_SIM, 400 - TPS80031_INT_MMC, 401 - TPS80031_INT_RES, 402 - TPS80031_INT_GPADC_RT, 403 - TPS80031_INT_GPADC_SW2_EOC, 404 - TPS80031_INT_CC_AUTOCAL, 405 - TPS80031_INT_ID_WKUP, 406 - TPS80031_INT_VBUSS_WKUP, 407 - TPS80031_INT_ID, 408 - TPS80031_INT_VBUS, 409 - TPS80031_INT_CHRG_CTRL, 410 - TPS80031_INT_EXT_CHRG, 411 - TPS80031_INT_INT_CHRG, 412 - TPS80031_INT_RES2, 413 - TPS80031_INT_BAT_TEMP_OVRANGE, 414 - TPS80031_INT_BAT_REMOVED, 415 - TPS80031_INT_VBUS_DET, 416 - TPS80031_INT_VAC_DET, 417 - TPS80031_INT_FAULT_WDG, 418 - TPS80031_INT_LINCH_GATED, 419 - 420 - /* Last interrupt id to get the end number */ 421 - TPS80031_INT_NR, 422 - }; 423 - 424 - /* TPS80031 Slave IDs */ 425 - #define TPS80031_NUM_SLAVES 4 426 - #define TPS80031_SLAVE_ID0 0 427 - #define TPS80031_SLAVE_ID1 1 428 - #define TPS80031_SLAVE_ID2 2 429 - #define TPS80031_SLAVE_ID3 3 430 - 431 - /* TPS80031 I2C addresses */ 432 - #define TPS80031_I2C_ID0_ADDR 0x12 433 - #define TPS80031_I2C_ID1_ADDR 0x48 434 - #define TPS80031_I2C_ID2_ADDR 0x49 435 - #define TPS80031_I2C_ID3_ADDR 0x4A 436 - 437 - enum { 438 - TPS80031_REGULATOR_VIO, 439 - TPS80031_REGULATOR_SMPS1, 440 - TPS80031_REGULATOR_SMPS2, 441 - TPS80031_REGULATOR_SMPS3, 442 - TPS80031_REGULATOR_SMPS4, 443 - TPS80031_REGULATOR_VANA, 444 - TPS80031_REGULATOR_LDO1, 445 - TPS80031_REGULATOR_LDO2, 446 - TPS80031_REGULATOR_LDO3, 447 - TPS80031_REGULATOR_LDO4, 448 - TPS80031_REGULATOR_LDO5, 449 - TPS80031_REGULATOR_LDO6, 450 - TPS80031_REGULATOR_LDO7, 451 - TPS80031_REGULATOR_LDOLN, 452 - TPS80031_REGULATOR_LDOUSB, 453 - TPS80031_REGULATOR_VBUS, 454 - TPS80031_REGULATOR_REGEN1, 455 - TPS80031_REGULATOR_REGEN2, 456 - TPS80031_REGULATOR_SYSEN, 457 - TPS80031_REGULATOR_MAX, 458 - }; 459 - 460 - /* Different configurations for the rails */ 461 - enum { 462 - /* USBLDO input selection */ 463 - TPS80031_USBLDO_INPUT_VSYS = 0x00000001, 464 - TPS80031_USBLDO_INPUT_PMID = 0x00000002, 465 - 466 - /* LDO3 output mode */ 467 - TPS80031_LDO3_OUTPUT_VIB = 0x00000004, 468 - 469 - /* VBUS configuration */ 470 - TPS80031_VBUS_DISCHRG_EN_PDN = 0x00000004, 471 - TPS80031_VBUS_SW_ONLY = 0x00000008, 472 - TPS80031_VBUS_SW_N_ID = 0x00000010, 473 - }; 474 - 475 - /* External controls requests */ 476 - enum tps80031_ext_control { 477 - TPS80031_PWR_REQ_INPUT_NONE = 0x00000000, 478 - TPS80031_PWR_REQ_INPUT_PREQ1 = 0x00000001, 479 - TPS80031_PWR_REQ_INPUT_PREQ2 = 0x00000002, 480 - TPS80031_PWR_REQ_INPUT_PREQ3 = 0x00000004, 481 - TPS80031_PWR_OFF_ON_SLEEP = 0x00000008, 482 - TPS80031_PWR_ON_ON_SLEEP = 0x00000010, 483 - }; 484 - 485 - enum tps80031_pupd_pins { 486 - TPS80031_PREQ1 = 0, 487 - TPS80031_PREQ2A, 488 - TPS80031_PREQ2B, 489 - TPS80031_PREQ2C, 490 - TPS80031_PREQ3, 491 - TPS80031_NRES_WARM, 492 - TPS80031_PWM_FORCE, 493 - TPS80031_CHRG_EXT_CHRG_STATZ, 494 - TPS80031_SIM, 495 - TPS80031_MMC, 496 - TPS80031_GPADC_START, 497 - TPS80031_DVSI2C_SCL, 498 - TPS80031_DVSI2C_SDA, 499 - TPS80031_CTLI2C_SCL, 500 - TPS80031_CTLI2C_SDA, 501 - }; 502 - 503 - enum tps80031_pupd_settings { 504 - TPS80031_PUPD_NORMAL, 505 - TPS80031_PUPD_PULLDOWN, 506 - TPS80031_PUPD_PULLUP, 507 - }; 508 - 509 - struct tps80031 { 510 - struct device *dev; 511 - unsigned long chip_info; 512 - int es_version; 513 - struct i2c_client *clients[TPS80031_NUM_SLAVES]; 514 - struct regmap *regmap[TPS80031_NUM_SLAVES]; 515 - struct regmap_irq_chip_data *irq_data; 516 - }; 517 - 518 - struct tps80031_pupd_init_data { 519 - int input_pin; 520 - int setting; 521 - }; 522 - 523 - /* 524 - * struct tps80031_regulator_platform_data - tps80031 regulator platform data. 525 - * 526 - * @reg_init_data: The regulator init data. 527 - * @ext_ctrl_flag: External control flag for sleep/power request control. 528 - * @config_flags: Configuration flag to configure the rails. 529 - * It should be ORed of config enums. 530 - */ 531 - 532 - struct tps80031_regulator_platform_data { 533 - struct regulator_init_data *reg_init_data; 534 - unsigned int ext_ctrl_flag; 535 - unsigned int config_flags; 536 - }; 537 - 538 - struct tps80031_platform_data { 539 - int irq_base; 540 - bool use_power_off; 541 - struct tps80031_pupd_init_data *pupd_init_data; 542 - int pupd_init_data_size; 543 - struct tps80031_regulator_platform_data 544 - *regulator_pdata[TPS80031_REGULATOR_MAX]; 545 - }; 546 - 547 - static inline int tps80031_write(struct device *dev, int sid, 548 - int reg, uint8_t val) 549 - { 550 - struct tps80031 *tps80031 = dev_get_drvdata(dev); 551 - 552 - return regmap_write(tps80031->regmap[sid], reg, val); 553 - } 554 - 555 - static inline int tps80031_writes(struct device *dev, int sid, int reg, 556 - int len, uint8_t *val) 557 - { 558 - struct tps80031 *tps80031 = dev_get_drvdata(dev); 559 - 560 - return regmap_bulk_write(tps80031->regmap[sid], reg, val, len); 561 - } 562 - 563 - static inline int tps80031_read(struct device *dev, int sid, 564 - int reg, uint8_t *val) 565 - { 566 - struct tps80031 *tps80031 = dev_get_drvdata(dev); 567 - unsigned int ival; 568 - int ret; 569 - 570 - ret = regmap_read(tps80031->regmap[sid], reg, &ival); 571 - if (ret < 0) { 572 - dev_err(dev, "failed reading from reg 0x%02x\n", reg); 573 - return ret; 574 - } 575 - 576 - *val = ival; 577 - return ret; 578 - } 579 - 580 - static inline int tps80031_reads(struct device *dev, int sid, 581 - int reg, int len, uint8_t *val) 582 - { 583 - struct tps80031 *tps80031 = dev_get_drvdata(dev); 584 - 585 - return regmap_bulk_read(tps80031->regmap[sid], reg, val, len); 586 - } 587 - 588 - static inline int tps80031_set_bits(struct device *dev, int sid, 589 - int reg, uint8_t bit_mask) 590 - { 591 - struct tps80031 *tps80031 = dev_get_drvdata(dev); 592 - 593 - return regmap_update_bits(tps80031->regmap[sid], reg, 594 - bit_mask, bit_mask); 595 - } 596 - 597 - static inline int tps80031_clr_bits(struct device *dev, int sid, 598 - int reg, uint8_t bit_mask) 599 - { 600 - struct tps80031 *tps80031 = dev_get_drvdata(dev); 601 - 602 - return regmap_update_bits(tps80031->regmap[sid], reg, bit_mask, 0); 603 - } 604 - 605 - static inline int tps80031_update(struct device *dev, int sid, 606 - int reg, uint8_t val, uint8_t mask) 607 - { 608 - struct tps80031 *tps80031 = dev_get_drvdata(dev); 609 - 610 - return regmap_update_bits(tps80031->regmap[sid], reg, mask, val); 611 - } 612 - 613 - static inline unsigned long tps80031_get_chip_info(struct device *dev) 614 - { 615 - struct tps80031 *tps80031 = dev_get_drvdata(dev); 616 - 617 - return tps80031->chip_info; 618 - } 619 - 620 - static inline int tps80031_get_pmu_version(struct device *dev) 621 - { 622 - struct tps80031 *tps80031 = dev_get_drvdata(dev); 623 - 624 - return tps80031->es_version; 625 - } 626 - 627 - static inline int tps80031_irq_get_virq(struct device *dev, int irq) 628 - { 629 - struct tps80031 *tps80031 = dev_get_drvdata(dev); 630 - 631 - return regmap_irq_get_virq(tps80031->irq_data, irq); 632 - } 633 - 634 - extern int tps80031_ext_power_req_config(struct device *dev, 635 - unsigned long ext_ctrl_flag, int preq_bit, 636 - int state_reg_add, int trans_reg_add); 637 - #endif /*__LINUX_MFD_TPS80031_H */