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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/ast: Split ast_set_def_ext_reg() by chip generation
Duplicate ast_set_def_ext_reg() for individual chip generations
and move call it into per-chip source files. Remove the original
code. AST2100 and AST2500 reuse the function from earlier chips.
AST2600 appears to be incorrect as it uses an older function. Keep
this behavior for now.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://lore.kernel.org/r/20250706162816.211552-9-tzimmermann@suse.de
+111
-40
+32
drivers/gpu/drm/ast/ast_2000.c
+32
drivers/gpu/drm/ast/ast_2000.c
···
35
35
* POST
36
36
*/
37
37
38
+
void ast_2000_set_def_ext_reg(struct ast_device *ast)
39
+
{
40
+
static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
41
+
u8 i, index, reg;
42
+
const u8 *ext_reg_info;
43
+
44
+
/* reset scratch */
45
+
for (i = 0x81; i <= 0x9f; i++)
46
+
ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
47
+
48
+
ext_reg_info = extreginfo;
49
+
index = 0xa0;
50
+
while (*ext_reg_info != 0xff) {
51
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
52
+
index++;
53
+
ext_reg_info++;
54
+
}
55
+
56
+
/* disable standard IO/MEM decode if secondary */
57
+
/* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
58
+
59
+
/* Set Ext. Default */
60
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
61
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
62
+
63
+
/* Enable RAMDAC for A1 */
64
+
reg = 0x04;
65
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
66
+
}
67
+
38
68
static const struct ast_dramstruct ast2000_dram_table_data[] = {
39
69
{ 0x0108, 0x00000000 },
40
70
{ 0x0120, 0x00004a21 },
···
134
104
135
105
int ast_2000_post(struct ast_device *ast)
136
106
{
107
+
ast_2000_set_def_ext_reg(ast);
108
+
137
109
if (ast->config_mode == ast_use_p2a) {
138
110
ast_post_chip_2000(ast);
139
111
} else {
+2
drivers/gpu/drm/ast/ast_2100.c
+2
drivers/gpu/drm/ast/ast_2100.c
+33
drivers/gpu/drm/ast/ast_2300.c
+33
drivers/gpu/drm/ast/ast_2300.c
···
35
35
* POST
36
36
*/
37
37
38
+
void ast_2300_set_def_ext_reg(struct ast_device *ast)
39
+
{
40
+
static const u8 extreginfo[] = { 0x0f, 0x04, 0x1f, 0xff };
41
+
u8 i, index, reg;
42
+
const u8 *ext_reg_info;
43
+
44
+
/* reset scratch */
45
+
for (i = 0x81; i <= 0x9f; i++)
46
+
ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
47
+
48
+
ext_reg_info = extreginfo;
49
+
index = 0xa0;
50
+
while (*ext_reg_info != 0xff) {
51
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
52
+
index++;
53
+
ext_reg_info++;
54
+
}
55
+
56
+
/* disable standard IO/MEM decode if secondary */
57
+
/* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
58
+
59
+
/* Set Ext. Default */
60
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
61
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
62
+
63
+
/* Enable RAMDAC for A1 */
64
+
reg = 0x04;
65
+
reg |= 0x20;
66
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
67
+
}
68
+
38
69
/* AST 2300 DRAM settings */
39
70
#define AST_DDR3 0
40
71
#define AST_DDR2 1
···
1312
1281
1313
1282
int ast_2300_post(struct ast_device *ast)
1314
1283
{
1284
+
ast_2300_set_def_ext_reg(ast);
1285
+
1315
1286
if (ast->config_mode == ast_use_p2a) {
1316
1287
ast_post_chip_2300(ast);
1317
1288
ast_init_3rdtx(ast);
+2
drivers/gpu/drm/ast/ast_2500.c
+2
drivers/gpu/drm/ast/ast_2500.c
+33
drivers/gpu/drm/ast/ast_2600.c
+33
drivers/gpu/drm/ast/ast_2600.c
···
27
27
*/
28
28
29
29
#include "ast_drv.h"
30
+
#include "ast_post.h"
30
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31
32
/*
32
33
* POST
33
34
*/
34
35
36
+
void ast_2600_set_def_ext_reg(struct ast_device *ast)
37
+
{
38
+
static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
39
+
u8 i, index, reg;
40
+
const u8 *ext_reg_info;
41
+
42
+
/* reset scratch */
43
+
for (i = 0x81; i <= 0x9f; i++)
44
+
ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
45
+
46
+
ext_reg_info = extreginfo;
47
+
index = 0xa0;
48
+
while (*ext_reg_info != 0xff) {
49
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
50
+
index++;
51
+
ext_reg_info++;
52
+
}
53
+
54
+
/* disable standard IO/MEM decode if secondary */
55
+
/* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
56
+
57
+
/* Set Ext. Default */
58
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
59
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
60
+
61
+
/* Enable RAMDAC for A1 */
62
+
reg = 0x04;
63
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
64
+
}
65
+
35
66
int ast_2600_post(struct ast_device *ast)
36
67
{
68
+
ast_2600_set_def_ext_reg(ast);
69
+
37
70
if (ast->tx_chip == AST_TX_ASTDP)
38
71
return ast_dp_launch(ast);
39
72
-40
drivers/gpu/drm/ast/ast_post.c
-40
drivers/gpu/drm/ast/ast_post.c
···
34
34
#include "ast_drv.h"
35
35
#include "ast_post.h"
36
36
37
-
static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
38
-
static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
39
-
40
-
static void ast_set_def_ext_reg(struct ast_device *ast)
41
-
{
42
-
u8 i, index, reg;
43
-
const u8 *ext_reg_info;
44
-
45
-
/* reset scratch */
46
-
for (i = 0x81; i <= 0x9f; i++)
47
-
ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
48
-
49
-
if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
50
-
ext_reg_info = extreginfo_ast2300;
51
-
else
52
-
ext_reg_info = extreginfo;
53
-
54
-
index = 0xa0;
55
-
while (*ext_reg_info != 0xff) {
56
-
ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
57
-
index++;
58
-
ext_reg_info++;
59
-
}
60
-
61
-
/* disable standard IO/MEM decode if secondary */
62
-
/* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
63
-
64
-
/* Set Ext. Default */
65
-
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
66
-
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
67
-
68
-
/* Enable RAMDAC for A1 */
69
-
reg = 0x04;
70
-
if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
71
-
reg |= 0x20;
72
-
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
73
-
}
74
-
75
37
u32 __ast_mindwm(void __iomem *regs, u32 r)
76
38
{
77
39
u32 data;
···
75
113
int ast_post_gpu(struct ast_device *ast)
76
114
{
77
115
int ret;
78
-
79
-
ast_set_def_ext_reg(ast);
80
116
81
117
if (AST_GEN(ast) >= 7) {
82
118
ret = ast_2600_post(ast);
+9
drivers/gpu/drm/ast/ast_post.h
+9
drivers/gpu/drm/ast/ast_post.h
···
41
41
bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl);
42
42
bool mmc_test_burst(struct ast_device *ast, u32 datagen);
43
43
44
+
/* ast_2000.c */
45
+
void ast_2000_set_def_ext_reg(struct ast_device *ast);
46
+
47
+
/* ast_2300.c */
48
+
void ast_2300_set_def_ext_reg(struct ast_device *ast);
49
+
50
+
/* ast_2600.c */
51
+
void ast_2600_set_def_ext_reg(struct ast_device *ast);
52
+
44
53
#endif