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kernel
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linux
dt-bindings: clock: qcom: Add SM8750 video clock controller
Add compatible string for SM8750 video clock controller and the bindings
for SM8750 Qualcomm SoC.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-4-049882a70c9f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Taniya Das
and committed by
Bjorn Andersson
b190eaea
aa788d3b
+44
-1
+4
-1
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
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Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
···
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title: Qualcomm Video Clock & Reset Controller on SM8450
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maintainers:
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- Taniya Das <quic_tdas@quicinc.com>
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- Taniya Das <taniya.das@oss.qualcomm.com>
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- Jagadeesh Kona <quic_jkona@quicinc.com>
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description: |
···
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See also:
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include/dt-bindings/clock/qcom,sm8450-videocc.h
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include/dt-bindings/clock/qcom,sm8650-videocc.h
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include/dt-bindings/clock/qcom,sm8750-videocc.h
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properties:
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compatible:
···
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- qcom,sm8475-videocc
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- qcom,sm8550-videocc
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- qcom,sm8650-videocc
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- qcom,sm8750-videocc
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- qcom,x1e80100-videocc
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clocks:
···
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enum:
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- qcom,sm8450-videocc
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- qcom,sm8550-videocc
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- qcom,sm8750-videocc
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then:
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required:
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- required-opps
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include/dt-bindings/clock/qcom,sm8750-videocc.h
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include/dt-bindings/clock/qcom,sm8750-videocc.h
···
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8750_H
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#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8750_H
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/* VIDEO_CC clocks */
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#define VIDEO_CC_AHB_CLK 0
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#define VIDEO_CC_AHB_CLK_SRC 1
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#define VIDEO_CC_MVS0_CLK 2
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#define VIDEO_CC_MVS0_CLK_SRC 3
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#define VIDEO_CC_MVS0_DIV_CLK_SRC 4
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#define VIDEO_CC_MVS0_FREERUN_CLK 5
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#define VIDEO_CC_MVS0_SHIFT_CLK 6
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#define VIDEO_CC_MVS0C_CLK 7
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#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8
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#define VIDEO_CC_MVS0C_FREERUN_CLK 9
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#define VIDEO_CC_MVS0C_SHIFT_CLK 10
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#define VIDEO_CC_PLL0 11
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#define VIDEO_CC_SLEEP_CLK 12
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#define VIDEO_CC_SLEEP_CLK_SRC 13
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#define VIDEO_CC_XO_CLK 14
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#define VIDEO_CC_XO_CLK_SRC 15
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/* VIDEO_CC power domains */
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#define VIDEO_CC_MVS0_GDSC 0
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#define VIDEO_CC_MVS0C_GDSC 1
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/* VIDEO_CC resets */
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#define VIDEO_CC_INTERFACE_BCR 0
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#define VIDEO_CC_MVS0_BCR 1
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#define VIDEO_CC_MVS0C_CLK_ARES 2
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#define VIDEO_CC_MVS0C_BCR 3
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#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 4
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#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 5
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#define VIDEO_CC_XO_CLK_ARES 6
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#endif