Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

staging: comedi: s626: use preferred kernel type u32

Fix the checkpatch.pl issue:
CHECK: Prefer kernel type 'u32' over 'uint32_t'

Signed-off-by: Saber Rezvani <irsaber@gmail.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Saber Rezvani and committed by
Greg Kroah-Hartman
b13db6bf 0bc45380

+29 -29
+29 -29
drivers/staging/comedi/drivers/s626.c
··· 88 88 * program */ 89 89 struct s626_buffer_dma ana_buf; /* DMA buffer used to receive ADC data 90 90 * and hold DAC data */ 91 - uint32_t *dac_wbuf; /* pointer to logical adrs of DMA buffer 91 + u32 *dac_wbuf; /* pointer to logical adrs of DMA buffer 92 92 * used to hold DAC data */ 93 93 u16 dacpol; /* image of DAC polarity register */ 94 94 u8 trim_setpoint[12]; /* images of TrimDAC setpoints */ 95 - uint32_t i2c_adrs; /* I2C device address for onboard EEPROM 95 + u32 i2c_adrs; /* I2C device address for onboard EEPROM 96 96 * (board rev dependent) */ 97 97 }; 98 98 ··· 241 241 return -EBUSY; 242 242 } 243 243 244 - static int s626_i2c_handshake(struct comedi_device *dev, uint32_t val) 244 + static int s626_i2c_handshake(struct comedi_device *dev, u32 val) 245 245 { 246 246 unsigned int ctrl; 247 247 int ret; ··· 357 357 * channel 2. Assumes: (1) TSL2 slot records initialized, and (2) 358 358 * dacpol contains valid target image. 359 359 */ 360 - static int s626_send_dac(struct comedi_device *dev, uint32_t val) 360 + static int s626_send_dac(struct comedi_device *dev, u32 val) 361 361 { 362 362 struct s626_private *devpriv = dev->private; 363 363 int ret; ··· 520 520 { 521 521 struct s626_private *devpriv = dev->private; 522 522 u16 signmask; 523 - uint32_t ws_image; 524 - uint32_t val; 523 + u32 ws_image; 524 + u32 val; 525 525 526 526 /* 527 527 * Adjust DAC data polarity and set up Polarity Control Register image. ··· 575 575 * (write to non-existent trimdac). */ 576 576 val |= 0x00004000; /* Address the two main dual-DAC devices 577 577 * (TSL's chip select enables target device). */ 578 - val |= ((uint32_t)(chan & 1) << 15); /* Address the DAC channel 578 + val |= ((u32)(chan & 1) << 15); /* Address the DAC channel 579 579 * within the device. */ 580 - val |= (uint32_t)dacdata; /* Include DAC setpoint data. */ 580 + val |= (u32)dacdata; /* Include DAC setpoint data. */ 581 581 return s626_send_dac(dev, val); 582 582 } 583 583 ··· 585 585 u8 logical_chan, u8 dac_data) 586 586 { 587 587 struct s626_private *devpriv = dev->private; 588 - uint32_t chan; 588 + u32 chan; 589 589 590 590 /* 591 591 * Save the new setpoint in case the application needs to read it back ··· 672 672 * Write value into counter preload register. 673 673 */ 674 674 static void s626_preload(struct comedi_device *dev, 675 - unsigned int chan, uint32_t value) 675 + unsigned int chan, u32 value) 676 676 { 677 677 s626_debi_write(dev, S626_LP_CNTR(chan), value); 678 678 s626_debi_write(dev, S626_LP_CNTR(chan) + 2, value >> 16); ··· 1196 1196 * first uint16_t in the buffer because it contains junk data 1197 1197 * from the final ADC of the previous poll list scan. 1198 1198 */ 1199 - uint32_t *readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1; 1199 + u32 *readaddr = (u32 *)devpriv->ana_buf.logical_base + 1; 1200 1200 int i; 1201 1201 1202 1202 /* get the data and hand it over to comedi */ ··· 1231 1231 { 1232 1232 struct comedi_device *dev = d; 1233 1233 unsigned long flags; 1234 - uint32_t irqtype, irqstatus; 1234 + u32 irqtype, irqstatus; 1235 1235 1236 1236 if (!dev->attached) 1237 1237 return IRQ_NONE; ··· 1277 1277 struct s626_private *devpriv = dev->private; 1278 1278 struct comedi_subdevice *s = dev->read_subdev; 1279 1279 struct comedi_cmd *cmd = &s->async->cmd; 1280 - uint32_t *rps; 1281 - uint32_t jmp_adrs; 1280 + u32 *rps; 1281 + u32 jmp_adrs; 1282 1282 u16 i; 1283 1283 u16 n; 1284 - uint32_t local_ppl; 1284 + u32 local_ppl; 1285 1285 1286 1286 /* Stop RPS program in case it is currently running */ 1287 1287 s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1); 1288 1288 1289 1289 /* Set starting logical address to write RPS commands. */ 1290 - rps = (uint32_t *)devpriv->rps_buf.logical_base; 1290 + rps = (u32 *)devpriv->rps_buf.logical_base; 1291 1291 1292 1292 /* Initialize RPS instruction pointer */ 1293 - writel((uint32_t)devpriv->rps_buf.physical_base, 1293 + writel((u32)devpriv->rps_buf.physical_base, 1294 1294 dev->mmio + S626_P_RPSADDR1); 1295 1295 1296 1296 /* Construct RPS program in rps_buf DMA buffer */ ··· 1372 1372 * flushes the RPS' instruction prefetch pipeline. 1373 1373 */ 1374 1374 jmp_adrs = 1375 - (uint32_t)devpriv->rps_buf.physical_base + 1376 - (uint32_t)((unsigned long)rps - 1375 + (u32)devpriv->rps_buf.physical_base + 1376 + (u32)((unsigned long)rps - 1377 1377 (unsigned long)devpriv-> 1378 1378 rps_buf.logical_base); 1379 1379 for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) { ··· 1408 1408 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */ 1409 1409 *rps++ = S626_RPS_STREG | 1410 1410 (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2); 1411 - *rps++ = (uint32_t)devpriv->ana_buf.physical_base + 1411 + *rps++ = (u32)devpriv->ana_buf.physical_base + 1412 1412 (devpriv->adc_items << 2); 1413 1413 1414 1414 /* ··· 1452 1452 1453 1453 /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */ 1454 1454 *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2); 1455 - *rps++ = (uint32_t)devpriv->ana_buf.physical_base + 1455 + *rps++ = (u32)devpriv->ana_buf.physical_base + 1456 1456 (devpriv->adc_items << 2); 1457 1457 1458 1458 /* Indicate ADC scan loop is finished. */ ··· 1465 1465 1466 1466 /* Restart RPS program at its beginning. */ 1467 1467 *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */ 1468 - *rps++ = (uint32_t)devpriv->rps_buf.physical_base; 1468 + *rps++ = (u32)devpriv->rps_buf.physical_base; 1469 1469 1470 1470 /* End of RPS program build */ 1471 1471 } ··· 1491 1491 u16 chan = CR_CHAN(insn->chanspec); 1492 1492 u16 range = CR_RANGE(insn->chanspec); 1493 1493 u16 adc_spec = 0; 1494 - uint32_t gpio_image; 1495 - uint32_t tmp; 1494 + u32 gpio_image; 1495 + u32 tmp; 1496 1496 int ret; 1497 1497 int n; 1498 1498 ··· 2248 2248 */ 2249 2249 2250 2250 /* Physical start of RPS program */ 2251 - writel((uint32_t)devpriv->rps_buf.physical_base, 2251 + writel((u32)devpriv->rps_buf.physical_base, 2252 2252 dev->mmio + S626_P_RPSADDR1); 2253 2253 /* RPS program performs no explicit mem writes */ 2254 2254 writel(0, dev->mmio + S626_P_RPSPAGE1); ··· 2318 2318 * enabled. 2319 2319 */ 2320 2320 phys_buf = devpriv->ana_buf.physical_base + 2321 - (S626_DAC_WDMABUF_OS * sizeof(uint32_t)); 2322 - writel((uint32_t)phys_buf, dev->mmio + S626_P_BASEA2_OUT); 2323 - writel((uint32_t)(phys_buf + sizeof(uint32_t)), 2321 + (S626_DAC_WDMABUF_OS * sizeof(u32)); 2322 + writel((u32)phys_buf, dev->mmio + S626_P_BASEA2_OUT); 2323 + writel((u32)(phys_buf + sizeof(u32)), 2324 2324 dev->mmio + S626_P_PROTA2_OUT); 2325 2325 2326 2326 /* 2327 2327 * Cache Audio2's output DMA buffer logical address. This is 2328 2328 * where DAC data is buffered for A2 output DMA transfers. 2329 2329 */ 2330 - devpriv->dac_wbuf = (uint32_t *)devpriv->ana_buf.logical_base + 2330 + devpriv->dac_wbuf = (u32 *)devpriv->ana_buf.logical_base + 2331 2331 S626_DAC_WDMABUF_OS; 2332 2332 2333 2333 /*