dt-bindings: clk: g12a-clks: expose all clock ids

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every g12a-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-9-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

authored by

Neil Armstrong and committed by

Jerome Brunet 2 years ago b1262497 8fdbdc79

+130 -140

2 changed files

expand all

drivers

clk

meson

g12a.h

include

dt-bindings

clock

g12a-clkc.h

-140

drivers/clk/meson/g12a.h

··· 126 126 #define HHI_SYS1_PLL_CNTL5 0x394 127 127 #define HHI_SYS1_PLL_CNTL6 0x398 128 128 129 - /* 130 - * CLKID index values 131 - * 132 - * These indices are entirely contrived and do not map onto the hardware. 133 - * It has now been decided to expose everything by default in the DT header: 134 - * include/dt-bindings/clock/g12a-clkc.h. Only the clocks ids we don't want 135 - * to expose, such as the internal muxes and dividers of composite clocks, 136 - * will remain defined here. 137 - */ 138 - #define CLKID_MPEG_SEL 8 139 - #define CLKID_MPEG_DIV 9 140 - #define CLKID_SD_EMMC_A_CLK0_SEL 63 141 - #define CLKID_SD_EMMC_A_CLK0_DIV 64 142 - #define CLKID_SD_EMMC_B_CLK0_SEL 65 143 - #define CLKID_SD_EMMC_B_CLK0_DIV 66 144 - #define CLKID_SD_EMMC_C_CLK0_SEL 67 145 - #define CLKID_SD_EMMC_C_CLK0_DIV 68 146 - #define CLKID_MPLL0_DIV 69 147 - #define CLKID_MPLL1_DIV 70 148 - #define CLKID_MPLL2_DIV 71 149 - #define CLKID_MPLL3_DIV 72 150 - #define CLKID_MPLL_PREDIV 73 151 - #define CLKID_FCLK_DIV2_DIV 75 152 - #define CLKID_FCLK_DIV3_DIV 76 153 - #define CLKID_FCLK_DIV4_DIV 77 154 - #define CLKID_FCLK_DIV5_DIV 78 155 - #define CLKID_FCLK_DIV7_DIV 79 156 - #define CLKID_FCLK_DIV2P5_DIV 100 157 - #define CLKID_FIXED_PLL_DCO 101 158 - #define CLKID_SYS_PLL_DCO 102 159 - #define CLKID_GP0_PLL_DCO 103 160 - #define CLKID_HIFI_PLL_DCO 104 161 - #define CLKID_VPU_0_DIV 111 162 - #define CLKID_VPU_1_DIV 114 163 - #define CLKID_VAPB_0_DIV 118 164 - #define CLKID_VAPB_1_DIV 121 165 - #define CLKID_HDMI_PLL_DCO 125 166 - #define CLKID_HDMI_PLL_OD 126 167 - #define CLKID_HDMI_PLL_OD2 127 168 - #define CLKID_VID_PLL_SEL 130 169 - #define CLKID_VID_PLL_DIV 131 170 - #define CLKID_VCLK_SEL 132 171 - #define CLKID_VCLK2_SEL 133 172 - #define CLKID_VCLK_INPUT 134 173 - #define CLKID_VCLK2_INPUT 135 174 - #define CLKID_VCLK_DIV 136 175 - #define CLKID_VCLK2_DIV 137 176 - #define CLKID_VCLK_DIV2_EN 140 177 - #define CLKID_VCLK_DIV4_EN 141 178 - #define CLKID_VCLK_DIV6_EN 142 179 - #define CLKID_VCLK_DIV12_EN 143 180 - #define CLKID_VCLK2_DIV2_EN 144 181 - #define CLKID_VCLK2_DIV4_EN 145 182 - #define CLKID_VCLK2_DIV6_EN 146 183 - #define CLKID_VCLK2_DIV12_EN 147 184 - #define CLKID_CTS_ENCI_SEL 158 185 - #define CLKID_CTS_ENCP_SEL 159 186 - #define CLKID_CTS_VDAC_SEL 160 187 - #define CLKID_HDMI_TX_SEL 161 188 - #define CLKID_HDMI_SEL 166 189 - #define CLKID_HDMI_DIV 167 190 - #define CLKID_MALI_0_DIV 170 191 - #define CLKID_MALI_1_DIV 173 192 - #define CLKID_MPLL_50M_DIV 176 193 - #define CLKID_SYS_PLL_DIV16_EN 178 194 - #define CLKID_SYS_PLL_DIV16 179 195 - #define CLKID_CPU_CLK_DYN0_SEL 180 196 - #define CLKID_CPU_CLK_DYN0_DIV 181 197 - #define CLKID_CPU_CLK_DYN0 182 198 - #define CLKID_CPU_CLK_DYN1_SEL 183 199 - #define CLKID_CPU_CLK_DYN1_DIV 184 200 - #define CLKID_CPU_CLK_DYN1 185 201 - #define CLKID_CPU_CLK_DYN 186 202 - #define CLKID_CPU_CLK_DIV16_EN 188 203 - #define CLKID_CPU_CLK_DIV16 189 204 - #define CLKID_CPU_CLK_APB_DIV 190 205 - #define CLKID_CPU_CLK_APB 191 206 - #define CLKID_CPU_CLK_ATB_DIV 192 207 - #define CLKID_CPU_CLK_ATB 193 208 - #define CLKID_CPU_CLK_AXI_DIV 194 209 - #define CLKID_CPU_CLK_AXI 195 210 - #define CLKID_CPU_CLK_TRACE_DIV 196 211 - #define CLKID_CPU_CLK_TRACE 197 212 - #define CLKID_PCIE_PLL_DCO 198 213 - #define CLKID_PCIE_PLL_DCO_DIV2 199 214 - #define CLKID_PCIE_PLL_OD 200 215 - #define CLKID_VDEC_1_SEL 202 216 - #define CLKID_VDEC_1_DIV 203 217 - #define CLKID_VDEC_HEVC_SEL 205 218 - #define CLKID_VDEC_HEVC_DIV 206 219 - #define CLKID_VDEC_HEVCF_SEL 208 220 - #define CLKID_VDEC_HEVCF_DIV 209 221 - #define CLKID_TS_DIV 211 222 - #define CLKID_SYS1_PLL_DCO 213 223 - #define CLKID_SYS1_PLL 214 224 - #define CLKID_SYS1_PLL_DIV16_EN 215 225 - #define CLKID_SYS1_PLL_DIV16 216 226 - #define CLKID_CPUB_CLK_DYN0_SEL 217 227 - #define CLKID_CPUB_CLK_DYN0_DIV 218 228 - #define CLKID_CPUB_CLK_DYN0 219 229 - #define CLKID_CPUB_CLK_DYN1_SEL 220 230 - #define CLKID_CPUB_CLK_DYN1_DIV 221 231 - #define CLKID_CPUB_CLK_DYN1 222 232 - #define CLKID_CPUB_CLK_DYN 223 233 - #define CLKID_CPUB_CLK_DIV16_EN 225 234 - #define CLKID_CPUB_CLK_DIV16 226 235 - #define CLKID_CPUB_CLK_DIV2 227 236 - #define CLKID_CPUB_CLK_DIV3 228 237 - #define CLKID_CPUB_CLK_DIV4 229 238 - #define CLKID_CPUB_CLK_DIV5 230 239 - #define CLKID_CPUB_CLK_DIV6 231 240 - #define CLKID_CPUB_CLK_DIV7 232 241 - #define CLKID_CPUB_CLK_DIV8 233 242 - #define CLKID_CPUB_CLK_APB_SEL 234 243 - #define CLKID_CPUB_CLK_APB 235 244 - #define CLKID_CPUB_CLK_ATB_SEL 236 245 - #define CLKID_CPUB_CLK_ATB 237 246 - #define CLKID_CPUB_CLK_AXI_SEL 238 247 - #define CLKID_CPUB_CLK_AXI 239 248 - #define CLKID_CPUB_CLK_TRACE_SEL 240 249 - #define CLKID_CPUB_CLK_TRACE 241 250 - #define CLKID_GP1_PLL_DCO 242 251 - #define CLKID_DSU_CLK_DYN0_SEL 244 252 - #define CLKID_DSU_CLK_DYN0_DIV 245 253 - #define CLKID_DSU_CLK_DYN0 246 254 - #define CLKID_DSU_CLK_DYN1_SEL 247 255 - #define CLKID_DSU_CLK_DYN1_DIV 248 256 - #define CLKID_DSU_CLK_DYN1 249 257 - #define CLKID_DSU_CLK_DYN 250 258 - #define CLKID_DSU_CLK_FINAL 251 259 - #define CLKID_SPICC0_SCLK_SEL 256 260 - #define CLKID_SPICC0_SCLK_DIV 257 261 - #define CLKID_SPICC1_SCLK_SEL 259 262 - #define CLKID_SPICC1_SCLK_DIV 260 263 - #define CLKID_NNA_AXI_CLK_SEL 262 264 - #define CLKID_NNA_AXI_CLK_DIV 263 265 - #define CLKID_NNA_CORE_CLK_SEL 265 266 - #define CLKID_NNA_CORE_CLK_DIV 266 267 - #define CLKID_MIPI_DSI_PXCLK_DIV 268 268 - 269 129 /* include the CLKIDs that have been made part of the DT binding */ 270 130 #include <dt-bindings/clock/g12a-clkc.h> 271 131

+130

include/dt-bindings/clock/g12a-clkc.h

··· 16 16 #define CLKID_FCLK_DIV5 5 17 17 #define CLKID_FCLK_DIV7 6 18 18 #define CLKID_GP0_PLL 7 19 + #define CLKID_MPEG_SEL 8 20 + #define CLKID_MPEG_DIV 9 19 21 #define CLKID_CLK81 10 20 22 #define CLKID_MPLL0 11 21 23 #define CLKID_MPLL1 12 ··· 71 69 #define CLKID_SD_EMMC_A_CLK0 60 72 70 #define CLKID_SD_EMMC_B_CLK0 61 73 71 #define CLKID_SD_EMMC_C_CLK0 62 72 + #define CLKID_SD_EMMC_A_CLK0_SEL 63 73 + #define CLKID_SD_EMMC_A_CLK0_DIV 64 74 + #define CLKID_SD_EMMC_B_CLK0_SEL 65 75 + #define CLKID_SD_EMMC_B_CLK0_DIV 66 76 + #define CLKID_SD_EMMC_C_CLK0_SEL 67 77 + #define CLKID_SD_EMMC_C_CLK0_DIV 68 78 + #define CLKID_MPLL0_DIV 69 79 + #define CLKID_MPLL1_DIV 70 80 + #define CLKID_MPLL2_DIV 71 81 + #define CLKID_MPLL3_DIV 72 82 + #define CLKID_MPLL_PREDIV 73 74 83 #define CLKID_HIFI_PLL 74 84 + #define CLKID_FCLK_DIV2_DIV 75 85 + #define CLKID_FCLK_DIV3_DIV 76 86 + #define CLKID_FCLK_DIV4_DIV 77 87 + #define CLKID_FCLK_DIV5_DIV 78 88 + #define CLKID_FCLK_DIV7_DIV 79 75 89 #define CLKID_VCLK2_VENCI0 80 76 90 #define CLKID_VCLK2_VENCI1 81 77 91 #define CLKID_VCLK2_VENCP0 82 ··· 108 90 #define CLKID_VCLK2_VENCL 97 109 91 #define CLKID_VCLK2_OTHER1 98 110 92 #define CLKID_FCLK_DIV2P5 99 93 + #define CLKID_FCLK_DIV2P5_DIV 100 94 + #define CLKID_FIXED_PLL_DCO 101 95 + #define CLKID_SYS_PLL_DCO 102 96 + #define CLKID_GP0_PLL_DCO 103 97 + #define CLKID_HIFI_PLL_DCO 104 111 98 #define CLKID_DMA 105 112 99 #define CLKID_EFUSE 106 113 100 #define CLKID_ROM_BOOT 107 114 101 #define CLKID_RESET_SEC 108 115 102 #define CLKID_SEC_AHB_APB3 109 116 103 #define CLKID_VPU_0_SEL 110 104 + #define CLKID_VPU_0_DIV 111 117 105 #define CLKID_VPU_0 112 118 106 #define CLKID_VPU_1_SEL 113 107 + #define CLKID_VPU_1_DIV 114 119 108 #define CLKID_VPU_1 115 120 109 #define CLKID_VPU 116 121 110 #define CLKID_VAPB_0_SEL 117 111 + #define CLKID_VAPB_0_DIV 118 122 112 #define CLKID_VAPB_0 119 123 113 #define CLKID_VAPB_1_SEL 120 114 + #define CLKID_VAPB_1_DIV 121 124 115 #define CLKID_VAPB_1 122 125 116 #define CLKID_VAPB_SEL 123 126 117 #define CLKID_VAPB 124 118 + #define CLKID_HDMI_PLL_DCO 125 119 + #define CLKID_HDMI_PLL_OD 126 120 + #define CLKID_HDMI_PLL_OD2 127 127 121 #define CLKID_HDMI_PLL 128 128 122 #define CLKID_VID_PLL 129 123 + #define CLKID_VID_PLL_SEL 130 124 + #define CLKID_VID_PLL_DIV 131 125 + #define CLKID_VCLK_SEL 132 126 + #define CLKID_VCLK2_SEL 133 127 + #define CLKID_VCLK_INPUT 134 128 + #define CLKID_VCLK2_INPUT 135 129 + #define CLKID_VCLK_DIV 136 130 + #define CLKID_VCLK2_DIV 137 129 131 #define CLKID_VCLK 138 130 132 #define CLKID_VCLK2 139 133 + #define CLKID_VCLK_DIV2_EN 140 134 + #define CLKID_VCLK_DIV4_EN 141 135 + #define CLKID_VCLK_DIV6_EN 142 136 + #define CLKID_VCLK_DIV12_EN 143 137 + #define CLKID_VCLK2_DIV2_EN 144 138 + #define CLKID_VCLK2_DIV4_EN 145 139 + #define CLKID_VCLK2_DIV6_EN 146 140 + #define CLKID_VCLK2_DIV12_EN 147 131 141 #define CLKID_VCLK_DIV1 148 132 142 #define CLKID_VCLK_DIV2 149 133 143 #define CLKID_VCLK_DIV4 150 ··· 166 120 #define CLKID_VCLK2_DIV4 155 167 121 #define CLKID_VCLK2_DIV6 156 168 122 #define CLKID_VCLK2_DIV12 157 123 + #define CLKID_CTS_ENCI_SEL 158 124 + #define CLKID_CTS_ENCP_SEL 159 125 + #define CLKID_CTS_VDAC_SEL 160 126 + #define CLKID_HDMI_TX_SEL 161 169 127 #define CLKID_CTS_ENCI 162 170 128 #define CLKID_CTS_ENCP 163 171 129 #define CLKID_CTS_VDAC 164 172 130 #define CLKID_HDMI_TX 165 131 + #define CLKID_HDMI_SEL 166 132 + #define CLKID_HDMI_DIV 167 173 133 #define CLKID_HDMI 168 174 134 #define CLKID_MALI_0_SEL 169 135 + #define CLKID_MALI_0_DIV 170 175 136 #define CLKID_MALI_0 171 176 137 #define CLKID_MALI_1_SEL 172 138 + #define CLKID_MALI_1_DIV 173 177 139 #define CLKID_MALI_1 174 178 140 #define CLKID_MALI 175 141 + #define CLKID_MPLL_50M_DIV 176 179 142 #define CLKID_MPLL_50M 177 143 + #define CLKID_SYS_PLL_DIV16_EN 178 144 + #define CLKID_SYS_PLL_DIV16 179 145 + #define CLKID_CPU_CLK_DYN0_SEL 180 146 + #define CLKID_CPU_CLK_DYN0_DIV 181 147 + #define CLKID_CPU_CLK_DYN0 182 148 + #define CLKID_CPU_CLK_DYN1_SEL 183 149 + #define CLKID_CPU_CLK_DYN1_DIV 184 150 + #define CLKID_CPU_CLK_DYN1 185 151 + #define CLKID_CPU_CLK_DYN 186 180 152 #define CLKID_CPU_CLK 187 153 + #define CLKID_CPU_CLK_DIV16_EN 188 154 + #define CLKID_CPU_CLK_DIV16 189 155 + #define CLKID_CPU_CLK_APB_DIV 190 156 + #define CLKID_CPU_CLK_APB 191 157 + #define CLKID_CPU_CLK_ATB_DIV 192 158 + #define CLKID_CPU_CLK_ATB 193 159 + #define CLKID_CPU_CLK_AXI_DIV 194 160 + #define CLKID_CPU_CLK_AXI 195 161 + #define CLKID_CPU_CLK_TRACE_DIV 196 162 + #define CLKID_CPU_CLK_TRACE 197 163 + #define CLKID_PCIE_PLL_DCO 198 164 + #define CLKID_PCIE_PLL_DCO_DIV2 199 165 + #define CLKID_PCIE_PLL_OD 200 181 166 #define CLKID_PCIE_PLL 201 167 + #define CLKID_VDEC_1_SEL 202 168 + #define CLKID_VDEC_1_DIV 203 182 169 #define CLKID_VDEC_1 204 170 + #define CLKID_VDEC_HEVC_SEL 205 171 + #define CLKID_VDEC_HEVC_DIV 206 183 172 #define CLKID_VDEC_HEVC 207 173 + #define CLKID_VDEC_HEVCF_SEL 208 174 + #define CLKID_VDEC_HEVCF_DIV 209 184 175 #define CLKID_VDEC_HEVCF 210 176 + #define CLKID_TS_DIV 211 185 177 #define CLKID_TS 212 178 + #define CLKID_SYS1_PLL_DCO 213 179 + #define CLKID_SYS1_PLL 214 180 + #define CLKID_SYS1_PLL_DIV16_EN 215 181 + #define CLKID_SYS1_PLL_DIV16 216 182 + #define CLKID_CPUB_CLK_DYN0_SEL 217 183 + #define CLKID_CPUB_CLK_DYN0_DIV 218 184 + #define CLKID_CPUB_CLK_DYN0 219 185 + #define CLKID_CPUB_CLK_DYN1_SEL 220 186 + #define CLKID_CPUB_CLK_DYN1_DIV 221 187 + #define CLKID_CPUB_CLK_DYN1 222 188 + #define CLKID_CPUB_CLK_DYN 223 186 189 #define CLKID_CPUB_CLK 224 190 + #define CLKID_CPUB_CLK_DIV16_EN 225 191 + #define CLKID_CPUB_CLK_DIV16 226 192 + #define CLKID_CPUB_CLK_DIV2 227 193 + #define CLKID_CPUB_CLK_DIV3 228 194 + #define CLKID_CPUB_CLK_DIV4 229 195 + #define CLKID_CPUB_CLK_DIV5 230 196 + #define CLKID_CPUB_CLK_DIV6 231 197 + #define CLKID_CPUB_CLK_DIV7 232 198 + #define CLKID_CPUB_CLK_DIV8 233 199 + #define CLKID_CPUB_CLK_APB_SEL 234 200 + #define CLKID_CPUB_CLK_APB 235 201 + #define CLKID_CPUB_CLK_ATB_SEL 236 202 + #define CLKID_CPUB_CLK_ATB 237 203 + #define CLKID_CPUB_CLK_AXI_SEL 238 204 + #define CLKID_CPUB_CLK_AXI 239 205 + #define CLKID_CPUB_CLK_TRACE_SEL 240 206 + #define CLKID_CPUB_CLK_TRACE 241 207 + #define CLKID_GP1_PLL_DCO 242 187 208 #define CLKID_GP1_PLL 243 209 + #define CLKID_DSU_CLK_DYN0_SEL 244 210 + #define CLKID_DSU_CLK_DYN0_DIV 245 211 + #define CLKID_DSU_CLK_DYN0 246 212 + #define CLKID_DSU_CLK_DYN1_SEL 247 213 + #define CLKID_DSU_CLK_DYN1_DIV 248 214 + #define CLKID_DSU_CLK_DYN1 249 215 + #define CLKID_DSU_CLK_DYN 250 216 + #define CLKID_DSU_CLK_FINAL 251 188 217 #define CLKID_DSU_CLK 252 189 218 #define CLKID_CPU1_CLK 253 190 219 #define CLKID_CPU2_CLK 254 191 220 #define CLKID_CPU3_CLK 255 221 + #define CLKID_SPICC0_SCLK_SEL 256 222 + #define CLKID_SPICC0_SCLK_DIV 257 192 223 #define CLKID_SPICC0_SCLK 258 224 + #define CLKID_SPICC1_SCLK_SEL 259 225 + #define CLKID_SPICC1_SCLK_DIV 260 193 226 #define CLKID_SPICC1_SCLK 261 227 + #define CLKID_NNA_AXI_CLK_SEL 262 228 + #define CLKID_NNA_AXI_CLK_DIV 263 194 229 #define CLKID_NNA_AXI_CLK 264 230 + #define CLKID_NNA_CORE_CLK_SEL 265 231 + #define CLKID_NNA_CORE_CLK_DIV 266 195 232 #define CLKID_NNA_CORE_CLK 267 233 + #define CLKID_MIPI_DSI_PXCLK_DIV 268 196 234 #define CLKID_MIPI_DSI_PXCLK_SEL 269 197 235 #define CLKID_MIPI_DSI_PXCLK 270 198 236