tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
frv: Rewrite atomic implementation
Mostly complete rewrite of the FRV atomic implementation, instead of
using assembly files, use inline assembler.
The out-of-line CONFIG option makes a bit of a mess of things, but a
little CPP trickery gets that done too.
FRV already had the atomic logic ops but under a non standard name,
the reimplementation provides the generic names and provides the
intermediate form required for the bitops implementation.
The slightly inconsistent __atomic32_fetch_##op naming is because
__atomic_fetch_##op conlicts with GCC builtin functions.
The 64bit atomic ops use the inline assembly %Ln construct to access
the low word register (r+1), afaik this construct was not previously
used in the kernel and is completely undocumented, but I found it in
the FRV GCC code and it seems to work.
FRV had a non-standard definition of atomic_{clear,set}_mask() which
would work types other than atomic_t, the one user relying on that
(arch/frv/kernel/dma.c) got converted to use the new intermediate
form.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
authored by
Peter Zijlstra
and committed by
Thomas Gleixner
b0d8003e
7fc1845d
+260
-356
+67
-54
arch/frv/include/asm/atomic.h
+67
-54
arch/frv/include/asm/atomic.h
···
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#define _ASM_ATOMIC_H
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#include <linux/types.h>
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#include <asm/spr-regs.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#ifdef CONFIG_SMP
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#error not SMP safe
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#endif
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#include <asm/atomic_defs.h>
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/*
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* Atomic operations that C can't guarantee us. Useful for
···
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#define atomic_read(v) ACCESS_ONCE((v)->counter)
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#define atomic_set(v, i) (((v)->counter) = (i))
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#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
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static inline int atomic_inc_return(atomic_t *v)
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{
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return __atomic_add_return(1, &v->counter);
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}
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static inline int atomic_dec_return(atomic_t *v)
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{
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return __atomic_sub_return(1, &v->counter);
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}
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+
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned long val;
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asm("0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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" ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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" add%I2 %1,%2,%1 \n"
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" cst.p %1,%M0 ,cc3,#1 \n"
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
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" beq icc3,#0,0b \n"
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: "+U"(v->counter), "=&r"(val)
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: "NPr"(i)
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: "memory", "cc7", "cc3", "icc3"
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);
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return val;
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return __atomic_add_return(i, &v->counter);
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned long val;
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asm("0: \n"
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
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" ckeq icc3,cc7 \n"
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" ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
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" sub%I2 %1,%2,%1 \n"
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" cst.p %1,%M0 ,cc3,#1 \n"
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
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" beq icc3,#0,0b \n"
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: "+U"(v->counter), "=&r"(val)
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: "NPr"(i)
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: "memory", "cc7", "cc3", "icc3"
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);
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return val;
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return __atomic_sub_return(i, &v->counter);
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}
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#else
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extern int atomic_add_return(int i, atomic_t *v);
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extern int atomic_sub_return(int i, atomic_t *v);
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#endif
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static inline int atomic_add_negative(int i, atomic_t *v)
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{
···
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static inline void atomic_inc(atomic_t *v)
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{
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atomic_add_return(1, v);
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atomic_inc_return(v);
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}
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static inline void atomic_dec(atomic_t *v)
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{
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atomic_sub_return(1, v);
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atomic_dec_return(v);
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}
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#define atomic_dec_return(v) atomic_sub_return(1, (v))
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#define atomic_inc_return(v) atomic_add_return(1, (v))
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#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
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#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
···
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* 64-bit atomic ops
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*/
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typedef struct {
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volatile long long counter;
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long long counter;
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} atomic64_t;
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#define ATOMIC64_INIT(i) { (i) }
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static inline long long atomic64_read(atomic64_t *v)
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static inline long long atomic64_read(const atomic64_t *v)
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{
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long long counter;
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asm("ldd%I1 %M1,%0"
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: "=e"(counter)
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: "m"(v->counter));
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return counter;
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}
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···
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: "e"(i));
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}
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extern long long atomic64_inc_return(atomic64_t *v);
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extern long long atomic64_dec_return(atomic64_t *v);
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extern long long atomic64_add_return(long long i, atomic64_t *v);
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extern long long atomic64_sub_return(long long i, atomic64_t *v);
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static inline long long atomic64_inc_return(atomic64_t *v)
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{
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return __atomic64_add_return(1, &v->counter);
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}
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static inline long long atomic64_dec_return(atomic64_t *v)
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{
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return __atomic64_sub_return(1, &v->counter);
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}
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static inline long long atomic64_add_return(long long i, atomic64_t *v)
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{
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return __atomic64_add_return(i, &v->counter);
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}
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static inline long long atomic64_sub_return(long long i, atomic64_t *v)
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{
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return __atomic64_sub_return(i, &v->counter);
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}
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static inline long long atomic64_add_negative(long long i, atomic64_t *v)
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{
···
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#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
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#define atomic64_inc_and_test(v) (atomic64_inc_return((v)) == 0)
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#define atomic_cmpxchg(v, old, new) (cmpxchg(&(v)->counter, old, new))
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#define atomic_xchg(v, new) (xchg(&(v)->counter, new))
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#define atomic64_cmpxchg(v, old, new) (__cmpxchg_64(old, new, &(v)->counter))
···
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return c;
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}
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#define ATOMIC_OP(op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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(void)__atomic32_fetch_##op(i, &v->counter); \
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} \
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\
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static inline void atomic64_##op(long long i, atomic64_t *v) \
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{ \
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(void)__atomic64_fetch_##op(i, &v->counter); \
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}
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#define CONFIG_ARCH_HAS_ATOMIC_OR
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ATOMIC_OP(or)
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ATOMIC_OP(and)
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ATOMIC_OP(xor)
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#undef ATOMIC_OP
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static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t *v)
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{
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atomic_and(~mask, v);
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}
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static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
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{
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atomic_or(mask, v);
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}
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#endif /* _ASM_ATOMIC_H */
+172
arch/frv/include/asm/atomic_defs.h
+172
arch/frv/include/asm/atomic_defs.h
···
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#include <asm/spr-regs.h>
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#ifdef __ATOMIC_LIB__
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#ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
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#define ATOMIC_QUALS
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#define ATOMIC_EXPORT(x) EXPORT_SYMBOL(x)
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#else /* !OUTOFLINE && LIB */
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#define ATOMIC_OP_RETURN(op)
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#define ATOMIC_FETCH_OP(op)
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#endif /* OUTOFLINE */
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#else /* !__ATOMIC_LIB__ */
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#define ATOMIC_EXPORT(x)
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#ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
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#define ATOMIC_OP_RETURN(op) \
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extern int __atomic_##op##_return(int i, int *v); \
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extern long long __atomic64_##op##_return(long long i, long long *v);
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#define ATOMIC_FETCH_OP(op) \
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extern int __atomic32_fetch_##op(int i, int *v); \
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extern long long __atomic64_fetch_##op(long long i, long long *v);
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32
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#else /* !OUTOFLINE && !LIB */
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#define ATOMIC_QUALS static inline
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#endif /* OUTOFLINE */
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#endif /* __ATOMIC_LIB__ */
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/*
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* Note on the 64 bit inline asm variants...
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*
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* CSTD is a conditional instruction and needs a constrained memory reference.
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* Normally 'U' provides the correct constraints for conditional instructions
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* and this is used for the 32 bit version, however 'U' does not appear to work
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* for 64 bit values (gcc-4.9)
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*
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* The exact constraint is that conditional instructions cannot deal with an
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* immediate displacement in the memory reference, so what we do is we read the
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* address through a volatile cast into a local variable in order to insure we
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* _have_ to compute the correct address without displacement. This allows us
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* to use the regular 'm' for the memory address.
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*
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* Furthermore, the %Ln operand, which prints the low word register (r+1),
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* really only works for registers, this means we cannot allow immediate values
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* for the 64 bit versions -- like we do for the 32 bit ones.
57
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*
58
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*/
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#ifndef ATOMIC_OP_RETURN
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#define ATOMIC_OP_RETURN(op) \
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ATOMIC_QUALS int __atomic_##op##_return(int i, int *v) \
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{ \
64
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int val; \
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\
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asm volatile( \
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"0: \n" \
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" orcc gr0,gr0,gr0,icc3 \n" \
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" ckeq icc3,cc7 \n" \
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" ld.p %M0,%1 \n" \
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" orcr cc7,cc7,cc3 \n" \
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" "#op"%I2 %1,%2,%1 \n" \
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" cst.p %1,%M0 ,cc3,#1 \n" \
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" \
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" beq icc3,#0,0b \n" \
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: "+U"(*v), "=&r"(val) \
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: "NPr"(i) \
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: "memory", "cc7", "cc3", "icc3" \
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); \
80
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\
81
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return val; \
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} \
83
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ATOMIC_EXPORT(__atomic_##op##_return); \
84
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\
85
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ATOMIC_QUALS long long __atomic64_##op##_return(long long i, long long *v) \
86
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{ \
87
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long long *__v = READ_ONCE(v); \
88
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long long val; \
89
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\
90
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asm volatile( \
91
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"0: \n" \
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" orcc gr0,gr0,gr0,icc3 \n" \
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" ckeq icc3,cc7 \n" \
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" ldd.p %M0,%1 \n" \
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" orcr cc7,cc7,cc3 \n" \
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" "#op"cc %L1,%L2,%L1,icc0 \n" \
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" "#op"x %1,%2,%1,icc0 \n" \
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" cstd.p %1,%M0 ,cc3,#1 \n" \
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" \
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" beq icc3,#0,0b \n" \
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: "+m"(*__v), "=&e"(val) \
102
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: "e"(i) \
103
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: "memory", "cc7", "cc3", "icc0", "icc3" \
104
+
); \
105
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\
106
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return val; \
107
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} \
108
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ATOMIC_EXPORT(__atomic64_##op##_return);
109
+
#endif
110
+
111
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#ifndef ATOMIC_FETCH_OP
112
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#define ATOMIC_FETCH_OP(op) \
113
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ATOMIC_QUALS int __atomic32_fetch_##op(int i, int *v) \
114
+
{ \
115
+
int old, tmp; \
116
+
\
117
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asm volatile( \
118
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"0: \n" \
119
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" orcc gr0,gr0,gr0,icc3 \n" \
120
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" ckeq icc3,cc7 \n" \
121
+
" ld.p %M0,%1 \n" \
122
+
" orcr cc7,cc7,cc3 \n" \
123
+
" "#op"%I3 %1,%3,%2 \n" \
124
+
" cst.p %2,%M0 ,cc3,#1 \n" \
125
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" \
126
+
" beq icc3,#0,0b \n" \
127
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: "+U"(*v), "=&r"(old), "=r"(tmp) \
128
+
: "NPr"(i) \
129
+
: "memory", "cc7", "cc3", "icc3" \
130
+
); \
131
+
\
132
+
return old; \
133
+
} \
134
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ATOMIC_EXPORT(__atomic32_fetch_##op); \
135
+
\
136
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ATOMIC_QUALS long long __atomic64_fetch_##op(long long i, long long *v) \
137
+
{ \
138
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long long *__v = READ_ONCE(v); \
139
+
long long old, tmp; \
140
+
\
141
+
asm volatile( \
142
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"0: \n" \
143
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" orcc gr0,gr0,gr0,icc3 \n" \
144
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" ckeq icc3,cc7 \n" \
145
+
" ldd.p %M0,%1 \n" \
146
+
" orcr cc7,cc7,cc3 \n" \
147
+
" "#op" %L1,%L3,%L2 \n" \
148
+
" "#op" %1,%3,%2 \n" \
149
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" cstd.p %2,%M0 ,cc3,#1 \n" \
150
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" \
151
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" beq icc3,#0,0b \n" \
152
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: "+m"(*__v), "=&e"(old), "=e"(tmp) \
153
+
: "e"(i) \
154
+
: "memory", "cc7", "cc3", "icc3" \
155
+
); \
156
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\
157
+
return old; \
158
+
} \
159
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ATOMIC_EXPORT(__atomic64_fetch_##op);
160
+
#endif
161
+
162
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ATOMIC_FETCH_OP(or)
163
+
ATOMIC_FETCH_OP(and)
164
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ATOMIC_FETCH_OP(xor)
165
+
166
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ATOMIC_OP_RETURN(add)
167
+
ATOMIC_OP_RETURN(sub)
168
+
169
+
#undef ATOMIC_FETCH_OP
170
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#undef ATOMIC_OP_RETURN
171
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#undef ATOMIC_QUALS
172
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#undef ATOMIC_EXPORT
+10
-89
arch/frv/include/asm/bitops.h
+10
-89
arch/frv/include/asm/bitops.h
···
25
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26
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#include <asm-generic/bitops/ffz.h>
27
27
28
-
#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
29
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static inline
30
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unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v)
31
-
{
32
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unsigned long old, tmp;
33
-
34
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asm volatile(
35
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"0: \n"
36
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
37
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" ckeq icc3,cc7 \n"
38
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" ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
39
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" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
40
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" and%I3 %1,%3,%2 \n"
41
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" cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
42
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
43
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" beq icc3,#0,0b \n"
44
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: "+U"(*v), "=&r"(old), "=r"(tmp)
45
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: "NPr"(~mask)
46
-
: "memory", "cc7", "cc3", "icc3"
47
-
);
48
-
49
-
return old;
50
-
}
51
-
52
-
static inline
53
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unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v)
54
-
{
55
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unsigned long old, tmp;
56
-
57
-
asm volatile(
58
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"0: \n"
59
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" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
60
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" ckeq icc3,cc7 \n"
61
-
" ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
62
-
" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
63
-
" or%I3 %1,%3,%2 \n"
64
-
" cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
65
-
" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
66
-
" beq icc3,#0,0b \n"
67
-
: "+U"(*v), "=&r"(old), "=r"(tmp)
68
-
: "NPr"(mask)
69
-
: "memory", "cc7", "cc3", "icc3"
70
-
);
71
-
72
-
return old;
73
-
}
74
-
75
-
static inline
76
-
unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v)
77
-
{
78
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unsigned long old, tmp;
79
-
80
-
asm volatile(
81
-
"0: \n"
82
-
" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
83
-
" ckeq icc3,cc7 \n"
84
-
" ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
85
-
" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
86
-
" xor%I3 %1,%3,%2 \n"
87
-
" cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
88
-
" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
89
-
" beq icc3,#0,0b \n"
90
-
: "+U"(*v), "=&r"(old), "=r"(tmp)
91
-
: "NPr"(mask)
92
-
: "memory", "cc7", "cc3", "icc3"
93
-
);
94
-
95
-
return old;
96
-
}
97
-
98
-
#else
99
-
100
-
extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v);
101
-
extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v);
102
-
extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v);
103
-
104
-
#endif
105
-
106
-
#define atomic_clear_mask(mask, v) atomic_test_and_ANDNOT_mask((mask), (v))
107
-
#define atomic_set_mask(mask, v) atomic_test_and_OR_mask((mask), (v))
28
+
#include <asm/atomic.h>
108
29
109
30
static inline int test_and_clear_bit(unsigned long nr, volatile void *addr)
110
31
{
111
-
volatile unsigned long *ptr = addr;
112
-
unsigned long mask = 1UL << (nr & 31);
32
+
unsigned int *ptr = (void *)addr;
33
+
unsigned int mask = 1UL << (nr & 31);
113
34
ptr += nr >> 5;
114
-
return (atomic_test_and_ANDNOT_mask(mask, ptr) & mask) != 0;
35
+
return (__atomic32_fetch_and(~mask, ptr) & mask) != 0;
115
36
}
116
37
117
38
static inline int test_and_set_bit(unsigned long nr, volatile void *addr)
118
39
{
119
-
volatile unsigned long *ptr = addr;
120
-
unsigned long mask = 1UL << (nr & 31);
40
+
unsigned int *ptr = (void *)addr;
41
+
unsigned int mask = 1UL << (nr & 31);
121
42
ptr += nr >> 5;
122
-
return (atomic_test_and_OR_mask(mask, ptr) & mask) != 0;
43
+
return (__atomic32_fetch_or(mask, ptr) & mask) != 0;
123
44
}
124
45
125
46
static inline int test_and_change_bit(unsigned long nr, volatile void *addr)
126
47
{
127
-
volatile unsigned long *ptr = addr;
128
-
unsigned long mask = 1UL << (nr & 31);
48
+
unsigned int *ptr = (void *)addr;
49
+
unsigned int mask = 1UL << (nr & 31);
129
50
ptr += nr >> 5;
130
-
return (atomic_test_and_XOR_mask(mask, ptr) & mask) != 0;
51
+
return (__atomic32_fetch_xor(mask, ptr) & mask) != 0;
131
52
}
132
53
133
54
static inline void clear_bit(unsigned long nr, volatile void *addr)
+3
-3
arch/frv/kernel/dma.c
+3
-3
arch/frv/kernel/dma.c
···
109
109
110
110
static DEFINE_RWLOCK(frv_dma_channels_lock);
111
111
112
-
unsigned long frv_dma_inprogress;
112
+
unsigned int frv_dma_inprogress;
113
113
114
114
#define frv_clear_dma_inprogress(channel) \
115
-
atomic_clear_mask(1 << (channel), &frv_dma_inprogress);
115
+
(void)__atomic32_fetch_and(~(1 << (channel)), &frv_dma_inprogress);
116
116
117
117
#define frv_set_dma_inprogress(channel) \
118
-
atomic_set_mask(1 << (channel), &frv_dma_inprogress);
118
+
(void)__atomic32_fetch_or(1 << (channel), &frv_dma_inprogress);
119
119
120
120
/*****************************************************************************/
121
121
/*
-5
arch/frv/kernel/frv_ksyms.c
-5
arch/frv/kernel/frv_ksyms.c
···
58
58
EXPORT_SYMBOL(__insl_ns);
59
59
60
60
#ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
61
-
EXPORT_SYMBOL(atomic_test_and_ANDNOT_mask);
62
-
EXPORT_SYMBOL(atomic_test_and_OR_mask);
63
-
EXPORT_SYMBOL(atomic_test_and_XOR_mask);
64
-
EXPORT_SYMBOL(atomic_add_return);
65
-
EXPORT_SYMBOL(atomic_sub_return);
66
61
EXPORT_SYMBOL(__xchg_32);
67
62
EXPORT_SYMBOL(__cmpxchg_32);
68
63
#endif
+1
-1
arch/frv/lib/Makefile
+1
-1
arch/frv/lib/Makefile
+7
arch/frv/lib/atomic-lib.c
+7
arch/frv/lib/atomic-lib.c
-110
arch/frv/lib/atomic-ops.S
-110
arch/frv/lib/atomic-ops.S
···
19
19
20
20
###############################################################################
21
21
#
22
-
# unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v);
23
-
#
24
-
###############################################################################
25
-
.globl atomic_test_and_ANDNOT_mask
26
-
.type atomic_test_and_ANDNOT_mask,@function
27
-
atomic_test_and_ANDNOT_mask:
28
-
not.p gr8,gr10
29
-
0:
30
-
orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
31
-
ckeq icc3,cc7
32
-
ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
33
-
orcr cc7,cc7,cc3 /* set CC3 to true */
34
-
and gr8,gr10,gr11
35
-
cst.p gr11,@(gr9,gr0) ,cc3,#1
36
-
corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
37
-
beq icc3,#0,0b
38
-
bralr
39
-
40
-
.size atomic_test_and_ANDNOT_mask, .-atomic_test_and_ANDNOT_mask
41
-
42
-
###############################################################################
43
-
#
44
-
# unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v);
45
-
#
46
-
###############################################################################
47
-
.globl atomic_test_and_OR_mask
48
-
.type atomic_test_and_OR_mask,@function
49
-
atomic_test_and_OR_mask:
50
-
or.p gr8,gr8,gr10
51
-
0:
52
-
orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
53
-
ckeq icc3,cc7
54
-
ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
55
-
orcr cc7,cc7,cc3 /* set CC3 to true */
56
-
or gr8,gr10,gr11
57
-
cst.p gr11,@(gr9,gr0) ,cc3,#1
58
-
corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
59
-
beq icc3,#0,0b
60
-
bralr
61
-
62
-
.size atomic_test_and_OR_mask, .-atomic_test_and_OR_mask
63
-
64
-
###############################################################################
65
-
#
66
-
# unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v);
67
-
#
68
-
###############################################################################
69
-
.globl atomic_test_and_XOR_mask
70
-
.type atomic_test_and_XOR_mask,@function
71
-
atomic_test_and_XOR_mask:
72
-
or.p gr8,gr8,gr10
73
-
0:
74
-
orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
75
-
ckeq icc3,cc7
76
-
ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
77
-
orcr cc7,cc7,cc3 /* set CC3 to true */
78
-
xor gr8,gr10,gr11
79
-
cst.p gr11,@(gr9,gr0) ,cc3,#1
80
-
corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
81
-
beq icc3,#0,0b
82
-
bralr
83
-
84
-
.size atomic_test_and_XOR_mask, .-atomic_test_and_XOR_mask
85
-
86
-
###############################################################################
87
-
#
88
-
# int atomic_add_return(int i, atomic_t *v)
89
-
#
90
-
###############################################################################
91
-
.globl atomic_add_return
92
-
.type atomic_add_return,@function
93
-
atomic_add_return:
94
-
or.p gr8,gr8,gr10
95
-
0:
96
-
orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
97
-
ckeq icc3,cc7
98
-
ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
99
-
orcr cc7,cc7,cc3 /* set CC3 to true */
100
-
add gr8,gr10,gr8
101
-
cst.p gr8,@(gr9,gr0) ,cc3,#1
102
-
corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
103
-
beq icc3,#0,0b
104
-
bralr
105
-
106
-
.size atomic_add_return, .-atomic_add_return
107
-
108
-
###############################################################################
109
-
#
110
-
# int atomic_sub_return(int i, atomic_t *v)
111
-
#
112
-
###############################################################################
113
-
.globl atomic_sub_return
114
-
.type atomic_sub_return,@function
115
-
atomic_sub_return:
116
-
or.p gr8,gr8,gr10
117
-
0:
118
-
orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
119
-
ckeq icc3,cc7
120
-
ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
121
-
orcr cc7,cc7,cc3 /* set CC3 to true */
122
-
sub gr8,gr10,gr8
123
-
cst.p gr8,@(gr9,gr0) ,cc3,#1
124
-
corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
125
-
beq icc3,#0,0b
126
-
bralr
127
-
128
-
.size atomic_sub_return, .-atomic_sub_return
129
-
130
-
###############################################################################
131
-
#
132
22
# uint32_t __xchg_32(uint32_t i, uint32_t *v)
133
23
#
134
24
###############################################################################
-94
arch/frv/lib/atomic64-ops.S
-94
arch/frv/lib/atomic64-ops.S
···
20
20
21
21
###############################################################################
22
22
#
23
-
# long long atomic64_inc_return(atomic64_t *v)
24
-
#
25
-
###############################################################################
26
-
.globl atomic64_inc_return
27
-
.type atomic64_inc_return,@function
28
-
atomic64_inc_return:
29
-
or.p gr8,gr8,gr10
30
-
0:
31
-
orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
32
-
ckeq icc3,cc7
33
-
ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */
34
-
orcr cc7,cc7,cc3 /* set CC3 to true */
35
-
addicc gr9,#1,gr9,icc0
36
-
addxi gr8,#0,gr8,icc0
37
-
cstd.p gr8,@(gr10,gr0) ,cc3,#1
38
-
corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
39
-
beq icc3,#0,0b
40
-
bralr
41
-
42
-
.size atomic64_inc_return, .-atomic64_inc_return
43
-
44
-
###############################################################################
45
-
#
46
-
# long long atomic64_dec_return(atomic64_t *v)
47
-
#
48
-
###############################################################################
49
-
.globl atomic64_dec_return
50
-
.type atomic64_dec_return,@function
51
-
atomic64_dec_return:
52
-
or.p gr8,gr8,gr10
53
-
0:
54
-
orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
55
-
ckeq icc3,cc7
56
-
ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */
57
-
orcr cc7,cc7,cc3 /* set CC3 to true */
58
-
subicc gr9,#1,gr9,icc0
59
-
subxi gr8,#0,gr8,icc0
60
-
cstd.p gr8,@(gr10,gr0) ,cc3,#1
61
-
corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
62
-
beq icc3,#0,0b
63
-
bralr
64
-
65
-
.size atomic64_dec_return, .-atomic64_dec_return
66
-
67
-
###############################################################################
68
-
#
69
-
# long long atomic64_add_return(long long i, atomic64_t *v)
70
-
#
71
-
###############################################################################
72
-
.globl atomic64_add_return
73
-
.type atomic64_add_return,@function
74
-
atomic64_add_return:
75
-
or.p gr8,gr8,gr4
76
-
or gr9,gr9,gr5
77
-
0:
78
-
orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
79
-
ckeq icc3,cc7
80
-
ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */
81
-
orcr cc7,cc7,cc3 /* set CC3 to true */
82
-
addcc gr9,gr5,gr9,icc0
83
-
addx gr8,gr4,gr8,icc0
84
-
cstd.p gr8,@(gr10,gr0) ,cc3,#1
85
-
corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
86
-
beq icc3,#0,0b
87
-
bralr
88
-
89
-
.size atomic64_add_return, .-atomic64_add_return
90
-
91
-
###############################################################################
92
-
#
93
-
# long long atomic64_sub_return(long long i, atomic64_t *v)
94
-
#
95
-
###############################################################################
96
-
.globl atomic64_sub_return
97
-
.type atomic64_sub_return,@function
98
-
atomic64_sub_return:
99
-
or.p gr8,gr8,gr4
100
-
or gr9,gr9,gr5
101
-
0:
102
-
orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
103
-
ckeq icc3,cc7
104
-
ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */
105
-
orcr cc7,cc7,cc3 /* set CC3 to true */
106
-
subcc gr9,gr5,gr9,icc0
107
-
subx gr8,gr4,gr8,icc0
108
-
cstd.p gr8,@(gr10,gr0) ,cc3,#1
109
-
corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
110
-
beq icc3,#0,0b
111
-
bralr
112
-
113
-
.size atomic64_sub_return, .-atomic64_sub_return
114
-
115
-
###############################################################################
116
-
#
117
23
# uint64_t __xchg_64(uint64_t i, uint64_t *v)
118
24
#
119
25
###############################################################################