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MIPS: Octeon: Set appropriate endianness in L2C registers

Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9629/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

Paul Martin and committed by
Ralf Baechle b0abf36f 11db04c8

+12
+12
arch/mips/cavium-octeon/octeon-platform.c
··· 325 325 /* Use 64-bit addressing. */ 326 326 ehci_ctl.s.ehci_64b_addr_en = 1; 327 327 ehci_ctl.s.l2c_addr_msb = 0; 328 + #ifdef __BIG_ENDIAN 328 329 ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ 329 330 ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ 331 + #else 332 + ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */ 333 + ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */ 334 + ehci_ctl.s.inv_reg_a2 = 1; 335 + #endif 330 336 cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64); 331 337 332 338 octeon2_usb_clocks_stop(); ··· 387 381 388 382 ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0)); 389 383 ohci_ctl.s.l2c_addr_msb = 0; 384 + #ifdef __BIG_ENDIAN 390 385 ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ 391 386 ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ 387 + #else 388 + ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */ 389 + ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */ 390 + ohci_ctl.s.inv_reg_a2 = 1; 391 + #endif 392 392 cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64); 393 393 394 394 octeon2_usb_clocks_stop();