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dt-bindings: pwm: Convert pwm-mtk-disp.txt to mediatek,pwm-disp.yaml format

Convert pwm-mtk-disp.txt to mediatek,pwm-disp.yaml format as suggested
by maintainer.

Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

authored by

Xinlei Lee and committed by
Thierry Reding
b09b179b 4225cd01

+66 -45
+66
Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: MediaTek DISP_PWM Controller Device Tree Bindings 8 + 9 + maintainers: 10 + - Jitao Shi <jitao.shi@mediatek.com> 11 + - Xinlei Lee <xinlei.lee@mediatek.com> 12 + 13 + allOf: 14 + - $ref: pwm.yaml# 15 + 16 + properties: 17 + compatible: 18 + oneOf: 19 + - enum: 20 + - mediatek,mt2701-disp-pwm 21 + - mediatek,mt6595-disp-pwm 22 + - mediatek,mt8173-disp-pwm 23 + - mediatek,mt8183-disp-pwm 24 + - items: 25 + - const: mediatek,mt8167-disp-pwm 26 + - const: mediatek,mt8173-disp-pwm 27 + 28 + reg: 29 + maxItems: 1 30 + 31 + "#pwm-cells": 32 + const: 2 33 + 34 + clocks: 35 + items: 36 + - description: Main Clock 37 + - description: Mm Clock 38 + 39 + clock-names: 40 + items: 41 + - const: main 42 + - const: mm 43 + 44 + required: 45 + - compatible 46 + - reg 47 + - "#pwm-cells" 48 + - clocks 49 + - clock-names 50 + 51 + additionalProperties: false 52 + 53 + examples: 54 + - | 55 + #include <dt-bindings/interrupt-controller/arm-gic.h> 56 + #include <dt-bindings/clock/mt8173-clk.h> 57 + #include <dt-bindings/interrupt-controller/irq.h> 58 + 59 + pwm0: pwm@1401e000 { 60 + compatible = "mediatek,mt8173-disp-pwm"; 61 + reg = <0x1401e000 0x1000>; 62 + #pwm-cells = <2>; 63 + clocks = <&mmsys CLK_MM_DISP_PWM026M>, 64 + <&mmsys CLK_MM_DISP_PWM0MM>; 65 + clock-names = "main", "mm"; 66 + };
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Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
··· 1 - MediaTek display PWM controller 2 - 3 - Required properties: 4 - - compatible: should be "mediatek,<name>-disp-pwm": 5 - - "mediatek,mt2701-disp-pwm": found on mt2701 SoC. 6 - - "mediatek,mt6595-disp-pwm": found on mt6595 SoC. 7 - - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC. 8 - - "mediatek,mt8173-disp-pwm": found on mt8173 SoC. 9 - - "mediatek,mt8183-disp-pwm": found on mt8183 SoC.$ 10 - - reg: physical base address and length of the controller's registers. 11 - - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of 12 - the cell format. 13 - - clocks: phandle and clock specifier of the PWM reference clock. 14 - - clock-names: must contain the following: 15 - - "main": clock used to generate PWM signals. 16 - - "mm": sync signals from the modules of mmsys. 17 - - pinctrl-names: Must contain a "default" entry. 18 - - pinctrl-0: One property must exist for each entry in pinctrl-names. 19 - See pinctrl/pinctrl-bindings.txt for details of the property values. 20 - 21 - Example: 22 - pwm0: pwm@1401e000 { 23 - compatible = "mediatek,mt8173-disp-pwm", 24 - "mediatek,mt6595-disp-pwm"; 25 - reg = <0 0x1401e000 0 0x1000>; 26 - #pwm-cells = <2>; 27 - clocks = <&mmsys CLK_MM_DISP_PWM026M>, 28 - <&mmsys CLK_MM_DISP_PWM0MM>; 29 - clock-names = "main", "mm"; 30 - pinctrl-names = "default"; 31 - pinctrl-0 = <&disp_pwm0_pins>; 32 - }; 33 - 34 - backlight_lcd: backlight_lcd { 35 - compatible = "pwm-backlight"; 36 - pwms = <&pwm0 0 1000000>; 37 - brightness-levels = < 38 - 0 16 32 48 64 80 96 112 39 - 128 144 160 176 192 208 224 240 40 - 255 41 - >; 42 - default-brightness-level = <9>; 43 - power-supply = <&mt6397_vio18_reg>; 44 - enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; 45 - };