tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

mfd: rtsx: Update phy register

Update some phy register name and value for rts5249,
the updated value makes chip more stable on some platform.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

authored by

Micky Ching and committed by
Lee Jones b0385381 e89f2318

+72 -66
+17 -12
drivers/mfd/rts5249.c
··· 132 132 if (err < 0) 133 133 return err; 134 134 135 - err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV, 136 - PHY_REG_REV_RESV | PHY_REG_REV_RXIDLE_LATCHED | 137 - PHY_REG_REV_P1_EN | PHY_REG_REV_RXIDLE_EN | 138 - PHY_REG_REV_RX_PWST | PHY_REG_REV_CLKREQ_DLY_TIMER_1_0 | 139 - PHY_REG_REV_STOP_CLKRD | PHY_REG_REV_STOP_CLKWR); 135 + err = rtsx_pci_write_phy_register(pcr, PHY_REV, 136 + PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED | 137 + PHY_REV_P1_EN | PHY_REV_RXIDLE_EN | 138 + PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST | 139 + PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD | 140 + PHY_REV_STOP_CLKWR); 140 141 if (err < 0) 141 142 return err; 142 143 ··· 148 147 PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN); 149 148 if (err < 0) 150 149 return err; 150 + 151 151 err = rtsx_pci_write_phy_register(pcr, PHY_PCR, 152 152 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 | 153 153 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | 154 - PHY_PCR_RSSI_EN); 154 + PHY_PCR_RSSI_EN | PHY_PCR_RX10K); 155 155 if (err < 0) 156 156 return err; 157 + 157 158 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2, 158 159 PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR | 159 - PHY_RCR2_CDR_CP_10 | PHY_RCR2_CDR_SR_2 | 160 - PHY_RCR2_FREQSEL_12 | PHY_RCR2_CPADJEN | 161 - PHY_RCR2_CDR_SC_8 | PHY_RCR2_CALIB_LATE); 160 + PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 | 161 + PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE); 162 162 if (err < 0) 163 163 return err; 164 + 164 165 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4, 165 166 PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF | 166 167 PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA | ··· 170 167 PHY_FLD4_BER_CHK_EN); 171 168 if (err < 0) 172 169 return err; 173 - err = rtsx_pci_write_phy_register(pcr, PHY_RDR, PHY_RDR_RXDSEL_1_9); 170 + err = rtsx_pci_write_phy_register(pcr, PHY_RDR, 171 + PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD); 174 172 if (err < 0) 175 173 return err; 176 174 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1, 177 - PHY_RCR1_ADP_TIME | PHY_RCR1_VCO_COARSE); 175 + PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE); 178 176 if (err < 0) 179 177 return err; 180 178 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3, ··· 183 179 PHY_FLD3_RXDELINK); 184 180 if (err < 0) 185 181 return err; 182 + 186 183 return rtsx_pci_write_phy_register(pcr, PHY_TUNE, 187 184 PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 | 188 185 PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 | 189 - PHY_TUNE_TUNED12); 186 + PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12); 190 187 } 191 188 192 189 static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
+55 -54
include/linux/mfd/rtsx_pci.h
··· 630 630 631 631 /* Phy register */ 632 632 #define PHY_PCR 0x00 633 + #define PHY_PCR_FORCE_CODE 0xB000 634 + #define PHY_PCR_OOBS_CALI_50 0x0800 635 + #define PHY_PCR_OOBS_VCM_08 0x0200 636 + #define PHY_PCR_OOBS_SEN_90 0x0040 637 + #define PHY_PCR_RSSI_EN 0x0002 638 + #define PHY_PCR_RX10K 0x0001 639 + 633 640 #define PHY_RCR0 0x01 634 641 #define PHY_RCR1 0x02 642 + #define PHY_RCR1_ADP_TIME_4 0x0400 643 + #define PHY_RCR1_VCO_COARSE 0x001F 644 + 635 645 #define PHY_RCR2 0x03 646 + #define PHY_RCR2_EMPHASE_EN 0x8000 647 + #define PHY_RCR2_NADJR 0x4000 648 + #define PHY_RCR2_CDR_SR_2 0x0100 649 + #define PHY_RCR2_FREQSEL_12 0x0040 650 + #define PHY_RCR2_CDR_SC_12P 0x0010 651 + #define PHY_RCR2_CALIB_LATE 0x0002 652 + 636 653 #define PHY_RTCR 0x04 637 654 #define PHY_RDR 0x05 655 + #define PHY_RDR_RXDSEL_1_9 0x4000 656 + #define PHY_SSC_AUTO_PWD 0x0600 638 657 #define PHY_TCR0 0x06 639 658 #define PHY_TCR1 0x07 640 659 #define PHY_TUNE 0x08 660 + #define PHY_TUNE_TUNEREF_1_0 0x4000 661 + #define PHY_TUNE_VBGSEL_1252 0x0C00 662 + #define PHY_TUNE_SDBUS_33 0x0200 663 + #define PHY_TUNE_TUNED18 0x01C0 664 + #define PHY_TUNE_TUNED12 0X0020 665 + #define PHY_TUNE_TUNEA12 0x0004 666 + 641 667 #define PHY_IMR 0x09 642 668 #define PHY_BPCR 0x0A 669 + #define PHY_BPCR_IBRXSEL 0x0400 670 + #define PHY_BPCR_IBTXSEL 0x0100 671 + #define PHY_BPCR_IB_FILTER 0x0080 672 + #define PHY_BPCR_CMIRROR_EN 0x0040 673 + 643 674 #define PHY_BIST 0x0B 644 675 #define PHY_RAW_L 0x0C 645 676 #define PHY_RAW_H 0x0D ··· 685 654 #define PHY_BPNR 0x16 686 655 #define PHY_BRNR2 0x17 687 656 #define PHY_BENR 0x18 688 - #define PHY_REG_REV 0x19 657 + #define PHY_REV 0x19 658 + #define PHY_REV_RESV 0xE000 659 + #define PHY_REV_RXIDLE_LATCHED 0x1000 660 + #define PHY_REV_P1_EN 0x0800 661 + #define PHY_REV_RXIDLE_EN 0x0400 662 + #define PHY_REV_CLKREQ_TX_EN 0x0200 663 + #define PHY_REV_CLKREQ_RX_EN 0x0100 664 + #define PHY_REV_CLKREQ_DT_1_0 0x0040 665 + #define PHY_REV_STOP_CLKRD 0x0020 666 + #define PHY_REV_RX_PWST 0x0008 667 + #define PHY_REV_STOP_CLKWR 0x0004 668 + 689 669 #define PHY_FLD0 0x1A 690 670 #define PHY_FLD1 0x1B 691 671 #define PHY_FLD2 0x1C 692 672 #define PHY_FLD3 0x1D 673 + #define PHY_FLD3_TIMER_4 0x0800 674 + #define PHY_FLD3_TIMER_6 0x0020 675 + #define PHY_FLD3_RXDELINK 0x0004 676 + 693 677 #define PHY_FLD4 0x1E 678 + #define PHY_FLD4_FLDEN_SEL 0x4000 679 + #define PHY_FLD4_REQ_REF 0x2000 680 + #define PHY_FLD4_RXAMP_OFF 0x1000 681 + #define PHY_FLD4_REQ_ADDA 0x0800 682 + #define PHY_FLD4_BER_COUNT 0x00E0 683 + #define PHY_FLD4_BER_TIMER 0x000A 684 + #define PHY_FLD4_BER_CHK_EN 0x0001 685 + 694 686 #define PHY_DUM_REG 0x1F 695 687 696 688 #define LCTLR 0x80 ··· 728 674 #define PCR_SETTING_REG1 0x724 729 675 #define PCR_SETTING_REG2 0x814 730 676 #define PCR_SETTING_REG3 0x747 731 - 732 - /* Phy bits */ 733 - #define PHY_PCR_FORCE_CODE 0xB000 734 - #define PHY_PCR_OOBS_CALI_50 0x0800 735 - #define PHY_PCR_OOBS_VCM_08 0x0200 736 - #define PHY_PCR_OOBS_SEN_90 0x0040 737 - #define PHY_PCR_RSSI_EN 0x0002 738 - 739 - #define PHY_RCR1_ADP_TIME 0x0100 740 - #define PHY_RCR1_VCO_COARSE 0x001F 741 - 742 - #define PHY_RCR2_EMPHASE_EN 0x8000 743 - #define PHY_RCR2_NADJR 0x4000 744 - #define PHY_RCR2_CDR_CP_10 0x0400 745 - #define PHY_RCR2_CDR_SR_2 0x0100 746 - #define PHY_RCR2_FREQSEL_12 0x0040 747 - #define PHY_RCR2_CPADJEN 0x0020 748 - #define PHY_RCR2_CDR_SC_8 0x0008 749 - #define PHY_RCR2_CALIB_LATE 0x0002 750 - 751 - #define PHY_RDR_RXDSEL_1_9 0x4000 752 - 753 - #define PHY_TUNE_TUNEREF_1_0 0x4000 754 - #define PHY_TUNE_VBGSEL_1252 0x0C00 755 - #define PHY_TUNE_SDBUS_33 0x0200 756 - #define PHY_TUNE_TUNED18 0x01C0 757 - #define PHY_TUNE_TUNED12 0X0020 758 - 759 - #define PHY_BPCR_IBRXSEL 0x0400 760 - #define PHY_BPCR_IBTXSEL 0x0100 761 - #define PHY_BPCR_IB_FILTER 0x0080 762 - #define PHY_BPCR_CMIRROR_EN 0x0040 763 - 764 - #define PHY_REG_REV_RESV 0xE000 765 - #define PHY_REG_REV_RXIDLE_LATCHED 0x1000 766 - #define PHY_REG_REV_P1_EN 0x0800 767 - #define PHY_REG_REV_RXIDLE_EN 0x0400 768 - #define PHY_REG_REV_CLKREQ_DLY_TIMER_1_0 0x0040 769 - #define PHY_REG_REV_STOP_CLKRD 0x0020 770 - #define PHY_REG_REV_RX_PWST 0x0008 771 - #define PHY_REG_REV_STOP_CLKWR 0x0004 772 - 773 - #define PHY_FLD3_TIMER_4 0x7800 774 - #define PHY_FLD3_TIMER_6 0x00E0 775 - #define PHY_FLD3_RXDELINK 0x0004 776 - 777 - #define PHY_FLD4_FLDEN_SEL 0x4000 778 - #define PHY_FLD4_REQ_REF 0x2000 779 - #define PHY_FLD4_RXAMP_OFF 0x1000 780 - #define PHY_FLD4_REQ_ADDA 0x0800 781 - #define PHY_FLD4_BER_COUNT 0x00E0 782 - #define PHY_FLD4_BER_TIMER 0x000A 783 - #define PHY_FLD4_BER_CHK_EN 0x0001 784 677 785 678 #define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0) 786 679