tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6

Conflicts:

arch/arm/mach-pxa/generic.c
arch/arm/mach-pxa/pxa25x.c
arch/arm/mach-pxa/pxa27x.c
arch/arm/mach-pxa/pxa2xx.c
arch/arm/mach-pxa/pxa3xx.c
arch/arm/mach-pxa/reset.c
arch/arm/mach-pxa/spitz.c
arch/arm/mach-pxa/tosa.c
drivers/watchdog/sa1100_wdt.c

authored by

Russell King and committed by
Russell King afd2fc02 1f4de5a0

+94 -9
+10
arch/arm/mach-pxa/generic.c
··· 26 26 #include <asm/mach/map.h> 27 27 28 28 #include <mach/pxa-regs.h> 29 + #include <mach/reset.h> 29 30 30 31 #include "generic.h" 32 + 33 + void clear_reset_status(unsigned int mask) 34 + { 35 + if (cpu_is_pxa2xx()) 36 + pxa2xx_clear_reset_status(mask); 37 + 38 + if (cpu_is_pxa3xx()) 39 + pxa3xx_clear_reset_status(mask); 40 + } 31 41 32 42 /* 33 43 * Get the clock frequency as reflected by CCCR and the turbo flag.
+8
arch/arm/mach-pxa/generic.h
··· 47 47 #define pxa27x_get_memclk_frequency_10khz() (0) 48 48 #endif 49 49 50 + #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) 51 + extern void pxa2xx_clear_reset_status(unsigned int); 52 + #else 53 + static inline void pxa2xx_clear_reset_status(unsigned int mask) {} 54 + #endif 55 + 50 56 #ifdef CONFIG_PXA3xx 51 57 extern unsigned pxa3xx_get_clk_frequency_khz(int); 52 58 extern unsigned pxa3xx_get_memclk_frequency_10khz(void); 59 + extern void pxa3xx_clear_reset_status(unsigned int); 53 60 #else 54 61 #define pxa3xx_get_clk_frequency_khz(x) (0) 55 62 #define pxa3xx_get_memclk_frequency_10khz() (0) 63 + static inline void pxa3xx_clear_reset_status(unsigned int mask) {} 56 64 #endif 57 65 58 66 extern struct sysdev_class pxa_irq_sysclass;
-5
arch/arm/mach-pxa/include/mach/hardware.h
··· 224 224 */ 225 225 extern unsigned int get_memclk_frequency_10khz(void); 226 226 227 - /* 228 - * register GPIO as reset generator 229 - */ 230 - extern int init_gpio_reset(int gpio); 231 - 232 227 #endif 233 228 234 229 #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
+18
arch/arm/mach-pxa/include/mach/reset.h
··· 1 + #ifndef __ASM_ARCH_RESET_H 2 + #define __ASM_ARCH_RESET_H 3 + 4 + #define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */ 5 + #define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */ 6 + #define RESET_STATUS_LOWPOWER (1 << 2) /* Low Power/Sleep Exit */ 7 + #define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */ 8 + #define RESET_STATUS_ALL (0xf) 9 + 10 + extern unsigned int reset_status; 11 + extern void clear_reset_status(unsigned int mask); 12 + 13 + /* 14 + * register GPIO as reset generator 15 + */ 16 + extern int init_gpio_reset(int gpio); 17 + 18 + #endif /* __ASM_ARCH_RESET_H */
+4
arch/arm/mach-pxa/pxa25x.c
··· 28 28 #include <mach/pxa-regs.h> 29 29 #include <mach/pxa2xx-regs.h> 30 30 #include <mach/mfp-pxa25x.h> 31 + #include <mach/reset.h> 31 32 #include <mach/pm.h> 32 33 #include <mach/dma.h> 33 34 ··· 349 348 clks_register(&pxa25x_hwuart_clk, 1); 350 349 351 350 if (cpu_is_pxa21x() || cpu_is_pxa25x()) { 351 + 352 + reset_status = RCSR; 353 + 352 354 clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); 353 355 354 356 if ((ret = pxa_init_dma(16)))
+4
arch/arm/mach-pxa/pxa27x.c
··· 24 24 #include <mach/pxa-regs.h> 25 25 #include <mach/pxa2xx-regs.h> 26 26 #include <mach/mfp-pxa27x.h> 27 + #include <mach/reset.h> 27 28 #include <mach/ohci.h> 28 29 #include <mach/pm.h> 29 30 #include <mach/dma.h> ··· 385 384 int i, ret = 0; 386 385 387 386 if (cpu_is_pxa27x()) { 387 + 388 + reset_status = RCSR; 389 + 388 390 clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); 389 391 390 392 if ((ret = pxa_init_dma(32)))
+9
arch/arm/mach-pxa/pxa2xx.c
··· 14 14 #include <linux/kernel.h> 15 15 #include <linux/device.h> 16 16 17 + #include <mach/hardware.h> 18 + #include <mach/pxa2xx-regs.h> 17 19 #include <mach/mfp-pxa2xx.h> 18 20 #include <mach/mfp-pxa25x.h> 21 + #include <mach/reset.h> 19 22 #include <mach/irda.h> 23 + 24 + void pxa2xx_clear_reset_status(unsigned int mask) 25 + { 26 + /* RESET_STATUS_* has a 1:1 mapping with RCSR */ 27 + RCSR = mask; 28 + } 20 29 21 30 static unsigned long pxa2xx_mfp_fir[] = { 22 31 GPIO46_FICP_RXD,
+10
arch/arm/mach-pxa/pxa3xx.c
··· 24 24 25 25 #include <mach/hardware.h> 26 26 #include <mach/pxa3xx-regs.h> 27 + #include <mach/reset.h> 27 28 #include <mach/ohci.h> 28 29 #include <mach/pm.h> 29 30 #include <mach/dma.h> ··· 108 107 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; 109 108 110 109 return (clk / 10000); 110 + } 111 + 112 + void pxa3xx_clear_reset_status(unsigned int mask) 113 + { 114 + /* RESET_STATUS_* has a 1:1 mapping with ARSR */ 115 + ARSR = mask; 111 116 } 112 117 113 118 /* ··· 539 532 int i, ret = 0; 540 533 541 534 if (cpu_is_pxa3xx()) { 535 + 536 + reset_status = ARSR; 537 + 542 538 /* 543 539 * clear RDH bit every time after reset 544 540 *
+5 -3
arch/arm/mach-pxa/reset.c
··· 11 11 #include <asm/proc-fns.h> 12 12 13 13 #include <mach/pxa-regs.h> 14 - #include <mach/pxa2xx-regs.h> 14 + #include <mach/reset.h> 15 + 16 + unsigned int reset_status; 17 + EXPORT_SYMBOL(reset_status); 15 18 16 19 static void do_hw_reset(void); 17 20 ··· 80 77 81 78 void arch_reset(char mode) 82 79 { 83 - if (cpu_is_pxa2xx()) 84 - RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; 80 + clear_reset_status(RESET_STATUS_ALL); 85 81 86 82 switch (mode) { 87 83 case 's':
+1
arch/arm/mach-pxa/spitz.c
··· 39 39 #include <mach/pxa2xx-regs.h> 40 40 #include <mach/pxa2xx-gpio.h> 41 41 #include <mach/pxa27x-udc.h> 42 + #include <mach/reset.h> 42 43 #include <mach/irda.h> 43 44 #include <mach/mmc.h> 44 45 #include <mach/ohci.h>
+1
arch/arm/mach-pxa/tosa.c
··· 36 36 #include <asm/mach-types.h> 37 37 #include <mach/pxa2xx-regs.h> 38 38 #include <mach/mfp-pxa25x.h> 39 + #include <mach/reset.h> 39 40 #include <mach/irda.h> 40 41 #include <mach/i2c.h> 41 42 #include <mach/mmc.h>
+3
arch/arm/mach-sa1100/generic.c
··· 31 31 32 32 #include "generic.h" 33 33 34 + unsigned int reset_status; 35 + EXPORT_SYMBOL(reset_status); 36 + 34 37 #define NR_FREQS 16 35 38 36 39 /*
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arch/arm/mach-sa1100/include/mach/reset.h
··· 1 + #ifndef __ASM_ARCH_RESET_H 2 + #define __ASM_ARCH_RESET_H 3 + 4 + #include "hardware.h" 5 + 6 + #define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */ 7 + #define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */ 8 + #define RESET_STATUS_LOWPOWER (1 << 2) /* Exit from Low Power/Sleep */ 9 + #define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */ 10 + #define RESET_STATUS_ALL (0xf) 11 + 12 + extern unsigned int reset_status; 13 + static inline void clear_reset_status(unsigned int mask) 14 + { 15 + RCSR = mask; 16 + } 17 + 18 + #endif /* __ASM_ARCH_RESET_H */
+3 -1
drivers/watchdog/sa1100_wdt.c
··· 31 31 #include <mach/pxa-regs.h> 32 32 #endif 33 33 34 + #include <mach/reset.h> 34 35 #include <mach/hardware.h> 35 36 #include <asm/uaccess.h> 36 37 ··· 163 162 * we suspend, RCSR will be cleared, and the watchdog 164 163 * reset reason will be lost. 165 164 */ 166 - boot_status = (RCSR & RCSR_WDR) ? WDIOF_CARDRESET : 0; 165 + boot_status = (reset_status & RESET_STATUS_WATCHDOG) ? 166 + WDIOF_CARDRESET : 0; 167 167 pre_margin = OSCR_FREQ * margin; 168 168 169 169 ret = misc_register(&sa1100dog_miscdev);