media: imx290: Convert to new CCI register access helpers

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Use the new comon CCI register access helpers to replace the private
register access helpers in the imx290 driver.

[Sakari Ailus: Squashed the patch to address a merge issue in Kconfig]

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>

authored by

Hans de Goede and committed by

Mauro Carvalho Chehab 2 years ago af73323b f3a5e2cc

+150 -211

2 changed files

expand all

drivers

media

i2c

Kconfig

imx290.c

drivers/media/i2c/Kconfig

··· 125 125 config VIDEO_IMX290 126 126 tristate "Sony IMX290 sensor support" 127 127 select REGMAP_I2C 128 + select V4L2_CCI_I2C 128 129 help 129 130 This is a Video4Linux2 sensor driver for the Sony 130 131 IMX290 camera sensor.

+149 -211

drivers/media/i2c/imx290.c

··· 21 21 #include <asm/unaligned.h> 22 22 23 23 #include <media/media-entity.h> 24 + #include <media/v4l2-cci.h> 24 25 #include <media/v4l2-ctrls.h> 25 26 #include <media/v4l2-device.h> 26 27 #include <media/v4l2-event.h> 27 28 #include <media/v4l2-fwnode.h> 28 29 #include <media/v4l2-subdev.h> 29 30 30 - #define IMX290_REG_SIZE_SHIFT 16 31 - #define IMX290_REG_ADDR_MASK 0xffff 32 - #define IMX290_REG_8BIT(n) ((1U << IMX290_REG_SIZE_SHIFT) | (n)) 33 - #define IMX290_REG_16BIT(n) ((2U << IMX290_REG_SIZE_SHIFT) | (n)) 34 - #define IMX290_REG_24BIT(n) ((3U << IMX290_REG_SIZE_SHIFT) | (n)) 35 - 36 - #define IMX290_STANDBY IMX290_REG_8BIT(0x3000) 37 - #define IMX290_REGHOLD IMX290_REG_8BIT(0x3001) 38 - #define IMX290_XMSTA IMX290_REG_8BIT(0x3002) 39 - #define IMX290_ADBIT IMX290_REG_8BIT(0x3005) 31 + #define IMX290_STANDBY CCI_REG8(0x3000) 32 + #define IMX290_REGHOLD CCI_REG8(0x3001) 33 + #define IMX290_XMSTA CCI_REG8(0x3002) 34 + #define IMX290_ADBIT CCI_REG8(0x3005) 40 35 #define IMX290_ADBIT_10BIT (0 << 0) 41 36 #define IMX290_ADBIT_12BIT (1 << 0) 42 - #define IMX290_CTRL_07 IMX290_REG_8BIT(0x3007) 37 + #define IMX290_CTRL_07 CCI_REG8(0x3007) 43 38 #define IMX290_VREVERSE BIT(0) 44 39 #define IMX290_HREVERSE BIT(1) 45 40 #define IMX290_WINMODE_1080P (0 << 4) 46 41 #define IMX290_WINMODE_720P (1 << 4) 47 42 #define IMX290_WINMODE_CROP (4 << 4) 48 - #define IMX290_FR_FDG_SEL IMX290_REG_8BIT(0x3009) 49 - #define IMX290_BLKLEVEL IMX290_REG_16BIT(0x300a) 50 - #define IMX290_GAIN IMX290_REG_8BIT(0x3014) 51 - #define IMX290_VMAX IMX290_REG_24BIT(0x3018) 43 + #define IMX290_FR_FDG_SEL CCI_REG8(0x3009) 44 + #define IMX290_BLKLEVEL CCI_REG16(0x300a) 45 + #define IMX290_GAIN CCI_REG8(0x3014) 46 + #define IMX290_VMAX CCI_REG24(0x3018) 52 47 #define IMX290_VMAX_MAX 0x3ffff 53 - #define IMX290_HMAX IMX290_REG_16BIT(0x301c) 48 + #define IMX290_HMAX CCI_REG16(0x301c) 54 49 #define IMX290_HMAX_MAX 0xffff 55 - #define IMX290_SHS1 IMX290_REG_24BIT(0x3020) 56 - #define IMX290_WINWV_OB IMX290_REG_8BIT(0x303a) 57 - #define IMX290_WINPV IMX290_REG_16BIT(0x303c) 58 - #define IMX290_WINWV IMX290_REG_16BIT(0x303e) 59 - #define IMX290_WINPH IMX290_REG_16BIT(0x3040) 60 - #define IMX290_WINWH IMX290_REG_16BIT(0x3042) 61 - #define IMX290_OUT_CTRL IMX290_REG_8BIT(0x3046) 50 + #define IMX290_SHS1 CCI_REG24(0x3020) 51 + #define IMX290_WINWV_OB CCI_REG8(0x303a) 52 + #define IMX290_WINPV CCI_REG16(0x303c) 53 + #define IMX290_WINWV CCI_REG16(0x303e) 54 + #define IMX290_WINPH CCI_REG16(0x3040) 55 + #define IMX290_WINWH CCI_REG16(0x3042) 56 + #define IMX290_OUT_CTRL CCI_REG8(0x3046) 62 57 #define IMX290_ODBIT_10BIT (0 << 0) 63 58 #define IMX290_ODBIT_12BIT (1 << 0) 64 59 #define IMX290_OPORTSEL_PARALLEL (0x0 << 4) 65 60 #define IMX290_OPORTSEL_LVDS_2CH (0xd << 4) 66 61 #define IMX290_OPORTSEL_LVDS_4CH (0xe << 4) 67 62 #define IMX290_OPORTSEL_LVDS_8CH (0xf << 4) 68 - #define IMX290_XSOUTSEL IMX290_REG_8BIT(0x304b) 63 + #define IMX290_XSOUTSEL CCI_REG8(0x304b) 69 64 #define IMX290_XSOUTSEL_XVSOUTSEL_HIGH (0 << 0) 70 65 #define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC (2 << 0) 71 66 #define IMX290_XSOUTSEL_XHSOUTSEL_HIGH (0 << 2) 72 67 #define IMX290_XSOUTSEL_XHSOUTSEL_HSYNC (2 << 2) 73 - #define IMX290_INCKSEL1 IMX290_REG_8BIT(0x305c) 74 - #define IMX290_INCKSEL2 IMX290_REG_8BIT(0x305d) 75 - #define IMX290_INCKSEL3 IMX290_REG_8BIT(0x305e) 76 - #define IMX290_INCKSEL4 IMX290_REG_8BIT(0x305f) 77 - #define IMX290_PGCTRL IMX290_REG_8BIT(0x308c) 78 - #define IMX290_ADBIT1 IMX290_REG_8BIT(0x3129) 68 + #define IMX290_INCKSEL1 CCI_REG8(0x305c) 69 + #define IMX290_INCKSEL2 CCI_REG8(0x305d) 70 + #define IMX290_INCKSEL3 CCI_REG8(0x305e) 71 + #define IMX290_INCKSEL4 CCI_REG8(0x305f) 72 + #define IMX290_PGCTRL CCI_REG8(0x308c) 73 + #define IMX290_ADBIT1 CCI_REG8(0x3129) 79 74 #define IMX290_ADBIT1_10BIT 0x1d 80 75 #define IMX290_ADBIT1_12BIT 0x00 81 - #define IMX290_INCKSEL5 IMX290_REG_8BIT(0x315e) 82 - #define IMX290_INCKSEL6 IMX290_REG_8BIT(0x3164) 83 - #define IMX290_ADBIT2 IMX290_REG_8BIT(0x317c) 76 + #define IMX290_INCKSEL5 CCI_REG8(0x315e) 77 + #define IMX290_INCKSEL6 CCI_REG8(0x3164) 78 + #define IMX290_ADBIT2 CCI_REG8(0x317c) 84 79 #define IMX290_ADBIT2_10BIT 0x12 85 80 #define IMX290_ADBIT2_12BIT 0x00 86 - #define IMX290_CHIP_ID IMX290_REG_16BIT(0x319a) 87 - #define IMX290_ADBIT3 IMX290_REG_8BIT(0x31ec) 81 + #define IMX290_CHIP_ID CCI_REG16(0x319a) 82 + #define IMX290_ADBIT3 CCI_REG8(0x31ec) 88 83 #define IMX290_ADBIT3_10BIT 0x37 89 84 #define IMX290_ADBIT3_12BIT 0x0e 90 - #define IMX290_REPETITION IMX290_REG_8BIT(0x3405) 91 - #define IMX290_PHY_LANE_NUM IMX290_REG_8BIT(0x3407) 92 - #define IMX290_OPB_SIZE_V IMX290_REG_8BIT(0x3414) 93 - #define IMX290_Y_OUT_SIZE IMX290_REG_16BIT(0x3418) 94 - #define IMX290_CSI_DT_FMT IMX290_REG_16BIT(0x3441) 85 + #define IMX290_REPETITION CCI_REG8(0x3405) 86 + #define IMX290_PHY_LANE_NUM CCI_REG8(0x3407) 87 + #define IMX290_OPB_SIZE_V CCI_REG8(0x3414) 88 + #define IMX290_Y_OUT_SIZE CCI_REG16(0x3418) 89 + #define IMX290_CSI_DT_FMT CCI_REG16(0x3441) 95 90 #define IMX290_CSI_DT_FMT_RAW10 0x0a0a 96 91 #define IMX290_CSI_DT_FMT_RAW12 0x0c0c 97 - #define IMX290_CSI_LANE_MODE IMX290_REG_8BIT(0x3443) 98 - #define IMX290_EXTCK_FREQ IMX290_REG_16BIT(0x3444) 99 - #define IMX290_TCLKPOST IMX290_REG_16BIT(0x3446) 100 - #define IMX290_THSZERO IMX290_REG_16BIT(0x3448) 101 - #define IMX290_THSPREPARE IMX290_REG_16BIT(0x344a) 102 - #define IMX290_TCLKTRAIL IMX290_REG_16BIT(0x344c) 103 - #define IMX290_THSTRAIL IMX290_REG_16BIT(0x344e) 104 - #define IMX290_TCLKZERO IMX290_REG_16BIT(0x3450) 105 - #define IMX290_TCLKPREPARE IMX290_REG_16BIT(0x3452) 106 - #define IMX290_TLPX IMX290_REG_16BIT(0x3454) 107 - #define IMX290_X_OUT_SIZE IMX290_REG_16BIT(0x3472) 108 - #define IMX290_INCKSEL7 IMX290_REG_8BIT(0x3480) 92 + #define IMX290_CSI_LANE_MODE CCI_REG8(0x3443) 93 + #define IMX290_EXTCK_FREQ CCI_REG16(0x3444) 94 + #define IMX290_TCLKPOST CCI_REG16(0x3446) 95 + #define IMX290_THSZERO CCI_REG16(0x3448) 96 + #define IMX290_THSPREPARE CCI_REG16(0x344a) 97 + #define IMX290_TCLKTRAIL CCI_REG16(0x344c) 98 + #define IMX290_THSTRAIL CCI_REG16(0x344e) 99 + #define IMX290_TCLKZERO CCI_REG16(0x3450) 100 + #define IMX290_TCLKPREPARE CCI_REG16(0x3452) 101 + #define IMX290_TLPX CCI_REG16(0x3454) 102 + #define IMX290_X_OUT_SIZE CCI_REG16(0x3472) 103 + #define IMX290_INCKSEL7 CCI_REG8(0x3480) 109 104 110 105 #define IMX290_PGCTRL_REGEN BIT(0) 111 106 #define IMX290_PGCTRL_THRU BIT(1) ··· 176 181 177 182 struct imx290_model_info { 178 183 enum imx290_colour_variant colour_variant; 179 - const struct imx290_regval *init_regs; 184 + const struct cci_reg_sequence *init_regs; 180 185 size_t init_regs_num; 181 186 const char *name; 182 187 }; ··· 185 190 IMX290_CLK_37_125, 186 191 IMX290_CLK_74_25, 187 192 IMX290_NUM_CLK 188 - }; 189 - 190 - struct imx290_regval { 191 - u32 reg; 192 - u32 val; 193 193 }; 194 194 195 195 /* ··· 207 217 u8 link_freq_index; 208 218 u8 ctrl_07; 209 219 210 - const struct imx290_regval *data; 220 + const struct cci_reg_sequence *data; 211 221 u32 data_size; 212 222 213 223 const struct imx290_clk_cfg *clk_cfg; ··· 261 271 * Modes and formats 262 272 */ 263 273 264 - static const struct imx290_regval imx290_global_init_settings[] = { 274 + static const struct cci_reg_sequence imx290_global_init_settings[] = { 265 275 { IMX290_WINWV_OB, 12 }, 266 276 { IMX290_WINPH, 0 }, 267 277 { IMX290_WINPV, 0 }, ··· 269 279 { IMX290_WINWV, 1097 }, 270 280 { IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC | 271 281 IMX290_XSOUTSEL_XHSOUTSEL_HSYNC }, 272 - { IMX290_REG_8BIT(0x3011), 0x02 }, 273 - { IMX290_REG_8BIT(0x3012), 0x64 }, 274 - { IMX290_REG_8BIT(0x3013), 0x00 }, 282 + { CCI_REG8(0x3011), 0x02 }, 283 + { CCI_REG8(0x3012), 0x64 }, 284 + { CCI_REG8(0x3013), 0x00 }, 275 285 }; 276 286 277 - static const struct imx290_regval imx290_global_init_settings_290[] = { 278 - { IMX290_REG_8BIT(0x300f), 0x00 }, 279 - { IMX290_REG_8BIT(0x3010), 0x21 }, 280 - { IMX290_REG_8BIT(0x3016), 0x09 }, 281 - { IMX290_REG_8BIT(0x3070), 0x02 }, 282 - { IMX290_REG_8BIT(0x3071), 0x11 }, 283 - { IMX290_REG_8BIT(0x309b), 0x10 }, 284 - { IMX290_REG_8BIT(0x309c), 0x22 }, 285 - { IMX290_REG_8BIT(0x30a2), 0x02 }, 286 - { IMX290_REG_8BIT(0x30a6), 0x20 }, 287 - { IMX290_REG_8BIT(0x30a8), 0x20 }, 288 - { IMX290_REG_8BIT(0x30aa), 0x20 }, 289 - { IMX290_REG_8BIT(0x30ac), 0x20 }, 290 - { IMX290_REG_8BIT(0x30b0), 0x43 }, 291 - { IMX290_REG_8BIT(0x3119), 0x9e }, 292 - { IMX290_REG_8BIT(0x311c), 0x1e }, 293 - { IMX290_REG_8BIT(0x311e), 0x08 }, 294 - { IMX290_REG_8BIT(0x3128), 0x05 }, 295 - { IMX290_REG_8BIT(0x313d), 0x83 }, 296 - { IMX290_REG_8BIT(0x3150), 0x03 }, 297 - { IMX290_REG_8BIT(0x317e), 0x00 }, 298 - { IMX290_REG_8BIT(0x32b8), 0x50 }, 299 - { IMX290_REG_8BIT(0x32b9), 0x10 }, 300 - { IMX290_REG_8BIT(0x32ba), 0x00 }, 301 - { IMX290_REG_8BIT(0x32bb), 0x04 }, 302 - { IMX290_REG_8BIT(0x32c8), 0x50 }, 303 - { IMX290_REG_8BIT(0x32c9), 0x10 }, 304 - { IMX290_REG_8BIT(0x32ca), 0x00 }, 305 - { IMX290_REG_8BIT(0x32cb), 0x04 }, 306 - { IMX290_REG_8BIT(0x332c), 0xd3 }, 307 - { IMX290_REG_8BIT(0x332d), 0x10 }, 308 - { IMX290_REG_8BIT(0x332e), 0x0d }, 309 - { IMX290_REG_8BIT(0x3358), 0x06 }, 310 - { IMX290_REG_8BIT(0x3359), 0xe1 }, 311 - { IMX290_REG_8BIT(0x335a), 0x11 }, 312 - { IMX290_REG_8BIT(0x3360), 0x1e }, 313 - { IMX290_REG_8BIT(0x3361), 0x61 }, 314 - { IMX290_REG_8BIT(0x3362), 0x10 }, 315 - { IMX290_REG_8BIT(0x33b0), 0x50 }, 316 - { IMX290_REG_8BIT(0x33b2), 0x1a }, 317 - { IMX290_REG_8BIT(0x33b3), 0x04 }, 287 + static const struct cci_reg_sequence imx290_global_init_settings_290[] = { 288 + { CCI_REG8(0x300f), 0x00 }, 289 + { CCI_REG8(0x3010), 0x21 }, 290 + { CCI_REG8(0x3016), 0x09 }, 291 + { CCI_REG8(0x3070), 0x02 }, 292 + { CCI_REG8(0x3071), 0x11 }, 293 + { CCI_REG8(0x309b), 0x10 }, 294 + { CCI_REG8(0x309c), 0x22 }, 295 + { CCI_REG8(0x30a2), 0x02 }, 296 + { CCI_REG8(0x30a6), 0x20 }, 297 + { CCI_REG8(0x30a8), 0x20 }, 298 + { CCI_REG8(0x30aa), 0x20 }, 299 + { CCI_REG8(0x30ac), 0x20 }, 300 + { CCI_REG8(0x30b0), 0x43 }, 301 + { CCI_REG8(0x3119), 0x9e }, 302 + { CCI_REG8(0x311c), 0x1e }, 303 + { CCI_REG8(0x311e), 0x08 }, 304 + { CCI_REG8(0x3128), 0x05 }, 305 + { CCI_REG8(0x313d), 0x83 }, 306 + { CCI_REG8(0x3150), 0x03 }, 307 + { CCI_REG8(0x317e), 0x00 }, 308 + { CCI_REG8(0x32b8), 0x50 }, 309 + { CCI_REG8(0x32b9), 0x10 }, 310 + { CCI_REG8(0x32ba), 0x00 }, 311 + { CCI_REG8(0x32bb), 0x04 }, 312 + { CCI_REG8(0x32c8), 0x50 }, 313 + { CCI_REG8(0x32c9), 0x10 }, 314 + { CCI_REG8(0x32ca), 0x00 }, 315 + { CCI_REG8(0x32cb), 0x04 }, 316 + { CCI_REG8(0x332c), 0xd3 }, 317 + { CCI_REG8(0x332d), 0x10 }, 318 + { CCI_REG8(0x332e), 0x0d }, 319 + { CCI_REG8(0x3358), 0x06 }, 320 + { CCI_REG8(0x3359), 0xe1 }, 321 + { CCI_REG8(0x335a), 0x11 }, 322 + { CCI_REG8(0x3360), 0x1e }, 323 + { CCI_REG8(0x3361), 0x61 }, 324 + { CCI_REG8(0x3362), 0x10 }, 325 + { CCI_REG8(0x33b0), 0x50 }, 326 + { CCI_REG8(0x33b2), 0x1a }, 327 + { CCI_REG8(0x33b3), 0x04 }, 318 328 }; 319 329 320 330 #define IMX290_NUM_CLK_REGS 2 321 - static const struct imx290_regval xclk_regs[][IMX290_NUM_CLK_REGS] = { 331 + static const struct cci_reg_sequence xclk_regs[][IMX290_NUM_CLK_REGS] = { 322 332 [IMX290_CLK_37_125] = { 323 333 { IMX290_EXTCK_FREQ, (37125 * 256) / 1000 }, 324 334 { IMX290_INCKSEL7, 0x49 }, ··· 329 339 }, 330 340 }; 331 341 332 - static const struct imx290_regval imx290_global_init_settings_327[] = { 333 - { IMX290_REG_8BIT(0x309e), 0x4A }, 334 - { IMX290_REG_8BIT(0x309f), 0x4A }, 335 - { IMX290_REG_8BIT(0x313b), 0x61 }, 342 + static const struct cci_reg_sequence imx290_global_init_settings_327[] = { 343 + { CCI_REG8(0x309e), 0x4A }, 344 + { CCI_REG8(0x309f), 0x4A }, 345 + { CCI_REG8(0x313b), 0x61 }, 336 346 }; 337 347 338 - static const struct imx290_regval imx290_1080p_settings[] = { 348 + static const struct cci_reg_sequence imx290_1080p_settings[] = { 339 349 /* mode settings */ 340 350 { IMX290_WINWV_OB, 12 }, 341 351 { IMX290_OPB_SIZE_V, 10 }, ··· 343 353 { IMX290_Y_OUT_SIZE, 1080 }, 344 354 }; 345 355 346 - static const struct imx290_regval imx290_720p_settings[] = { 356 + static const struct cci_reg_sequence imx290_720p_settings[] = { 347 357 /* mode settings */ 348 358 { IMX290_WINWV_OB, 6 }, 349 359 { IMX290_OPB_SIZE_V, 4 }, ··· 351 361 { IMX290_Y_OUT_SIZE, 720 }, 352 362 }; 353 363 354 - static const struct imx290_regval imx290_10bit_settings[] = { 364 + static const struct cci_reg_sequence imx290_10bit_settings[] = { 355 365 { IMX290_ADBIT, IMX290_ADBIT_10BIT }, 356 366 { IMX290_OUT_CTRL, IMX290_ODBIT_10BIT }, 357 367 { IMX290_ADBIT1, IMX290_ADBIT1_10BIT }, ··· 360 370 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW10 }, 361 371 }; 362 372 363 - static const struct imx290_regval imx290_12bit_settings[] = { 373 + static const struct cci_reg_sequence imx290_12bit_settings[] = { 364 374 { IMX290_ADBIT, IMX290_ADBIT_12BIT }, 365 375 { IMX290_OUT_CTRL, IMX290_ODBIT_12BIT }, 366 376 { IMX290_ADBIT1, IMX290_ADBIT1_12BIT }, ··· 566 576 struct imx290_format_info { 567 577 u32 code[IMX290_VARIANT_MAX]; 568 578 u8 bpp; 569 - const struct imx290_regval *regs; 579 + const struct cci_reg_sequence *regs; 570 580 unsigned int num_regs; 571 581 }; 572 582 ··· 605 615 return NULL; 606 616 } 607 617 608 - /* ----------------------------------------------------------------------------- 609 - * Register access 610 - */ 611 - 612 - static int __always_unused imx290_read(struct imx290 *imx290, u32 addr, u32 *value) 613 - { 614 - u8 data[3] = { 0, 0, 0 }; 615 - int ret; 616 - 617 - ret = regmap_raw_read(imx290->regmap, addr & IMX290_REG_ADDR_MASK, 618 - data, (addr >> IMX290_REG_SIZE_SHIFT) & 3); 619 - if (ret < 0) { 620 - dev_err(imx290->dev, "%u-bit read from 0x%04x failed: %d\n", 621 - ((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8, 622 - addr & IMX290_REG_ADDR_MASK, ret); 623 - return ret; 624 - } 625 - 626 - *value = get_unaligned_le24(data); 627 - return 0; 628 - } 629 - 630 - static int imx290_write(struct imx290 *imx290, u32 addr, u32 value, int *err) 631 - { 632 - u8 data[3]; 633 - int ret; 634 - 635 - if (err && *err) 636 - return *err; 637 - 638 - put_unaligned_le24(value, data); 639 - 640 - ret = regmap_raw_write(imx290->regmap, addr & IMX290_REG_ADDR_MASK, 641 - data, (addr >> IMX290_REG_SIZE_SHIFT) & 3); 642 - if (ret < 0) { 643 - dev_err(imx290->dev, "%u-bit write to 0x%04x failed: %d\n", 644 - ((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8, 645 - addr & IMX290_REG_ADDR_MASK, ret); 646 - if (err) 647 - *err = ret; 648 - } 649 - 650 - return ret; 651 - } 652 - 653 618 static int imx290_set_register_array(struct imx290 *imx290, 654 - const struct imx290_regval *settings, 619 + const struct cci_reg_sequence *settings, 655 620 unsigned int num_settings) 656 621 { 657 - unsigned int i; 658 622 int ret; 659 623 660 - for (i = 0; i < num_settings; ++i, ++settings) { 661 - ret = imx290_write(imx290, settings->reg, settings->val, NULL); 662 - if (ret < 0) 663 - return ret; 664 - } 624 + ret = cci_multi_reg_write(imx290->regmap, settings, num_settings, NULL); 625 + if (ret < 0) 626 + return ret; 665 627 666 628 /* Provide 10ms settle time */ 667 629 usleep_range(10000, 11000); ··· 631 689 ret = imx290_set_register_array(imx290, xclk_regs[clk_idx], 632 690 IMX290_NUM_CLK_REGS); 633 691 634 - imx290_write(imx290, IMX290_INCKSEL1, clk_cfg->incksel1, &ret); 635 - imx290_write(imx290, IMX290_INCKSEL2, clk_cfg->incksel2, &ret); 636 - imx290_write(imx290, IMX290_INCKSEL3, clk_cfg->incksel3, &ret); 637 - imx290_write(imx290, IMX290_INCKSEL4, clk_cfg->incksel4, &ret); 638 - imx290_write(imx290, IMX290_INCKSEL5, clk_cfg->incksel5, &ret); 639 - imx290_write(imx290, IMX290_INCKSEL6, clk_cfg->incksel6, &ret); 692 + cci_write(imx290->regmap, IMX290_INCKSEL1, clk_cfg->incksel1, &ret); 693 + cci_write(imx290->regmap, IMX290_INCKSEL2, clk_cfg->incksel2, &ret); 694 + cci_write(imx290->regmap, IMX290_INCKSEL3, clk_cfg->incksel3, &ret); 695 + cci_write(imx290->regmap, IMX290_INCKSEL4, clk_cfg->incksel4, &ret); 696 + cci_write(imx290->regmap, IMX290_INCKSEL5, clk_cfg->incksel5, &ret); 697 + cci_write(imx290->regmap, IMX290_INCKSEL6, clk_cfg->incksel6, &ret); 640 698 641 699 return ret; 642 700 } ··· 645 703 { 646 704 int ret = 0; 647 705 648 - imx290_write(imx290, IMX290_PHY_LANE_NUM, imx290->nlanes - 1, &ret); 649 - imx290_write(imx290, IMX290_CSI_LANE_MODE, imx290->nlanes - 1, &ret); 650 - imx290_write(imx290, IMX290_FR_FDG_SEL, 0x01, &ret); 706 + cci_write(imx290->regmap, IMX290_PHY_LANE_NUM, imx290->nlanes - 1, 707 + &ret); 708 + cci_write(imx290->regmap, IMX290_CSI_LANE_MODE, imx290->nlanes - 1, 709 + &ret); 710 + cci_write(imx290->regmap, IMX290_FR_FDG_SEL, 0x01, &ret); 651 711 652 712 return ret; 653 713 } ··· 660 716 { 661 717 unsigned int bpp = imx290_format_info(imx290, format->code)->bpp; 662 718 663 - return imx290_write(imx290, IMX290_BLKLEVEL, 664 - black_level >> (16 - bpp), err); 719 + return cci_write(imx290->regmap, IMX290_BLKLEVEL, 720 + black_level >> (16 - bpp), err); 665 721 } 666 722 667 723 static int imx290_set_csi_config(struct imx290 *imx290) ··· 687 743 return -EINVAL; 688 744 } 689 745 690 - imx290_write(imx290, IMX290_REPETITION, csi_cfg->repetition, &ret); 691 - imx290_write(imx290, IMX290_TCLKPOST, csi_cfg->tclkpost, &ret); 692 - imx290_write(imx290, IMX290_THSZERO, csi_cfg->thszero, &ret); 693 - imx290_write(imx290, IMX290_THSPREPARE, csi_cfg->thsprepare, &ret); 694 - imx290_write(imx290, IMX290_TCLKTRAIL, csi_cfg->tclktrail, &ret); 695 - imx290_write(imx290, IMX290_THSTRAIL, csi_cfg->thstrail, &ret); 696 - imx290_write(imx290, IMX290_TCLKZERO, csi_cfg->tclkzero, &ret); 697 - imx290_write(imx290, IMX290_TCLKPREPARE, csi_cfg->tclkprepare, &ret); 698 - imx290_write(imx290, IMX290_TLPX, csi_cfg->tlpx, &ret); 746 + cci_write(imx290->regmap, IMX290_REPETITION, csi_cfg->repetition, &ret); 747 + cci_write(imx290->regmap, IMX290_TCLKPOST, csi_cfg->tclkpost, &ret); 748 + cci_write(imx290->regmap, IMX290_THSZERO, csi_cfg->thszero, &ret); 749 + cci_write(imx290->regmap, IMX290_THSPREPARE, csi_cfg->thsprepare, &ret); 750 + cci_write(imx290->regmap, IMX290_TCLKTRAIL, csi_cfg->tclktrail, &ret); 751 + cci_write(imx290->regmap, IMX290_THSTRAIL, csi_cfg->thstrail, &ret); 752 + cci_write(imx290->regmap, IMX290_TCLKZERO, csi_cfg->tclkzero, &ret); 753 + cci_write(imx290->regmap, IMX290_TCLKPREPARE, csi_cfg->tclkprepare, 754 + &ret); 755 + cci_write(imx290->regmap, IMX290_TLPX, csi_cfg->tlpx, &ret); 699 756 700 757 return ret; 701 758 } ··· 762 817 763 818 switch (ctrl->id) { 764 819 case V4L2_CID_ANALOGUE_GAIN: 765 - ret = imx290_write(imx290, IMX290_GAIN, ctrl->val, NULL); 820 + ret = cci_write(imx290->regmap, IMX290_GAIN, ctrl->val, NULL); 766 821 break; 767 822 768 823 case V4L2_CID_VBLANK: 769 - ret = imx290_write(imx290, IMX290_VMAX, 770 - ctrl->val + imx290->current_mode->height, 771 - NULL); 824 + ret = cci_write(imx290->regmap, IMX290_VMAX, 825 + ctrl->val + imx290->current_mode->height, NULL); 772 826 /* 773 827 * Due to the way that exposure is programmed in this sensor in 774 828 * relation to VMAX, we have to reprogramme it whenever VMAX is ··· 779 835 fallthrough; 780 836 case V4L2_CID_EXPOSURE: 781 837 vmax = imx290->vblank->val + imx290->current_mode->height; 782 - ret = imx290_write(imx290, IMX290_SHS1, 783 - vmax - ctrl->val - 1, NULL); 838 + ret = cci_write(imx290->regmap, IMX290_SHS1, 839 + vmax - ctrl->val - 1, NULL); 784 840 break; 785 841 786 842 case V4L2_CID_TEST_PATTERN: 787 843 if (ctrl->val) { 788 844 imx290_set_black_level(imx290, format, 0, &ret); 789 845 usleep_range(10000, 11000); 790 - imx290_write(imx290, IMX290_PGCTRL, 791 - (u8)(IMX290_PGCTRL_REGEN | 792 - IMX290_PGCTRL_THRU | 793 - IMX290_PGCTRL_MODE(ctrl->val)), &ret); 846 + cci_write(imx290->regmap, IMX290_PGCTRL, 847 + (u8)(IMX290_PGCTRL_REGEN | 848 + IMX290_PGCTRL_THRU | 849 + IMX290_PGCTRL_MODE(ctrl->val)), &ret); 794 850 } else { 795 - imx290_write(imx290, IMX290_PGCTRL, 0x00, &ret); 851 + cci_write(imx290->regmap, IMX290_PGCTRL, 0x00, &ret); 796 852 usleep_range(10000, 11000); 797 853 imx290_set_black_level(imx290, format, 798 854 IMX290_BLACK_LEVEL_DEFAULT, &ret); ··· 800 856 break; 801 857 802 858 case V4L2_CID_HBLANK: 803 - ret = imx290_write(imx290, IMX290_HMAX, 804 - ctrl->val + imx290->current_mode->width, 805 - NULL); 859 + ret = cci_write(imx290->regmap, IMX290_HMAX, 860 + ctrl->val + imx290->current_mode->width, NULL); 806 861 break; 807 862 808 863 case V4L2_CID_HFLIP: ··· 814 871 reg |= IMX290_HREVERSE; 815 872 if (imx290->vflip->val) 816 873 reg |= IMX290_VREVERSE; 817 - ret = imx290_write(imx290, IMX290_CTRL_07, reg, NULL); 874 + ret = cci_write(imx290->regmap, IMX290_CTRL_07, reg, NULL); 818 875 break; 819 876 } 820 877 ··· 1016 1073 return ret; 1017 1074 } 1018 1075 1019 - imx290_write(imx290, IMX290_STANDBY, 0x00, &ret); 1076 + cci_write(imx290->regmap, IMX290_STANDBY, 0x00, &ret); 1020 1077 1021 1078 msleep(30); 1022 1079 1023 1080 /* Start streaming */ 1024 - return imx290_write(imx290, IMX290_XMSTA, 0x00, &ret); 1081 + return cci_write(imx290->regmap, IMX290_XMSTA, 0x00, &ret); 1025 1082 } 1026 1083 1027 1084 /* Stop streaming */ ··· 1029 1086 { 1030 1087 int ret = 0; 1031 1088 1032 - imx290_write(imx290, IMX290_STANDBY, 0x01, &ret); 1089 + cci_write(imx290->regmap, IMX290_STANDBY, 0x01, &ret); 1033 1090 1034 1091 msleep(30); 1035 1092 1036 - return imx290_write(imx290, IMX290_XMSTA, 0x01, &ret); 1093 + return cci_write(imx290->regmap, IMX290_XMSTA, 0x01, &ret); 1037 1094 } 1038 1095 1039 1096 static int imx290_set_stream(struct v4l2_subdev *sd, int enable) ··· 1357 1414 * Probe & remove 1358 1415 */ 1359 1416 1360 - static const struct regmap_config imx290_regmap_config = { 1361 - .reg_bits = 16, 1362 - .val_bits = 8, 1363 - }; 1364 - 1365 1417 static const char * const imx290_supply_name[IMX290_NUM_SUPPLIES] = { 1366 1418 "vdda", 1367 1419 "vddd", ··· 1523 1585 return -ENOMEM; 1524 1586 1525 1587 imx290->dev = dev; 1526 - imx290->regmap = devm_regmap_init_i2c(client, &imx290_regmap_config); 1588 + imx290->regmap = devm_cci_regmap_init_i2c(client, 16); 1527 1589 if (IS_ERR(imx290->regmap)) { 1528 1590 dev_err(dev, "Unable to initialize I2C\n"); 1529 1591 return -ENODEV;