Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mattst88/alpha-2.6

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mattst88/alpha-2.6:
alpha: fix WARN_ON in __local_bh_enable()
alpha: fix breakage caused by df9ee29270
alpha: add GENERIC_HARDIRQS_NO__DO_IRQ to Kconfig
alpha/osf_sys: remove unused MAX_SELECT_SECONDS
alpha: change to new Makefile flag variables
alpha: kill off alpha_do_IRQ
alpha: irq clean up
alpha: use set_irq_chip and push down __do_IRQ to the machine types

+159 -504
+3
arch/alpha/Kconfig
··· 68 bool 69 default n 70 71 config GENERIC_HARDIRQS 72 bool 73 default y
··· 68 bool 69 default n 70 71 + config GENERIC_HARDIRQS_NO__DO_IRQ 72 + def_bool y 73 + 74 config GENERIC_HARDIRQS 75 bool 76 default y
+5 -3
arch/alpha/include/asm/io.h
··· 37 */ 38 extern inline void __set_hae(unsigned long new_hae) 39 { 40 - unsigned long flags; 41 - local_irq_save(flags); 42 43 alpha_mv.hae_cache = new_hae; 44 *alpha_mv.hae_register = new_hae; ··· 47 /* Re-read to make sure it was written. */ 48 new_hae = *alpha_mv.hae_register; 49 50 - local_irq_restore(flags); 51 } 52 53 extern inline void set_hae(unsigned long new_hae)
··· 37 */ 38 extern inline void __set_hae(unsigned long new_hae) 39 { 40 + unsigned long flags = swpipl(IPL_MAX); 41 + 42 + barrier(); 43 44 alpha_mv.hae_cache = new_hae; 45 *alpha_mv.hae_register = new_hae; ··· 46 /* Re-read to make sure it was written. */ 47 new_hae = *alpha_mv.hae_register; 48 49 + setipl(flags); 50 + barrier(); 51 } 52 53 extern inline void set_hae(unsigned long new_hae)
+2 -2
arch/alpha/kernel/Makefile
··· 3 # 4 5 extra-y := head.o vmlinux.lds 6 - EXTRA_AFLAGS := $(KBUILD_CFLAGS) 7 - EXTRA_CFLAGS := -Werror -Wno-sign-compare 8 9 obj-y := entry.o traps.o process.o init_task.o osf_sys.o irq.o \ 10 irq_alpha.o signal.o setup.o ptrace.o time.o \
··· 3 # 4 5 extra-y := head.o vmlinux.lds 6 + asflags-y := $(KBUILD_CFLAGS) 7 + ccflags-y := -Werror -Wno-sign-compare 8 9 obj-y := entry.o traps.o process.o init_task.o osf_sys.o irq.o \ 10 irq_alpha.o signal.o setup.o ptrace.o time.o \
+20 -11
arch/alpha/kernel/irq.c
··· 44 45 int irq_select_affinity(unsigned int irq) 46 { 47 static int last_cpu; 48 int cpu = last_cpu + 1; 49 50 - if (!irq_desc[irq].chip->set_affinity || irq_user_affinity[irq]) 51 return 1; 52 53 while (!cpu_possible(cpu) || ··· 56 cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0); 57 last_cpu = cpu; 58 59 - cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu)); 60 - irq_desc[irq].chip->set_affinity(irq, cpumask_of(cpu)); 61 return 0; 62 } 63 #endif /* CONFIG_SMP */ ··· 68 int j; 69 int irq = *(loff_t *) v; 70 struct irqaction * action; 71 unsigned long flags; 72 73 #ifdef CONFIG_SMP ··· 81 #endif 82 83 if (irq < ACTUAL_NR_IRQS) { 84 - raw_spin_lock_irqsave(&irq_desc[irq].lock, flags); 85 - action = irq_desc[irq].action; 86 if (!action) 87 goto unlock; 88 seq_printf(p, "%3d: ", irq); ··· 97 for_each_online_cpu(j) 98 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, j)); 99 #endif 100 - seq_printf(p, " %14s", irq_desc[irq].chip->name); 101 seq_printf(p, " %c%s", 102 (action->flags & IRQF_DISABLED)?'+':' ', 103 action->name); ··· 110 111 seq_putc(p, '\n'); 112 unlock: 113 - raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags); 114 } else if (irq == ACTUAL_NR_IRQS) { 115 #ifdef CONFIG_SMP 116 seq_puts(p, "IPI: "); ··· 149 * handled by some other CPU. (or is disabled) 150 */ 151 static unsigned int illegal_count=0; 152 153 - if ((unsigned) irq > ACTUAL_NR_IRQS && illegal_count < MAX_ILLEGAL_IRQS ) { 154 irq_err_count++; 155 illegal_count++; 156 printk(KERN_CRIT "device_interrupt: invalid interrupt %d\n", ··· 160 return; 161 } 162 163 - irq_enter(); 164 /* 165 - * __do_IRQ() must be called with IPL_MAX. Note that we do not 166 * explicitly enable interrupts afterwards - some MILO PALcode 167 * (namely LX164 one) seems to have severe problems with RTI 168 * at IPL 0. 169 */ 170 local_irq_disable(); 171 - __do_IRQ(irq); 172 irq_exit(); 173 }
··· 44 45 int irq_select_affinity(unsigned int irq) 46 { 47 + struct irq_desc *desc = irq_to_desc[irq]; 48 static int last_cpu; 49 int cpu = last_cpu + 1; 50 51 + if (!desc || !get_irq_desc_chip(desc)->set_affinity || irq_user_affinity[irq]) 52 return 1; 53 54 while (!cpu_possible(cpu) || ··· 55 cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0); 56 last_cpu = cpu; 57 58 + cpumask_copy(desc->affinity, cpumask_of(cpu)); 59 + get_irq_desc_chip(desc)->set_affinity(irq, cpumask_of(cpu)); 60 return 0; 61 } 62 #endif /* CONFIG_SMP */ ··· 67 int j; 68 int irq = *(loff_t *) v; 69 struct irqaction * action; 70 + struct irq_desc *desc; 71 unsigned long flags; 72 73 #ifdef CONFIG_SMP ··· 79 #endif 80 81 if (irq < ACTUAL_NR_IRQS) { 82 + desc = irq_to_desc(irq); 83 + 84 + if (!desc) 85 + return 0; 86 + 87 + raw_spin_lock_irqsave(&desc->lock, flags); 88 + action = desc->action; 89 if (!action) 90 goto unlock; 91 seq_printf(p, "%3d: ", irq); ··· 90 for_each_online_cpu(j) 91 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, j)); 92 #endif 93 + seq_printf(p, " %14s", get_irq_desc_chip(desc)->name); 94 seq_printf(p, " %c%s", 95 (action->flags & IRQF_DISABLED)?'+':' ', 96 action->name); ··· 103 104 seq_putc(p, '\n'); 105 unlock: 106 + raw_spin_unlock_irqrestore(&desc->lock, flags); 107 } else if (irq == ACTUAL_NR_IRQS) { 108 #ifdef CONFIG_SMP 109 seq_puts(p, "IPI: "); ··· 142 * handled by some other CPU. (or is disabled) 143 */ 144 static unsigned int illegal_count=0; 145 + struct irq_desc *desc = irq_to_desc(irq); 146 147 + if (!desc || ((unsigned) irq > ACTUAL_NR_IRQS && 148 + illegal_count < MAX_ILLEGAL_IRQS)) { 149 irq_err_count++; 150 illegal_count++; 151 printk(KERN_CRIT "device_interrupt: invalid interrupt %d\n", ··· 151 return; 152 } 153 154 /* 155 + * From here we must proceed with IPL_MAX. Note that we do not 156 * explicitly enable interrupts afterwards - some MILO PALcode 157 * (namely LX164 one) seems to have severe problems with RTI 158 * at IPL 0. 159 */ 160 local_irq_disable(); 161 + irq_enter(); 162 + generic_handle_irq_desc(irq, desc); 163 irq_exit(); 164 }
+8 -16
arch/alpha/kernel/irq_alpha.c
··· 219 * processed by PALcode, and comes in via entInt vector 1. 220 */ 221 222 - static void rtc_enable_disable(unsigned int irq) { } 223 - static unsigned int rtc_startup(unsigned int irq) { return 0; } 224 - 225 struct irqaction timer_irqaction = { 226 .handler = timer_interrupt, 227 .flags = IRQF_DISABLED, 228 .name = "timer", 229 }; 230 231 - static struct irq_chip rtc_irq_type = { 232 - .name = "RTC", 233 - .startup = rtc_startup, 234 - .shutdown = rtc_enable_disable, 235 - .enable = rtc_enable_disable, 236 - .disable = rtc_enable_disable, 237 - .ack = rtc_enable_disable, 238 - .end = rtc_enable_disable, 239 - }; 240 - 241 void __init 242 init_rtc_irq(void) 243 { 244 - irq_desc[RTC_IRQ].status = IRQ_DISABLED; 245 - irq_desc[RTC_IRQ].chip = &rtc_irq_type; 246 - setup_irq(RTC_IRQ, &timer_irqaction); 247 } 248 249 /* Dummy irqactions. */
··· 219 * processed by PALcode, and comes in via entInt vector 1. 220 */ 221 222 struct irqaction timer_irqaction = { 223 .handler = timer_interrupt, 224 .flags = IRQF_DISABLED, 225 .name = "timer", 226 }; 227 228 void __init 229 init_rtc_irq(void) 230 { 231 + struct irq_desc *desc = irq_to_desc(RTC_IRQ); 232 + 233 + if (desc) { 234 + desc->status |= IRQ_DISABLED; 235 + set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip, 236 + handle_simple_irq, "RTC"); 237 + setup_irq(RTC_IRQ, &timer_irqaction); 238 + } 239 } 240 241 /* Dummy irqactions. */
+4 -22
arch/alpha/kernel/irq_i8259.c
··· 69 spin_unlock(&i8259_irq_lock); 70 } 71 72 - unsigned int 73 - i8259a_startup_irq(unsigned int irq) 74 - { 75 - i8259a_enable_irq(irq); 76 - return 0; /* never anything pending */ 77 - } 78 - 79 - void 80 - i8259a_end_irq(unsigned int irq) 81 - { 82 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 83 - i8259a_enable_irq(irq); 84 - } 85 - 86 struct irq_chip i8259a_irq_type = { 87 .name = "XT-PIC", 88 - .startup = i8259a_startup_irq, 89 - .shutdown = i8259a_disable_irq, 90 - .enable = i8259a_enable_irq, 91 - .disable = i8259a_disable_irq, 92 - .ack = i8259a_mask_and_ack_irq, 93 - .end = i8259a_end_irq, 94 }; 95 96 void __init ··· 90 outb(0xff, 0xA1); /* mask all of 8259A-2 */ 91 92 for (i = 0; i < 16; i++) { 93 - irq_desc[i].status = IRQ_DISABLED; 94 - irq_desc[i].chip = &i8259a_irq_type; 95 } 96 97 setup_irq(2, &cascade);
··· 69 spin_unlock(&i8259_irq_lock); 70 } 71 72 struct irq_chip i8259a_irq_type = { 73 .name = "XT-PIC", 74 + .unmask = i8259a_enable_irq, 75 + .mask = i8259a_disable_irq, 76 + .mask_ack = i8259a_mask_and_ack_irq, 77 }; 78 79 void __init ··· 107 outb(0xff, 0xA1); /* mask all of 8259A-2 */ 108 109 for (i = 0; i < 16; i++) { 110 + set_irq_chip_and_handler(i, &i8259a_irq_type, handle_level_irq); 111 } 112 113 setup_irq(2, &cascade);
+5 -22
arch/alpha/kernel/irq_pyxis.c
··· 40 pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16))); 41 } 42 43 - static unsigned int 44 - pyxis_startup_irq(unsigned int irq) 45 - { 46 - pyxis_enable_irq(irq); 47 - return 0; 48 - } 49 - 50 - static void 51 - pyxis_end_irq(unsigned int irq) 52 - { 53 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 54 - pyxis_enable_irq(irq); 55 - } 56 - 57 static void 58 pyxis_mask_and_ack_irq(unsigned int irq) 59 { ··· 58 59 static struct irq_chip pyxis_irq_type = { 60 .name = "PYXIS", 61 - .startup = pyxis_startup_irq, 62 - .shutdown = pyxis_disable_irq, 63 - .enable = pyxis_enable_irq, 64 - .disable = pyxis_disable_irq, 65 - .ack = pyxis_mask_and_ack_irq, 66 - .end = pyxis_end_irq, 67 }; 68 69 void ··· 102 for (i = 16; i < 48; ++i) { 103 if ((ignore_mask >> i) & 1) 104 continue; 105 - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 106 - irq_desc[i].chip = &pyxis_irq_type; 107 } 108 109 setup_irq(16+7, &isa_cascade_irqaction);
··· 40 pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16))); 41 } 42 43 static void 44 pyxis_mask_and_ack_irq(unsigned int irq) 45 { ··· 72 73 static struct irq_chip pyxis_irq_type = { 74 .name = "PYXIS", 75 + .mask_ack = pyxis_mask_and_ack_irq, 76 + .mask = pyxis_disable_irq, 77 + .unmask = pyxis_enable_irq, 78 }; 79 80 void ··· 119 for (i = 16; i < 48; ++i) { 120 if ((ignore_mask >> i) & 1) 121 continue; 122 + set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq); 123 + irq_to_desc(i)->status |= IRQ_LEVEL; 124 } 125 126 setup_irq(16+7, &isa_cascade_irqaction);
+5 -22
arch/alpha/kernel/irq_srm.c
··· 33 spin_unlock(&srm_irq_lock); 34 } 35 36 - static unsigned int 37 - srm_startup_irq(unsigned int irq) 38 - { 39 - srm_enable_irq(irq); 40 - return 0; 41 - } 42 - 43 - static void 44 - srm_end_irq(unsigned int irq) 45 - { 46 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 47 - srm_enable_irq(irq); 48 - } 49 - 50 /* Handle interrupts from the SRM, assuming no additional weirdness. */ 51 static struct irq_chip srm_irq_type = { 52 .name = "SRM", 53 - .startup = srm_startup_irq, 54 - .shutdown = srm_disable_irq, 55 - .enable = srm_enable_irq, 56 - .disable = srm_disable_irq, 57 - .ack = srm_disable_irq, 58 - .end = srm_end_irq, 59 }; 60 61 void __init ··· 51 for (i = 16; i < max; ++i) { 52 if (i < 64 && ((ignore_mask >> i) & 1)) 53 continue; 54 - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 55 - irq_desc[i].chip = &srm_irq_type; 56 } 57 } 58
··· 33 spin_unlock(&srm_irq_lock); 34 } 35 36 /* Handle interrupts from the SRM, assuming no additional weirdness. */ 37 static struct irq_chip srm_irq_type = { 38 .name = "SRM", 39 + .unmask = srm_enable_irq, 40 + .mask = srm_disable_irq, 41 + .mask_ack = srm_disable_irq, 42 }; 43 44 void __init ··· 68 for (i = 16; i < max; ++i) { 69 if (i < 64 && ((ignore_mask >> i) & 1)) 70 continue; 71 + set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq); 72 + irq_to_desc(i)->status |= IRQ_LEVEL; 73 } 74 } 75
-3
arch/alpha/kernel/osf_sys.c
··· 951 return do_utimes(AT_FDCWD, filename, tvs ? tv : NULL, 0); 952 } 953 954 - #define MAX_SELECT_SECONDS \ 955 - ((unsigned long) (MAX_SCHEDULE_TIMEOUT / HZ)-1) 956 - 957 SYSCALL_DEFINE5(osf_select, int, n, fd_set __user *, inp, fd_set __user *, outp, 958 fd_set __user *, exp, struct timeval32 __user *, tvp) 959 {
··· 951 return do_utimes(AT_FDCWD, filename, tvs ? tv : NULL, 0); 952 } 953 954 SYSCALL_DEFINE5(osf_select, int, n, fd_set __user *, inp, fd_set __user *, outp, 955 fd_set __user *, exp, struct timeval32 __user *, tvp) 956 {
+5 -22
arch/alpha/kernel/sys_alcor.c
··· 65 *(vuip)GRU_INT_CLEAR = 0; mb(); 66 } 67 68 - static unsigned int 69 - alcor_startup_irq(unsigned int irq) 70 - { 71 - alcor_enable_irq(irq); 72 - return 0; 73 - } 74 - 75 static void 76 alcor_isa_mask_and_ack_irq(unsigned int irq) 77 { ··· 75 *(vuip)GRU_INT_CLEAR = 0; mb(); 76 } 77 78 - static void 79 - alcor_end_irq(unsigned int irq) 80 - { 81 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 82 - alcor_enable_irq(irq); 83 - } 84 - 85 static struct irq_chip alcor_irq_type = { 86 .name = "ALCOR", 87 - .startup = alcor_startup_irq, 88 - .shutdown = alcor_disable_irq, 89 - .enable = alcor_enable_irq, 90 - .disable = alcor_disable_irq, 91 - .ack = alcor_mask_and_ack_irq, 92 - .end = alcor_end_irq, 93 }; 94 95 static void ··· 125 on while IRQ probing. */ 126 if (i >= 16+20 && i <= 16+30) 127 continue; 128 - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 129 - irq_desc[i].chip = &alcor_irq_type; 130 } 131 i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq; 132
··· 65 *(vuip)GRU_INT_CLEAR = 0; mb(); 66 } 67 68 static void 69 alcor_isa_mask_and_ack_irq(unsigned int irq) 70 { ··· 82 *(vuip)GRU_INT_CLEAR = 0; mb(); 83 } 84 85 static struct irq_chip alcor_irq_type = { 86 .name = "ALCOR", 87 + .unmask = alcor_enable_irq, 88 + .mask = alcor_disable_irq, 89 + .mask_ack = alcor_mask_and_ack_irq, 90 }; 91 92 static void ··· 142 on while IRQ probing. */ 143 if (i >= 16+20 && i <= 16+30) 144 continue; 145 + set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq); 146 + irq_to_desc(i)->status |= IRQ_LEVEL; 147 } 148 i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq; 149
+6 -22
arch/alpha/kernel/sys_cabriolet.c
··· 57 cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq); 58 } 59 60 - static unsigned int 61 - cabriolet_startup_irq(unsigned int irq) 62 - { 63 - cabriolet_enable_irq(irq); 64 - return 0; /* never anything pending */ 65 - } 66 - 67 - static void 68 - cabriolet_end_irq(unsigned int irq) 69 - { 70 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 71 - cabriolet_enable_irq(irq); 72 - } 73 - 74 static struct irq_chip cabriolet_irq_type = { 75 .name = "CABRIOLET", 76 - .startup = cabriolet_startup_irq, 77 - .shutdown = cabriolet_disable_irq, 78 - .enable = cabriolet_enable_irq, 79 - .disable = cabriolet_disable_irq, 80 - .ack = cabriolet_disable_irq, 81 - .end = cabriolet_end_irq, 82 }; 83 84 static void ··· 105 outb(0xff, 0x806); 106 107 for (i = 16; i < 35; ++i) { 108 - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 109 - irq_desc[i].chip = &cabriolet_irq_type; 110 } 111 } 112
··· 57 cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq); 58 } 59 60 static struct irq_chip cabriolet_irq_type = { 61 .name = "CABRIOLET", 62 + .unmask = cabriolet_enable_irq, 63 + .mask = cabriolet_disable_irq, 64 + .mask_ack = cabriolet_disable_irq, 65 }; 66 67 static void ··· 122 outb(0xff, 0x806); 123 124 for (i = 16; i < 35; ++i) { 125 + set_irq_chip_and_handler(i, &cabriolet_irq_type, 126 + handle_level_irq); 127 + irq_to_desc(i)->status |= IRQ_LEVEL; 128 } 129 } 130
+8 -42
arch/alpha/kernel/sys_dp264.c
··· 115 spin_unlock(&dp264_irq_lock); 116 } 117 118 - static unsigned int 119 - dp264_startup_irq(unsigned int irq) 120 - { 121 - dp264_enable_irq(irq); 122 - return 0; /* never anything pending */ 123 - } 124 - 125 - static void 126 - dp264_end_irq(unsigned int irq) 127 - { 128 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 129 - dp264_enable_irq(irq); 130 - } 131 - 132 static void 133 clipper_enable_irq(unsigned int irq) 134 { ··· 131 cached_irq_mask &= ~(1UL << (irq - 16)); 132 tsunami_update_irq_hw(cached_irq_mask); 133 spin_unlock(&dp264_irq_lock); 134 - } 135 - 136 - static unsigned int 137 - clipper_startup_irq(unsigned int irq) 138 - { 139 - clipper_enable_irq(irq); 140 - return 0; /* never anything pending */ 141 - } 142 - 143 - static void 144 - clipper_end_irq(unsigned int irq) 145 - { 146 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 147 - clipper_enable_irq(irq); 148 } 149 150 static void ··· 172 173 static struct irq_chip dp264_irq_type = { 174 .name = "DP264", 175 - .startup = dp264_startup_irq, 176 - .shutdown = dp264_disable_irq, 177 - .enable = dp264_enable_irq, 178 - .disable = dp264_disable_irq, 179 - .ack = dp264_disable_irq, 180 - .end = dp264_end_irq, 181 .set_affinity = dp264_set_affinity, 182 }; 183 184 static struct irq_chip clipper_irq_type = { 185 .name = "CLIPPER", 186 - .startup = clipper_startup_irq, 187 - .shutdown = clipper_disable_irq, 188 - .enable = clipper_enable_irq, 189 - .disable = clipper_disable_irq, 190 - .ack = clipper_disable_irq, 191 - .end = clipper_end_irq, 192 .set_affinity = clipper_set_affinity, 193 }; 194 ··· 268 { 269 long i; 270 for (i = imin; i <= imax; ++i) { 271 - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 272 - irq_desc[i].chip = ops; 273 } 274 } 275
··· 115 spin_unlock(&dp264_irq_lock); 116 } 117 118 static void 119 clipper_enable_irq(unsigned int irq) 120 { ··· 145 cached_irq_mask &= ~(1UL << (irq - 16)); 146 tsunami_update_irq_hw(cached_irq_mask); 147 spin_unlock(&dp264_irq_lock); 148 } 149 150 static void ··· 200 201 static struct irq_chip dp264_irq_type = { 202 .name = "DP264", 203 + .unmask = dp264_enable_irq, 204 + .mask = dp264_disable_irq, 205 + .mask_ack = dp264_disable_irq, 206 .set_affinity = dp264_set_affinity, 207 }; 208 209 static struct irq_chip clipper_irq_type = { 210 .name = "CLIPPER", 211 + .unmask = clipper_enable_irq, 212 + .mask = clipper_disable_irq, 213 + .mask_ack = clipper_disable_irq, 214 .set_affinity = clipper_set_affinity, 215 }; 216 ··· 302 { 303 long i; 304 for (i = imin; i <= imax; ++i) { 305 + irq_to_desc(i)->status |= IRQ_LEVEL; 306 + set_irq_chip_and_handler(i, ops, handle_level_irq); 307 } 308 } 309
+5 -22
arch/alpha/kernel/sys_eb64p.c
··· 55 eb64p_update_irq_hw(irq, cached_irq_mask |= 1 << irq); 56 } 57 58 - static unsigned int 59 - eb64p_startup_irq(unsigned int irq) 60 - { 61 - eb64p_enable_irq(irq); 62 - return 0; /* never anything pending */ 63 - } 64 - 65 - static void 66 - eb64p_end_irq(unsigned int irq) 67 - { 68 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 69 - eb64p_enable_irq(irq); 70 - } 71 - 72 static struct irq_chip eb64p_irq_type = { 73 .name = "EB64P", 74 - .startup = eb64p_startup_irq, 75 - .shutdown = eb64p_disable_irq, 76 - .enable = eb64p_enable_irq, 77 - .disable = eb64p_disable_irq, 78 - .ack = eb64p_disable_irq, 79 - .end = eb64p_end_irq, 80 }; 81 82 static void ··· 118 init_i8259a_irqs(); 119 120 for (i = 16; i < 32; ++i) { 121 - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 122 - irq_desc[i].chip = &eb64p_irq_type; 123 } 124 125 common_init_isa_dma();
··· 55 eb64p_update_irq_hw(irq, cached_irq_mask |= 1 << irq); 56 } 57 58 static struct irq_chip eb64p_irq_type = { 59 .name = "EB64P", 60 + .unmask = eb64p_enable_irq, 61 + .mask = eb64p_disable_irq, 62 + .mask_ack = eb64p_disable_irq, 63 }; 64 65 static void ··· 135 init_i8259a_irqs(); 136 137 for (i = 16; i < 32; ++i) { 138 + irq_to_desc(i)->status |= IRQ_LEVEL; 139 + set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq); 140 } 141 142 common_init_isa_dma();
+5 -22
arch/alpha/kernel/sys_eiger.c
··· 66 eiger_update_irq_hw(irq, mask); 67 } 68 69 - static unsigned int 70 - eiger_startup_irq(unsigned int irq) 71 - { 72 - eiger_enable_irq(irq); 73 - return 0; /* never anything pending */ 74 - } 75 - 76 - static void 77 - eiger_end_irq(unsigned int irq) 78 - { 79 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 80 - eiger_enable_irq(irq); 81 - } 82 - 83 static struct irq_chip eiger_irq_type = { 84 .name = "EIGER", 85 - .startup = eiger_startup_irq, 86 - .shutdown = eiger_disable_irq, 87 - .enable = eiger_enable_irq, 88 - .disable = eiger_disable_irq, 89 - .ack = eiger_disable_irq, 90 - .end = eiger_end_irq, 91 }; 92 93 static void ··· 136 init_i8259a_irqs(); 137 138 for (i = 16; i < 128; ++i) { 139 - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 140 - irq_desc[i].chip = &eiger_irq_type; 141 } 142 } 143
··· 66 eiger_update_irq_hw(irq, mask); 67 } 68 69 static struct irq_chip eiger_irq_type = { 70 .name = "EIGER", 71 + .unmask = eiger_enable_irq, 72 + .mask = eiger_disable_irq, 73 + .mask_ack = eiger_disable_irq, 74 }; 75 76 static void ··· 153 init_i8259a_irqs(); 154 155 for (i = 16; i < 128; ++i) { 156 + irq_to_desc(i)->status |= IRQ_LEVEL; 157 + set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq); 158 } 159 } 160
+10 -45
arch/alpha/kernel/sys_jensen.c
··· 62 * world. 63 */ 64 65 - static unsigned int 66 - jensen_local_startup(unsigned int irq) 67 - { 68 - /* the parport is really hw IRQ 1, silly Jensen. */ 69 - if (irq == 7) 70 - i8259a_startup_irq(1); 71 - else 72 - /* 73 - * For all true local interrupts, set the flag that prevents 74 - * the IPL from being dropped during handler processing. 75 - */ 76 - if (irq_desc[irq].action) 77 - irq_desc[irq].action->flags |= IRQF_DISABLED; 78 - return 0; 79 - } 80 - 81 - static void 82 - jensen_local_shutdown(unsigned int irq) 83 - { 84 - /* the parport is really hw IRQ 1, silly Jensen. */ 85 - if (irq == 7) 86 - i8259a_disable_irq(1); 87 - } 88 - 89 static void 90 jensen_local_enable(unsigned int irq) 91 { ··· 79 } 80 81 static void 82 - jensen_local_ack(unsigned int irq) 83 { 84 /* the parport is really hw IRQ 1, silly Jensen. */ 85 if (irq == 7) 86 i8259a_mask_and_ack_irq(1); 87 } 88 89 - static void 90 - jensen_local_end(unsigned int irq) 91 - { 92 - /* the parport is really hw IRQ 1, silly Jensen. */ 93 - if (irq == 7) 94 - i8259a_end_irq(1); 95 - } 96 - 97 static struct irq_chip jensen_local_irq_type = { 98 .name = "LOCAL", 99 - .startup = jensen_local_startup, 100 - .shutdown = jensen_local_shutdown, 101 - .enable = jensen_local_enable, 102 - .disable = jensen_local_disable, 103 - .ack = jensen_local_ack, 104 - .end = jensen_local_end, 105 }; 106 107 static void ··· 123 } 124 125 /* If there is no handler yet... */ 126 - if (irq_desc[irq].action == NULL) { 127 /* If it is a local interrupt that cannot be masked... */ 128 if (vector >= 0x900) 129 { ··· 171 { 172 init_i8259a_irqs(); 173 174 - irq_desc[1].chip = &jensen_local_irq_type; 175 - irq_desc[4].chip = &jensen_local_irq_type; 176 - irq_desc[3].chip = &jensen_local_irq_type; 177 - irq_desc[7].chip = &jensen_local_irq_type; 178 - irq_desc[9].chip = &jensen_local_irq_type; 179 180 common_init_isa_dma(); 181 }
··· 62 * world. 63 */ 64 65 static void 66 jensen_local_enable(unsigned int irq) 67 { ··· 103 } 104 105 static void 106 + jensen_local_mask_ack(unsigned int irq) 107 { 108 /* the parport is really hw IRQ 1, silly Jensen. */ 109 if (irq == 7) 110 i8259a_mask_and_ack_irq(1); 111 } 112 113 static struct irq_chip jensen_local_irq_type = { 114 .name = "LOCAL", 115 + .unmask = jensen_local_enable, 116 + .mask = jensen_local_disable, 117 + .mask_ack = jensen_local_mask_ack, 118 }; 119 120 static void ··· 158 } 159 160 /* If there is no handler yet... */ 161 + if (!irq_has_action(irq)) { 162 /* If it is a local interrupt that cannot be masked... */ 163 if (vector >= 0x900) 164 { ··· 206 { 207 init_i8259a_irqs(); 208 209 + set_irq_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq); 210 + set_irq_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq); 211 + set_irq_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq); 212 + set_irq_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq); 213 + set_irq_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq); 214 215 common_init_isa_dma(); 216 }
+13 -37
arch/alpha/kernel/sys_marvel.c
··· 143 spin_unlock(&io7->irq_lock); 144 } 145 146 - static unsigned int 147 - io7_startup_irq(unsigned int irq) 148 - { 149 - io7_enable_irq(irq); 150 - return 0; /* never anything pending */ 151 - } 152 - 153 - static void 154 - io7_end_irq(unsigned int irq) 155 - { 156 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 157 - io7_enable_irq(irq); 158 - } 159 - 160 static void 161 marvel_irq_noop(unsigned int irq) 162 { ··· 157 158 static struct irq_chip marvel_legacy_irq_type = { 159 .name = "LEGACY", 160 - .startup = marvel_irq_noop_return, 161 - .shutdown = marvel_irq_noop, 162 - .enable = marvel_irq_noop, 163 - .disable = marvel_irq_noop, 164 - .ack = marvel_irq_noop, 165 - .end = marvel_irq_noop, 166 }; 167 168 static struct irq_chip io7_lsi_irq_type = { 169 .name = "LSI", 170 - .startup = io7_startup_irq, 171 - .shutdown = io7_disable_irq, 172 - .enable = io7_enable_irq, 173 - .disable = io7_disable_irq, 174 - .ack = io7_disable_irq, 175 - .end = io7_end_irq, 176 }; 177 178 static struct irq_chip io7_msi_irq_type = { 179 .name = "MSI", 180 - .startup = io7_startup_irq, 181 - .shutdown = io7_disable_irq, 182 - .enable = io7_enable_irq, 183 - .disable = io7_disable_irq, 184 .ack = marvel_irq_noop, 185 - .end = io7_end_irq, 186 }; 187 188 static void ··· 280 281 /* Set up the lsi irqs. */ 282 for (i = 0; i < 128; ++i) { 283 - irq_desc[base + i].status = IRQ_DISABLED | IRQ_LEVEL; 284 - irq_desc[base + i].chip = lsi_ops; 285 } 286 287 /* Disable the implemented irqs in hardware. */ ··· 294 295 /* Set up the msi irqs. */ 296 for (i = 128; i < (128 + 512); ++i) { 297 - irq_desc[base + i].status = IRQ_DISABLED | IRQ_LEVEL; 298 - irq_desc[base + i].chip = msi_ops; 299 } 300 301 for (i = 0; i < 16; ++i) ··· 312 313 /* Reserve the legacy irqs. */ 314 for (i = 0; i < 16; ++i) { 315 - irq_desc[i].status = IRQ_DISABLED; 316 - irq_desc[i].chip = &marvel_legacy_irq_type; 317 } 318 319 /* Init the io7 irqs. */
··· 143 spin_unlock(&io7->irq_lock); 144 } 145 146 static void 147 marvel_irq_noop(unsigned int irq) 148 { ··· 171 172 static struct irq_chip marvel_legacy_irq_type = { 173 .name = "LEGACY", 174 + .mask = marvel_irq_noop, 175 + .unmask = marvel_irq_noop, 176 }; 177 178 static struct irq_chip io7_lsi_irq_type = { 179 .name = "LSI", 180 + .unmask = io7_enable_irq, 181 + .mask = io7_disable_irq, 182 + .mask_ack = io7_disable_irq, 183 }; 184 185 static struct irq_chip io7_msi_irq_type = { 186 .name = "MSI", 187 + .unmask = io7_enable_irq, 188 + .mask = io7_disable_irq, 189 .ack = marvel_irq_noop, 190 }; 191 192 static void ··· 304 305 /* Set up the lsi irqs. */ 306 for (i = 0; i < 128; ++i) { 307 + irq_to_desc(base + i)->status |= IRQ_LEVEL; 308 + set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq); 309 } 310 311 /* Disable the implemented irqs in hardware. */ ··· 318 319 /* Set up the msi irqs. */ 320 for (i = 128; i < (128 + 512); ++i) { 321 + irq_to_desc(base + i)->status |= IRQ_LEVEL; 322 + set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq); 323 } 324 325 for (i = 0; i < 16; ++i) ··· 336 337 /* Reserve the legacy irqs. */ 338 for (i = 0; i < 16; ++i) { 339 + set_irq_chip_and_handler(i, &marvel_legacy_irq_type, 340 + handle_level_irq); 341 } 342 343 /* Init the io7 irqs. */
+5 -22
arch/alpha/kernel/sys_mikasa.c
··· 54 mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16))); 55 } 56 57 - static unsigned int 58 - mikasa_startup_irq(unsigned int irq) 59 - { 60 - mikasa_enable_irq(irq); 61 - return 0; 62 - } 63 - 64 - static void 65 - mikasa_end_irq(unsigned int irq) 66 - { 67 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 68 - mikasa_enable_irq(irq); 69 - } 70 - 71 static struct irq_chip mikasa_irq_type = { 72 .name = "MIKASA", 73 - .startup = mikasa_startup_irq, 74 - .shutdown = mikasa_disable_irq, 75 - .enable = mikasa_enable_irq, 76 - .disable = mikasa_disable_irq, 77 - .ack = mikasa_disable_irq, 78 - .end = mikasa_end_irq, 79 }; 80 81 static void ··· 98 mikasa_update_irq_hw(0); 99 100 for (i = 16; i < 32; ++i) { 101 - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 102 - irq_desc[i].chip = &mikasa_irq_type; 103 } 104 105 init_i8259a_irqs();
··· 54 mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16))); 55 } 56 57 static struct irq_chip mikasa_irq_type = { 58 .name = "MIKASA", 59 + .unmask = mikasa_enable_irq, 60 + .mask = mikasa_disable_irq, 61 + .mask_ack = mikasa_disable_irq, 62 }; 63 64 static void ··· 115 mikasa_update_irq_hw(0); 116 117 for (i = 16; i < 32; ++i) { 118 + irq_to_desc(i)->status |= IRQ_LEVEL; 119 + set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq); 120 } 121 122 init_i8259a_irqs();
+5 -22
arch/alpha/kernel/sys_noritake.c
··· 59 noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16))); 60 } 61 62 - static unsigned int 63 - noritake_startup_irq(unsigned int irq) 64 - { 65 - noritake_enable_irq(irq); 66 - return 0; 67 - } 68 - 69 - static void 70 - noritake_end_irq(unsigned int irq) 71 - { 72 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 73 - noritake_enable_irq(irq); 74 - } 75 - 76 static struct irq_chip noritake_irq_type = { 77 .name = "NORITAKE", 78 - .startup = noritake_startup_irq, 79 - .shutdown = noritake_disable_irq, 80 - .enable = noritake_enable_irq, 81 - .disable = noritake_disable_irq, 82 - .ack = noritake_disable_irq, 83 - .end = noritake_end_irq, 84 }; 85 86 static void ··· 127 outw(0, 0x54c); 128 129 for (i = 16; i < 48; ++i) { 130 - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 131 - irq_desc[i].chip = &noritake_irq_type; 132 } 133 134 init_i8259a_irqs();
··· 59 noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16))); 60 } 61 62 static struct irq_chip noritake_irq_type = { 63 .name = "NORITAKE", 64 + .unmask = noritake_enable_irq, 65 + .mask = noritake_disable_irq, 66 + .mask_ack = noritake_disable_irq, 67 }; 68 69 static void ··· 144 outw(0, 0x54c); 145 146 for (i = 16; i < 48; ++i) { 147 + irq_to_desc(i)->status |= IRQ_LEVEL; 148 + set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq); 149 } 150 151 init_i8259a_irqs();
+5 -22
arch/alpha/kernel/sys_rawhide.c
··· 121 spin_unlock(&rawhide_irq_lock); 122 } 123 124 - static unsigned int 125 - rawhide_startup_irq(unsigned int irq) 126 - { 127 - rawhide_enable_irq(irq); 128 - return 0; 129 - } 130 - 131 - static void 132 - rawhide_end_irq(unsigned int irq) 133 - { 134 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 135 - rawhide_enable_irq(irq); 136 - } 137 - 138 static struct irq_chip rawhide_irq_type = { 139 .name = "RAWHIDE", 140 - .startup = rawhide_startup_irq, 141 - .shutdown = rawhide_disable_irq, 142 - .enable = rawhide_enable_irq, 143 - .disable = rawhide_disable_irq, 144 - .ack = rawhide_mask_and_ack_irq, 145 - .end = rawhide_end_irq, 146 }; 147 148 static void ··· 177 } 178 179 for (i = 16; i < 128; ++i) { 180 - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 181 - irq_desc[i].chip = &rawhide_irq_type; 182 } 183 184 init_i8259a_irqs();
··· 121 spin_unlock(&rawhide_irq_lock); 122 } 123 124 static struct irq_chip rawhide_irq_type = { 125 .name = "RAWHIDE", 126 + .unmask = rawhide_enable_irq, 127 + .mask = rawhide_disable_irq, 128 + .mask_ack = rawhide_mask_and_ack_irq, 129 }; 130 131 static void ··· 194 } 195 196 for (i = 16; i < 128; ++i) { 197 + irq_to_desc(i)->status |= IRQ_LEVEL; 198 + set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq); 199 } 200 201 init_i8259a_irqs();
+5 -22
arch/alpha/kernel/sys_rx164.c
··· 58 rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16))); 59 } 60 61 - static unsigned int 62 - rx164_startup_irq(unsigned int irq) 63 - { 64 - rx164_enable_irq(irq); 65 - return 0; 66 - } 67 - 68 - static void 69 - rx164_end_irq(unsigned int irq) 70 - { 71 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 72 - rx164_enable_irq(irq); 73 - } 74 - 75 static struct irq_chip rx164_irq_type = { 76 .name = "RX164", 77 - .startup = rx164_startup_irq, 78 - .shutdown = rx164_disable_irq, 79 - .enable = rx164_enable_irq, 80 - .disable = rx164_disable_irq, 81 - .ack = rx164_disable_irq, 82 - .end = rx164_end_irq, 83 }; 84 85 static void ··· 99 100 rx164_update_irq_hw(0); 101 for (i = 16; i < 40; ++i) { 102 - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 103 - irq_desc[i].chip = &rx164_irq_type; 104 } 105 106 init_i8259a_irqs();
··· 58 rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16))); 59 } 60 61 static struct irq_chip rx164_irq_type = { 62 .name = "RX164", 63 + .unmask = rx164_enable_irq, 64 + .mask = rx164_disable_irq, 65 + .mask_ack = rx164_disable_irq, 66 }; 67 68 static void ··· 116 117 rx164_update_irq_hw(0); 118 for (i = 16; i < 40; ++i) { 119 + irq_to_desc(i)->status |= IRQ_LEVEL; 120 + set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq); 121 } 122 123 init_i8259a_irqs();
+6 -22
arch/alpha/kernel/sys_sable.c
··· 474 #endif 475 } 476 477 - static unsigned int 478 - sable_lynx_startup_irq(unsigned int irq) 479 - { 480 - sable_lynx_enable_irq(irq); 481 - return 0; 482 - } 483 - 484 - static void 485 - sable_lynx_end_irq(unsigned int irq) 486 - { 487 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 488 - sable_lynx_enable_irq(irq); 489 - } 490 - 491 static void 492 sable_lynx_mask_and_ack_irq(unsigned int irq) 493 { ··· 489 490 static struct irq_chip sable_lynx_irq_type = { 491 .name = "SABLE/LYNX", 492 - .startup = sable_lynx_startup_irq, 493 - .shutdown = sable_lynx_disable_irq, 494 - .enable = sable_lynx_enable_irq, 495 - .disable = sable_lynx_disable_irq, 496 - .ack = sable_lynx_mask_and_ack_irq, 497 - .end = sable_lynx_end_irq, 498 }; 499 500 static void ··· 518 long i; 519 520 for (i = 0; i < nr_of_irqs; ++i) { 521 - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 522 - irq_desc[i].chip = &sable_lynx_irq_type; 523 } 524 525 common_init_isa_dma();
··· 474 #endif 475 } 476 477 static void 478 sable_lynx_mask_and_ack_irq(unsigned int irq) 479 { ··· 503 504 static struct irq_chip sable_lynx_irq_type = { 505 .name = "SABLE/LYNX", 506 + .unmask = sable_lynx_enable_irq, 507 + .mask = sable_lynx_disable_irq, 508 + .mask_ack = sable_lynx_mask_and_ack_irq, 509 }; 510 511 static void ··· 535 long i; 536 537 for (i = 0; i < nr_of_irqs; ++i) { 538 + irq_to_desc(i)->status |= IRQ_LEVEL; 539 + set_irq_chip_and_handler(i, &sable_lynx_irq_type, 540 + handle_level_irq); 541 } 542 543 common_init_isa_dma();
+5 -22
arch/alpha/kernel/sys_takara.c
··· 60 takara_update_irq_hw(irq, mask); 61 } 62 63 - static unsigned int 64 - takara_startup_irq(unsigned int irq) 65 - { 66 - takara_enable_irq(irq); 67 - return 0; /* never anything pending */ 68 - } 69 - 70 - static void 71 - takara_end_irq(unsigned int irq) 72 - { 73 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 74 - takara_enable_irq(irq); 75 - } 76 - 77 static struct irq_chip takara_irq_type = { 78 .name = "TAKARA", 79 - .startup = takara_startup_irq, 80 - .shutdown = takara_disable_irq, 81 - .enable = takara_enable_irq, 82 - .disable = takara_disable_irq, 83 - .ack = takara_disable_irq, 84 - .end = takara_end_irq, 85 }; 86 87 static void ··· 136 takara_update_irq_hw(i, -1); 137 138 for (i = 16; i < 128; ++i) { 139 - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 140 - irq_desc[i].chip = &takara_irq_type; 141 } 142 143 common_init_isa_dma();
··· 60 takara_update_irq_hw(irq, mask); 61 } 62 63 static struct irq_chip takara_irq_type = { 64 .name = "TAKARA", 65 + .unmask = takara_enable_irq, 66 + .mask = takara_disable_irq, 67 + .mask_ack = takara_disable_irq, 68 }; 69 70 static void ··· 153 takara_update_irq_hw(i, -1); 154 155 for (i = 16; i < 128; ++i) { 156 + irq_to_desc(i)->status |= IRQ_LEVEL; 157 + set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq); 158 } 159 160 common_init_isa_dma();
+7 -24
arch/alpha/kernel/sys_titan.c
··· 129 spin_unlock(&titan_irq_lock); 130 } 131 132 - static unsigned int 133 - titan_startup_irq(unsigned int irq) 134 - { 135 - titan_enable_irq(irq); 136 - return 0; /* never anything pending */ 137 - } 138 - 139 - static void 140 - titan_end_irq(unsigned int irq) 141 - { 142 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 143 - titan_enable_irq(irq); 144 - } 145 - 146 static void 147 titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) 148 { ··· 175 { 176 long i; 177 for (i = imin; i <= imax; ++i) { 178 - irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 179 - irq_desc[i].chip = ops; 180 } 181 } 182 183 static struct irq_chip titan_irq_type = { 184 - .name = "TITAN", 185 - .startup = titan_startup_irq, 186 - .shutdown = titan_disable_irq, 187 - .enable = titan_enable_irq, 188 - .disable = titan_disable_irq, 189 - .ack = titan_disable_irq, 190 - .end = titan_end_irq, 191 - .set_affinity = titan_set_irq_affinity, 192 }; 193 194 static irqreturn_t
··· 129 spin_unlock(&titan_irq_lock); 130 } 131 132 static void 133 titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) 134 { ··· 189 { 190 long i; 191 for (i = imin; i <= imax; ++i) { 192 + irq_to_desc(i)->status |= IRQ_LEVEL; 193 + set_irq_chip_and_handler(i, ops, handle_level_irq); 194 } 195 } 196 197 static struct irq_chip titan_irq_type = { 198 + .name = "TITAN", 199 + .unmask = titan_enable_irq, 200 + .mask = titan_disable_irq, 201 + .mask_ack = titan_disable_irq, 202 + .set_affinity = titan_set_irq_affinity, 203 }; 204 205 static irqreturn_t
+12 -30
arch/alpha/kernel/sys_wildfire.c
··· 139 spin_unlock(&wildfire_irq_lock); 140 } 141 142 - static unsigned int 143 - wildfire_startup_irq(unsigned int irq) 144 - { 145 - wildfire_enable_irq(irq); 146 - return 0; /* never anything pending */ 147 - } 148 - 149 - static void 150 - wildfire_end_irq(unsigned int irq) 151 - { 152 - #if 0 153 - if (!irq_desc[irq].action) 154 - printk("got irq %d\n", irq); 155 - #endif 156 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 157 - wildfire_enable_irq(irq); 158 - } 159 - 160 static struct irq_chip wildfire_irq_type = { 161 .name = "WILDFIRE", 162 - .startup = wildfire_startup_irq, 163 - .shutdown = wildfire_disable_irq, 164 - .enable = wildfire_enable_irq, 165 - .disable = wildfire_disable_irq, 166 - .ack = wildfire_mask_and_ack_irq, 167 - .end = wildfire_end_irq, 168 }; 169 170 static void __init ··· 177 for (i = 0; i < 16; ++i) { 178 if (i == 2) 179 continue; 180 - irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; 181 - irq_desc[i+irq_bias].chip = &wildfire_irq_type; 182 } 183 184 - irq_desc[36+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; 185 - irq_desc[36+irq_bias].chip = &wildfire_irq_type; 186 for (i = 40; i < 64; ++i) { 187 - irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL; 188 - irq_desc[i+irq_bias].chip = &wildfire_irq_type; 189 } 190 191 setup_irq(32+irq_bias, &isa_enable);
··· 139 spin_unlock(&wildfire_irq_lock); 140 } 141 142 static struct irq_chip wildfire_irq_type = { 143 .name = "WILDFIRE", 144 + .unmask = wildfire_enable_irq, 145 + .mask = wildfire_disable_irq, 146 + .mask_ack = wildfire_mask_and_ack_irq, 147 }; 148 149 static void __init ··· 198 for (i = 0; i < 16; ++i) { 199 if (i == 2) 200 continue; 201 + irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL; 202 + set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type, 203 + handle_level_irq); 204 } 205 206 + irq_to_desc(36+irq_bias)->status |= IRQ_LEVEL; 207 + set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type, 208 + handle_level_irq); 209 for (i = 40; i < 64; ++i) { 210 + irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL; 211 + set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type, 212 + handle_level_irq); 213 } 214 215 setup_irq(32+irq_bias, &isa_enable);
+2 -2
arch/alpha/lib/Makefile
··· 2 # Makefile for alpha-specific library files.. 3 # 4 5 - EXTRA_AFLAGS := $(KBUILD_CFLAGS) 6 - EXTRA_CFLAGS := -Werror 7 8 # Many of these routines have implementations tuned for ev6. 9 # Choose them iff we're targeting ev6 specifically.
··· 2 # Makefile for alpha-specific library files.. 3 # 4 5 + asflags-y := $(KBUILD_CFLAGS) 6 + ccflags-y := -Werror 7 8 # Many of these routines have implementations tuned for ev6. 9 # Choose them iff we're targeting ev6 specifically.
+1 -1
arch/alpha/math-emu/Makefile
··· 2 # Makefile for the FPU instruction emulation. 3 # 4 5 - EXTRA_CFLAGS := -w 6 7 obj-$(CONFIG_MATHEMU) += math-emu.o 8
··· 2 # Makefile for the FPU instruction emulation. 3 # 4 5 + ccflags-y := -w 6 7 obj-$(CONFIG_MATHEMU) += math-emu.o 8
+1 -1
arch/alpha/mm/Makefile
··· 2 # Makefile for the linux alpha-specific parts of the memory manager. 3 # 4 5 - EXTRA_CFLAGS := -Werror 6 7 obj-y := init.o fault.o extable.o 8
··· 2 # Makefile for the linux alpha-specific parts of the memory manager. 3 # 4 5 + ccflags-y := -Werror 6 7 obj-y := init.o fault.o extable.o 8
+1 -1
arch/alpha/oprofile/Makefile
··· 1 - EXTRA_CFLAGS := -Werror -Wno-sign-compare 2 3 obj-$(CONFIG_OPROFILE) += oprofile.o 4
··· 1 + ccflags-y := -Werror -Wno-sign-compare 2 3 obj-$(CONFIG_OPROFILE) += oprofile.o 4