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kernel os linux

net: stmmac: sunxi platform extensions for GMAC in Allwinner A20 SoC's

The Allwinner A20 has an ethernet controller that seems to be
an early version of Synopsys DesignWare MAC 10/100/1000 Universal,
which is supported by the stmmac driver.

Allwinner's GMAC requires setting additional registers in the SoC's
clock control unit.

The exact version of the DWMAC IP that Allwinner uses is unknown,
thus the exact feature set is unknown.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Chen-Yu Tsai and committed by
David S. Miller
af0bd4e9 022066f5

+185
+27
Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt
··· 1 + * Allwinner GMAC ethernet controller 2 + 3 + This device is a platform glue layer for stmmac. 4 + Please see stmmac.txt for the other unchanged properties. 5 + 6 + Required properties: 7 + - compatible: Should be "allwinner,sun7i-a20-gmac" 8 + - clocks: Should contain the GMAC main clock, and tx clock 9 + The tx clock type should be "allwinner,sun7i-a20-gmac-clk" 10 + - clock-names: Should contain the clock names "stmmaceth", 11 + and "allwinner_gmac_tx" 12 + 13 + Optional properties: 14 + - phy-supply: phandle to a regulator if the PHY needs one 15 + 16 + Examples: 17 + 18 + gmac: ethernet@01c50000 { 19 + compatible = "allwinner,sun7i-a20-gmac"; 20 + reg = <0x01c50000 0x10000>, 21 + <0x01c20164 0x4>; 22 + interrupts = <0 85 1>; 23 + interrupt-names = "macirq"; 24 + clocks = <&ahb_gates 49>, <&gmac_tx>; 25 + clock-names = "stmmaceth", "allwinner_gmac_tx"; 26 + phy-mode = "mii"; 27 + };
+11
drivers/net/ethernet/stmicro/stmmac/Kconfig
··· 26 26 27 27 If unsure, say N. 28 28 29 + config DWMAC_SUNXI 30 + bool "Allwinner GMAC support" 31 + depends on STMMAC_PLATFORM && ARCH_SUNXI 32 + default y 33 + ---help--- 34 + Support for Allwinner A20/A31 GMAC ethernet controllers. 35 + 36 + This selects Allwinner SoC glue layer support for the 37 + stmmac device driver. This driver is used for A20/A31 38 + GMAC ethernet controller. 39 + 29 40 config STMMAC_PCI 30 41 bool "STMMAC PCI bus support" 31 42 depends on STMMAC_ETH && PCI
+1
drivers/net/ethernet/stmicro/stmmac/Makefile
··· 1 1 obj-$(CONFIG_STMMAC_ETH) += stmmac.o 2 2 stmmac-$(CONFIG_STMMAC_PLATFORM) += stmmac_platform.o 3 3 stmmac-$(CONFIG_STMMAC_PCI) += stmmac_pci.o 4 + stmmac-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o 4 5 stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \ 5 6 chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \ 6 7 dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
+140
drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
··· 1 + /** 2 + * dwmac-sunxi.c - Allwinner sunxi DWMAC specific glue layer 3 + * 4 + * Copyright (C) 2013 Chen-Yu Tsai 5 + * 6 + * Chen-Yu Tsai <wens@csie.org> 7 + * 8 + * This program is free software; you can redistribute it and/or modify 9 + * it under the terms of the GNU General Public License as published by 10 + * the Free Software Foundation; either version 2 of the License, or 11 + * (at your option) any later version. 12 + * 13 + * This program is distributed in the hope that it will be useful, 14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 + * GNU General Public License for more details. 17 + */ 18 + 19 + #include <linux/stmmac.h> 20 + #include <linux/clk.h> 21 + #include <linux/phy.h> 22 + #include <linux/of_net.h> 23 + #include <linux/regulator/consumer.h> 24 + 25 + struct sunxi_priv_data { 26 + int interface; 27 + int clk_enabled; 28 + struct clk *tx_clk; 29 + struct regulator *regulator; 30 + }; 31 + 32 + static void *sun7i_gmac_setup(struct platform_device *pdev) 33 + { 34 + struct sunxi_priv_data *gmac; 35 + struct device *dev = &pdev->dev; 36 + 37 + gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 38 + if (!gmac) 39 + return ERR_PTR(-ENOMEM); 40 + 41 + gmac->interface = of_get_phy_mode(dev->of_node); 42 + 43 + gmac->tx_clk = devm_clk_get(dev, "allwinner_gmac_tx"); 44 + if (IS_ERR(gmac->tx_clk)) { 45 + dev_err(dev, "could not get tx clock\n"); 46 + return gmac->tx_clk; 47 + } 48 + 49 + /* Optional regulator for PHY */ 50 + gmac->regulator = devm_regulator_get_optional(dev, "phy"); 51 + if (IS_ERR(gmac->regulator)) { 52 + if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) 53 + return ERR_PTR(-EPROBE_DEFER); 54 + dev_info(dev, "no regulator found\n"); 55 + gmac->regulator = NULL; 56 + } 57 + 58 + return gmac; 59 + } 60 + 61 + #define SUN7I_GMAC_GMII_RGMII_RATE 125000000 62 + #define SUN7I_GMAC_MII_RATE 25000000 63 + 64 + static int sun7i_gmac_init(struct platform_device *pdev, void *priv) 65 + { 66 + struct sunxi_priv_data *gmac = priv; 67 + int ret; 68 + 69 + if (gmac->regulator) { 70 + ret = regulator_enable(gmac->regulator); 71 + if (ret) 72 + return ret; 73 + } 74 + 75 + /* Set GMAC interface port mode 76 + * 77 + * The GMAC TX clock lines are configured by setting the clock 78 + * rate, which then uses the auto-reparenting feature of the 79 + * clock driver, and enabling/disabling the clock. 80 + */ 81 + if (gmac->interface == PHY_INTERFACE_MODE_RGMII) { 82 + clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); 83 + clk_prepare_enable(gmac->tx_clk); 84 + gmac->clk_enabled = 1; 85 + } else { 86 + clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE); 87 + clk_prepare(gmac->tx_clk); 88 + } 89 + 90 + return 0; 91 + } 92 + 93 + static void sun7i_gmac_exit(struct platform_device *pdev, void *priv) 94 + { 95 + struct sunxi_priv_data *gmac = priv; 96 + 97 + if (gmac->clk_enabled) { 98 + clk_disable(gmac->tx_clk); 99 + gmac->clk_enabled = 0; 100 + } 101 + clk_unprepare(gmac->tx_clk); 102 + 103 + if (gmac->regulator) 104 + regulator_disable(gmac->regulator); 105 + } 106 + 107 + static void sun7i_fix_speed(void *priv, unsigned int speed) 108 + { 109 + struct sunxi_priv_data *gmac = priv; 110 + 111 + /* only GMII mode requires us to reconfigure the clock lines */ 112 + if (gmac->interface != PHY_INTERFACE_MODE_GMII) 113 + return; 114 + 115 + if (gmac->clk_enabled) { 116 + clk_disable(gmac->tx_clk); 117 + gmac->clk_enabled = 0; 118 + } 119 + clk_unprepare(gmac->tx_clk); 120 + 121 + if (speed == 1000) { 122 + clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); 123 + clk_prepare_enable(gmac->tx_clk); 124 + gmac->clk_enabled = 1; 125 + } else { 126 + clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE); 127 + clk_prepare(gmac->tx_clk); 128 + } 129 + } 130 + 131 + /* of_data specifying hardware features and callbacks. 132 + * hardware features were copied from Allwinner drivers. */ 133 + const struct stmmac_of_data sun7i_gmac_data = { 134 + .has_gmac = 1, 135 + .tx_coe = 1, 136 + .fix_mac_speed = sun7i_fix_speed, 137 + .setup = sun7i_gmac_setup, 138 + .init = sun7i_gmac_init, 139 + .exit = sun7i_gmac_exit, 140 + };
+3
drivers/net/ethernet/stmicro/stmmac/stmmac.h
··· 130 130 bool stmmac_eee_init(struct stmmac_priv *priv); 131 131 132 132 #ifdef CONFIG_STMMAC_PLATFORM 133 + #ifdef CONFIG_DWMAC_SUNXI 134 + extern const struct stmmac_of_data sun7i_gmac_data; 135 + #endif 133 136 extern struct platform_driver stmmac_pltfr_driver; 134 137 static inline int stmmac_register_platform(void) 135 138 {
+3
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
··· 30 30 #include "stmmac.h" 31 31 32 32 static const struct of_device_id stmmac_dt_ids[] = { 33 + #ifdef CONFIG_DWMAC_SUNXI 34 + { .compatible = "allwinner,sun7i-a20-gmac", .data = &sun7i_gmac_data}, 35 + #endif 33 36 /* SoC specific glue layers should come before generic bindings */ 34 37 { .compatible = "st,spear600-gmac"}, 35 38 { .compatible = "snps,dwmac-3.610"},