Merge tag 'reset-for-v6.19' of https://git.pengutronix.de/git/pza/linux into soc/drivers

+42

Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/reset/eswin,eic7700-reset.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: ESWIN EIC7700 SoC reset controller 8 + 9 + maintainers: 10 + - Yifeng Huang <huangyifeng@eswincomputing.com> 11 + - Xuyang Dong <dongxuyang@eswincomputing.com> 12 + 13 + description: 14 + The system reset controller can be used to reset various peripheral 15 + controllers in ESWIN eic7700 SoC. 16 + 17 + properties: 18 + compatible: 19 + const: eswin,eic7700-reset 20 + 21 + reg: 22 + maxItems: 1 23 + 24 + '#reset-cells': 25 + const: 1 26 + 27 + required: 28 + - compatible 29 + - reg 30 + - '#reset-cells' 31 + 32 + additionalProperties: false 33 + 34 + examples: 35 + - | 36 + #include <dt-bindings/reset/eswin,eic7700-reset.h> 37 + 38 + reset-controller@51828300 { 39 + compatible = "eswin,eic7700-reset"; 40 + reg = <0x51828300 0x200>; 41 + #reset-cells = <1>; 42 + };

+8 -3

Documentation/devicetree/bindings/reset/microchip,rst.yaml

··· 20 20 pattern: "^reset-controller@[0-9a-f]+$" 21 21 22 22 compatible: 23 - enum: 24 - - microchip,sparx5-switch-reset 25 - - microchip,lan966x-switch-reset 23 + oneOf: 24 + - enum: 25 + - microchip,sparx5-switch-reset 26 + - microchip,lan966x-switch-reset 27 + - items: 28 + - enum: 29 + - microchip,lan9691-switch-reset 30 + - const: microchip,lan966x-switch-reset 26 31 27 32 reg: 28 33 items:

+35 -6

Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml

··· 15 15 16 16 properties: 17 17 compatible: 18 - items: 19 - - enum: 20 - - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five 21 - - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} 22 - - renesas,r9a07g054-usbphy-ctrl # RZ/V2L 23 - - const: renesas,rzg2l-usbphy-ctrl 18 + oneOf: 19 + - items: 20 + - enum: 21 + - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five 22 + - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} 23 + - renesas,r9a07g054-usbphy-ctrl # RZ/V2L 24 + - const: renesas,rzg2l-usbphy-ctrl 25 + - const: renesas,r9a08g045-usbphy-ctrl # RZ/G3S 24 26 25 27 reg: 26 28 maxItems: 1 ··· 50 48 $ref: /schemas/regulator/regulator.yaml# 51 49 unevaluatedProperties: false 52 50 51 + renesas,sysc-pwrrdy: 52 + description: 53 + The system controller PWRRDY indicates to the USB PHY if the power supply 54 + is ready. PWRRDY needs to be set during power-on before applying any 55 + other settings. It also needs to be set before powering off the USB. 56 + $ref: /schemas/types.yaml#/definitions/phandle-array 57 + items: 58 + - items: 59 + - description: 60 + System controller phandle required by USB PHY CTRL driver to set 61 + PWRRDY 62 + - description: Register offset associated with PWRRDY 63 + - description: Register bitmask associated with PWRRDY 64 + 53 65 required: 54 66 - compatible 55 67 - reg ··· 72 56 - power-domains 73 57 - '#reset-cells' 74 58 - regulator-vbus 59 + 60 + allOf: 61 + - if: 62 + properties: 63 + compatible: 64 + contains: 65 + const: renesas,r9a08g045-usbphy-ctrl 66 + then: 67 + required: 68 + - renesas,sysc-pwrrdy 69 + else: 70 + properties: 71 + renesas,sysc-pwrrdy: false 75 72 76 73 additionalProperties: false 77 74

+7 -1

Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml

··· 16 16 properties: 17 17 compatible: 18 18 enum: 19 - - thead,th1520-reset 19 + - thead,th1520-reset # Reset controller for VO subsystem 20 + - thead,th1520-reset-ao 21 + - thead,th1520-reset-ap 22 + - thead,th1520-reset-dsp 23 + - thead,th1520-reset-misc 24 + - thead,th1520-reset-vi 25 + - thead,th1520-reset-vp 20 26 21 27 reg: 22 28 maxItems: 1

-1

Documentation/driver-api/reset.rst

··· 218 218 reset_controller_register 219 219 reset_controller_unregister 220 220 devm_reset_controller_register 221 - reset_controller_add_lookup

-7

drivers/clk/davinci/psc-da850.c

··· 6 6 */ 7 7 8 8 #include <linux/clk-provider.h> 9 - #include <linux/reset-controller.h> 10 9 #include <linux/clk.h> 11 10 #include <linux/clkdev.h> 12 11 #include <linux/init.h> ··· 65 66 "fck", "ecap.1", 66 67 "fck", "ecap.2"); 67 68 68 - static struct reset_control_lookup da850_psc0_reset_lookup_table[] = { 69 - RESET_LOOKUP("da850-psc0", 15, "davinci-rproc.0", NULL), 70 - }; 71 - 72 69 static int da850_psc0_init(struct device *dev, void __iomem *base) 73 70 { 74 - reset_controller_add_lookup(da850_psc0_reset_lookup_table, 75 - ARRAY_SIZE(da850_psc0_reset_lookup_table)); 76 71 return davinci_psc_register_clocks(dev, da850_psc0_info, 16, base); 77 72 } 78 73

+12 -1

drivers/reset/Kconfig

··· 73 73 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 74 74 BCM7216 or the BCM2712. 75 75 76 + config RESET_EIC7700 77 + bool "Reset controller driver for ESWIN SoCs" 78 + depends on ARCH_ESWIN || COMPILE_TEST 79 + default ARCH_ESWIN 80 + help 81 + This enables the reset controller driver for ESWIN SoCs. This driver is 82 + specific to ESWIN SoCs and should only be enabled if using such hardware. 83 + The driver supports eic7700 series chips and provides functionality for 84 + asserting and deasserting resets on the chip. 85 + 76 86 config RESET_EYEQ 77 87 bool "Mobileye EyeQ reset controller" 78 88 depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST ··· 180 170 181 171 config RESET_MCHP_SPARX5 182 172 tristate "Microchip Sparx5 reset driver" 183 - depends on ARCH_SPARX5 || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST 173 + depends on ARCH_SPARX5 || ARCH_LAN969X || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST 184 174 default y if SPARX5_SWITCH 185 175 select MFD_SYSCON 186 176 help ··· 247 237 config RESET_RZG2L_USBPHY_CTRL 248 238 tristate "Renesas RZ/G2L USBPHY control driver" 249 239 depends on ARCH_RZG2L || COMPILE_TEST 240 + select MFD_SYSCON 250 241 help 251 242 Support for USBPHY Control found on RZ/G2L family. It mainly 252 243 controls reset and power down of the USB/PHY.

+1

drivers/reset/Makefile

··· 13 13 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o 14 14 obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o 15 15 obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o 16 + obj-$(CONFIG_RESET_EIC7700) += reset-eic7700.o 16 17 obj-$(CONFIG_RESET_EYEQ) += reset-eyeq.o 17 18 obj-$(CONFIG_RESET_GPIO) += reset-gpio.o 18 19 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o

+3 -121

drivers/reset/core.c

··· 25 25 static DEFINE_MUTEX(reset_list_mutex); 26 26 static LIST_HEAD(reset_controller_list); 27 27 28 - static DEFINE_MUTEX(reset_lookup_mutex); 29 - static LIST_HEAD(reset_lookup_list); 30 - 31 28 /* Protects reset_gpio_lookup_list */ 32 29 static DEFINE_MUTEX(reset_gpio_lookup_mutex); 33 30 static LIST_HEAD(reset_gpio_lookup_list); ··· 186 189 return ret; 187 190 } 188 191 EXPORT_SYMBOL_GPL(devm_reset_controller_register); 189 - 190 - /** 191 - * reset_controller_add_lookup - register a set of lookup entries 192 - * @lookup: array of reset lookup entries 193 - * @num_entries: number of entries in the lookup array 194 - */ 195 - void reset_controller_add_lookup(struct reset_control_lookup *lookup, 196 - unsigned int num_entries) 197 - { 198 - struct reset_control_lookup *entry; 199 - unsigned int i; 200 - 201 - mutex_lock(&reset_lookup_mutex); 202 - for (i = 0; i < num_entries; i++) { 203 - entry = &lookup[i]; 204 - 205 - if (!entry->dev_id || !entry->provider) { 206 - pr_warn("%s(): reset lookup entry badly specified, skipping\n", 207 - __func__); 208 - continue; 209 - } 210 - 211 - list_add_tail(&entry->list, &reset_lookup_list); 212 - } 213 - mutex_unlock(&reset_lookup_mutex); 214 - } 215 - EXPORT_SYMBOL_GPL(reset_controller_add_lookup); 216 192 217 193 static inline struct reset_control_array * 218 194 rstc_to_array(struct reset_control *rstc) { ··· 1051 1081 } 1052 1082 EXPORT_SYMBOL_GPL(__of_reset_control_get); 1053 1083 1054 - static struct reset_controller_dev * 1055 - __reset_controller_by_name(const char *name) 1056 - { 1057 - struct reset_controller_dev *rcdev; 1058 - 1059 - lockdep_assert_held(&reset_list_mutex); 1060 - 1061 - list_for_each_entry(rcdev, &reset_controller_list, list) { 1062 - if (!rcdev->dev) 1063 - continue; 1064 - 1065 - if (!strcmp(name, dev_name(rcdev->dev))) 1066 - return rcdev; 1067 - } 1068 - 1069 - return NULL; 1070 - } 1071 - 1072 - static struct reset_control * 1073 - __reset_control_get_from_lookup(struct device *dev, const char *con_id, 1074 - enum reset_control_flags flags) 1075 - { 1076 - bool optional = flags & RESET_CONTROL_FLAGS_BIT_OPTIONAL; 1077 - const struct reset_control_lookup *lookup; 1078 - struct reset_controller_dev *rcdev; 1079 - const char *dev_id = dev_name(dev); 1080 - struct reset_control *rstc = NULL; 1081 - 1082 - mutex_lock(&reset_lookup_mutex); 1083 - 1084 - list_for_each_entry(lookup, &reset_lookup_list, list) { 1085 - if (strcmp(lookup->dev_id, dev_id)) 1086 - continue; 1087 - 1088 - if ((!con_id && !lookup->con_id) || 1089 - ((con_id && lookup->con_id) && 1090 - !strcmp(con_id, lookup->con_id))) { 1091 - mutex_lock(&reset_list_mutex); 1092 - rcdev = __reset_controller_by_name(lookup->provider); 1093 - if (!rcdev) { 1094 - mutex_unlock(&reset_list_mutex); 1095 - mutex_unlock(&reset_lookup_mutex); 1096 - /* Reset provider may not be ready yet. */ 1097 - return ERR_PTR(-EPROBE_DEFER); 1098 - } 1099 - 1100 - flags &= ~RESET_CONTROL_FLAGS_BIT_OPTIONAL; 1101 - 1102 - rstc = __reset_control_get_internal(rcdev, 1103 - lookup->index, 1104 - flags); 1105 - mutex_unlock(&reset_list_mutex); 1106 - break; 1107 - } 1108 - } 1109 - 1110 - mutex_unlock(&reset_lookup_mutex); 1111 - 1112 - if (!rstc) 1113 - return optional ? NULL : ERR_PTR(-ENOENT); 1114 - 1115 - return rstc; 1116 - } 1117 - 1118 1084 struct reset_control *__reset_control_get(struct device *dev, const char *id, 1119 1085 int index, enum reset_control_flags flags) 1120 1086 { 1121 1087 bool shared = flags & RESET_CONTROL_FLAGS_BIT_SHARED; 1122 1088 bool acquired = flags & RESET_CONTROL_FLAGS_BIT_ACQUIRED; 1089 + bool optional = flags & RESET_CONTROL_FLAGS_BIT_OPTIONAL; 1123 1090 1124 1091 if (WARN_ON(shared && acquired)) 1125 1092 return ERR_PTR(-EINVAL); ··· 1064 1157 if (dev->of_node) 1065 1158 return __of_reset_control_get(dev->of_node, id, index, flags); 1066 1159 1067 - return __reset_control_get_from_lookup(dev, id, flags); 1160 + return optional ? NULL : ERR_PTR(-ENOENT); 1068 1161 } 1069 1162 EXPORT_SYMBOL_GPL(__reset_control_get); 1070 1163 ··· 1399 1492 } 1400 1493 EXPORT_SYMBOL_GPL(devm_reset_control_array_get); 1401 1494 1402 - static int reset_control_get_count_from_lookup(struct device *dev) 1403 - { 1404 - const struct reset_control_lookup *lookup; 1405 - const char *dev_id; 1406 - int count = 0; 1407 - 1408 - if (!dev) 1409 - return -EINVAL; 1410 - 1411 - dev_id = dev_name(dev); 1412 - mutex_lock(&reset_lookup_mutex); 1413 - 1414 - list_for_each_entry(lookup, &reset_lookup_list, list) { 1415 - if (!strcmp(lookup->dev_id, dev_id)) 1416 - count++; 1417 - } 1418 - 1419 - mutex_unlock(&reset_lookup_mutex); 1420 - 1421 - if (count == 0) 1422 - count = -ENOENT; 1423 - 1424 - return count; 1425 - } 1426 - 1427 1495 /** 1428 1496 * reset_control_get_count - Count number of resets available with a device 1429 1497 * ··· 1412 1530 if (dev->of_node) 1413 1531 return of_reset_control_get_count(dev->of_node); 1414 1532 1415 - return reset_control_get_count_from_lookup(dev); 1533 + return -ENOENT; 1416 1534 } 1417 1535 EXPORT_SYMBOL_GPL(reset_control_get_count);

+429

drivers/reset/reset-eic7700.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. 4 + * All rights reserved. 5 + * 6 + * ESWIN Reset Driver 7 + * 8 + * Authors: 9 + * Yifeng Huang <huangyifeng@eswincomputing.com> 10 + * Xuyang Dong <dongxuyang@eswincomputing.com> 11 + */ 12 + 13 + #include <linux/err.h> 14 + #include <linux/init.h> 15 + #include <linux/of.h> 16 + #include <linux/platform_device.h> 17 + #include <linux/regmap.h> 18 + #include <linux/reset-controller.h> 19 + #include <linux/slab.h> 20 + #include <linux/types.h> 21 + 22 + #include <dt-bindings/reset/eswin,eic7700-reset.h> 23 + 24 + #define SYSCRG_CLEAR_BOOT_INFO_OFFSET 0xC 25 + #define CLEAR_BOOT_FLAG_BIT BIT(0) 26 + #define SYSCRG_RESET_OFFSET 0x100 27 + 28 + /** 29 + * struct eic7700_reset_data - reset controller information structure 30 + * @rcdev: reset controller entity 31 + * @regmap: regmap handle containing the memory-mapped reset registers 32 + */ 33 + struct eic7700_reset_data { 34 + struct reset_controller_dev rcdev; 35 + struct regmap *regmap; 36 + }; 37 + 38 + static const struct regmap_config eic7700_regmap_config = { 39 + .reg_bits = 32, 40 + .val_bits = 32, 41 + .reg_stride = 4, 42 + .max_register = 0x1fc, 43 + }; 44 + 45 + struct eic7700_reg { 46 + u32 reg; 47 + u32 bit; 48 + }; 49 + 50 + static inline struct eic7700_reset_data * 51 + to_eic7700_reset_data(struct reset_controller_dev *rcdev) 52 + { 53 + return container_of(rcdev, struct eic7700_reset_data, rcdev); 54 + } 55 + 56 + #define EIC7700_RESET(id, reg, bit)[id] = \ 57 + { SYSCRG_RESET_OFFSET + (reg) * sizeof(u32), BIT(bit) } 58 + 59 + /* mapping table for reset ID to register offset and reset bit */ 60 + static const struct eic7700_reg eic7700_reset[] = { 61 + EIC7700_RESET(EIC7700_RESET_NOC_NSP, 0, 0), 62 + EIC7700_RESET(EIC7700_RESET_NOC_CFG, 0, 1), 63 + EIC7700_RESET(EIC7700_RESET_RNOC_NSP, 0, 2), 64 + EIC7700_RESET(EIC7700_RESET_SNOC_TCU, 0, 3), 65 + EIC7700_RESET(EIC7700_RESET_SNOC_U84, 0, 4), 66 + EIC7700_RESET(EIC7700_RESET_SNOC_PCIE_XSR, 0, 5), 67 + EIC7700_RESET(EIC7700_RESET_SNOC_PCIE_XMR, 0, 6), 68 + EIC7700_RESET(EIC7700_RESET_SNOC_PCIE_PR, 0, 7), 69 + EIC7700_RESET(EIC7700_RESET_SNOC_NPU, 0, 8), 70 + EIC7700_RESET(EIC7700_RESET_SNOC_JTAG, 0, 9), 71 + EIC7700_RESET(EIC7700_RESET_SNOC_DSP, 0, 10), 72 + EIC7700_RESET(EIC7700_RESET_SNOC_DDRC1_P2, 0, 11), 73 + EIC7700_RESET(EIC7700_RESET_SNOC_DDRC1_P1, 0, 12), 74 + EIC7700_RESET(EIC7700_RESET_SNOC_DDRC0_P2, 0, 13), 75 + EIC7700_RESET(EIC7700_RESET_SNOC_DDRC0_P1, 0, 14), 76 + EIC7700_RESET(EIC7700_RESET_SNOC_D2D, 0, 15), 77 + EIC7700_RESET(EIC7700_RESET_SNOC_AON, 0, 16), 78 + EIC7700_RESET(EIC7700_RESET_GPU_AXI, 1, 0), 79 + EIC7700_RESET(EIC7700_RESET_GPU_CFG, 1, 1), 80 + EIC7700_RESET(EIC7700_RESET_GPU_GRAY, 1, 2), 81 + EIC7700_RESET(EIC7700_RESET_GPU_JONES, 1, 3), 82 + EIC7700_RESET(EIC7700_RESET_GPU_SPU, 1, 4), 83 + EIC7700_RESET(EIC7700_RESET_DSP_AXI, 2, 0), 84 + EIC7700_RESET(EIC7700_RESET_DSP_CFG, 2, 1), 85 + EIC7700_RESET(EIC7700_RESET_DSP_DIV4, 2, 2), 86 + EIC7700_RESET(EIC7700_RESET_DSP_DIV0, 2, 4), 87 + EIC7700_RESET(EIC7700_RESET_DSP_DIV1, 2, 5), 88 + EIC7700_RESET(EIC7700_RESET_DSP_DIV2, 2, 6), 89 + EIC7700_RESET(EIC7700_RESET_DSP_DIV3, 2, 7), 90 + EIC7700_RESET(EIC7700_RESET_D2D_AXI, 3, 0), 91 + EIC7700_RESET(EIC7700_RESET_D2D_CFG, 3, 1), 92 + EIC7700_RESET(EIC7700_RESET_D2D_PRST, 3, 2), 93 + EIC7700_RESET(EIC7700_RESET_D2D_RAW_PCS, 3, 4), 94 + EIC7700_RESET(EIC7700_RESET_D2D_RX, 3, 5), 95 + EIC7700_RESET(EIC7700_RESET_D2D_TX, 3, 6), 96 + EIC7700_RESET(EIC7700_RESET_D2D_CORE, 3, 7), 97 + EIC7700_RESET(EIC7700_RESET_DDR1_ARST, 4, 0), 98 + EIC7700_RESET(EIC7700_RESET_DDR1_TRACE, 4, 6), 99 + EIC7700_RESET(EIC7700_RESET_DDR0_ARST, 4, 16), 100 + EIC7700_RESET(EIC7700_RESET_DDR_CFG, 4, 21), 101 + EIC7700_RESET(EIC7700_RESET_DDR0_TRACE, 4, 22), 102 + EIC7700_RESET(EIC7700_RESET_DDR_CORE, 4, 23), 103 + EIC7700_RESET(EIC7700_RESET_DDR_PRST, 4, 26), 104 + EIC7700_RESET(EIC7700_RESET_TCU_AXI, 5, 0), 105 + EIC7700_RESET(EIC7700_RESET_TCU_CFG, 5, 1), 106 + EIC7700_RESET(EIC7700_RESET_TCU_TBU0, 5, 4), 107 + EIC7700_RESET(EIC7700_RESET_TCU_TBU1, 5, 5), 108 + EIC7700_RESET(EIC7700_RESET_TCU_TBU2, 5, 6), 109 + EIC7700_RESET(EIC7700_RESET_TCU_TBU3, 5, 7), 110 + EIC7700_RESET(EIC7700_RESET_TCU_TBU4, 5, 8), 111 + EIC7700_RESET(EIC7700_RESET_TCU_TBU5, 5, 9), 112 + EIC7700_RESET(EIC7700_RESET_TCU_TBU6, 5, 10), 113 + EIC7700_RESET(EIC7700_RESET_TCU_TBU7, 5, 11), 114 + EIC7700_RESET(EIC7700_RESET_TCU_TBU8, 5, 12), 115 + EIC7700_RESET(EIC7700_RESET_TCU_TBU9, 5, 13), 116 + EIC7700_RESET(EIC7700_RESET_TCU_TBU10, 5, 14), 117 + EIC7700_RESET(EIC7700_RESET_TCU_TBU11, 5, 15), 118 + EIC7700_RESET(EIC7700_RESET_TCU_TBU12, 5, 16), 119 + EIC7700_RESET(EIC7700_RESET_TCU_TBU13, 5, 17), 120 + EIC7700_RESET(EIC7700_RESET_TCU_TBU14, 5, 18), 121 + EIC7700_RESET(EIC7700_RESET_TCU_TBU15, 5, 19), 122 + EIC7700_RESET(EIC7700_RESET_TCU_TBU16, 5, 20), 123 + EIC7700_RESET(EIC7700_RESET_NPU_AXI, 6, 0), 124 + EIC7700_RESET(EIC7700_RESET_NPU_CFG, 6, 1), 125 + EIC7700_RESET(EIC7700_RESET_NPU_CORE, 6, 2), 126 + EIC7700_RESET(EIC7700_RESET_NPU_E31CORE, 6, 3), 127 + EIC7700_RESET(EIC7700_RESET_NPU_E31BUS, 6, 4), 128 + EIC7700_RESET(EIC7700_RESET_NPU_E31DBG, 6, 5), 129 + EIC7700_RESET(EIC7700_RESET_NPU_LLC, 6, 6), 130 + EIC7700_RESET(EIC7700_RESET_HSP_AXI, 7, 0), 131 + EIC7700_RESET(EIC7700_RESET_HSP_CFG, 7, 1), 132 + EIC7700_RESET(EIC7700_RESET_HSP_POR, 7, 2), 133 + EIC7700_RESET(EIC7700_RESET_MSHC0_PHY, 7, 3), 134 + EIC7700_RESET(EIC7700_RESET_MSHC1_PHY, 7, 4), 135 + EIC7700_RESET(EIC7700_RESET_MSHC2_PHY, 7, 5), 136 + EIC7700_RESET(EIC7700_RESET_MSHC0_TXRX, 7, 6), 137 + EIC7700_RESET(EIC7700_RESET_MSHC1_TXRX, 7, 7), 138 + EIC7700_RESET(EIC7700_RESET_MSHC2_TXRX, 7, 8), 139 + EIC7700_RESET(EIC7700_RESET_SATA_ASIC0, 7, 9), 140 + EIC7700_RESET(EIC7700_RESET_SATA_OOB, 7, 10), 141 + EIC7700_RESET(EIC7700_RESET_SATA_PMALIVE, 7, 11), 142 + EIC7700_RESET(EIC7700_RESET_SATA_RBC, 7, 12), 143 + EIC7700_RESET(EIC7700_RESET_DMA0, 7, 13), 144 + EIC7700_RESET(EIC7700_RESET_HSP_DMA, 7, 14), 145 + EIC7700_RESET(EIC7700_RESET_USB0_VAUX, 7, 15), 146 + EIC7700_RESET(EIC7700_RESET_USB1_VAUX, 7, 16), 147 + EIC7700_RESET(EIC7700_RESET_HSP_SD1_PRST, 7, 17), 148 + EIC7700_RESET(EIC7700_RESET_HSP_SD0_PRST, 7, 18), 149 + EIC7700_RESET(EIC7700_RESET_HSP_EMMC_PRST, 7, 19), 150 + EIC7700_RESET(EIC7700_RESET_HSP_DMA_PRST, 7, 20), 151 + EIC7700_RESET(EIC7700_RESET_HSP_SD1_ARST, 7, 21), 152 + EIC7700_RESET(EIC7700_RESET_HSP_SD0_ARST, 7, 22), 153 + EIC7700_RESET(EIC7700_RESET_HSP_EMMC_ARST, 7, 23), 154 + EIC7700_RESET(EIC7700_RESET_HSP_DMA_ARST, 7, 24), 155 + EIC7700_RESET(EIC7700_RESET_HSP_ETH1_ARST, 7, 25), 156 + EIC7700_RESET(EIC7700_RESET_HSP_ETH0_ARST, 7, 26), 157 + EIC7700_RESET(EIC7700_RESET_SATA_ARST, 7, 27), 158 + EIC7700_RESET(EIC7700_RESET_PCIE_CFG, 8, 0), 159 + EIC7700_RESET(EIC7700_RESET_PCIE_POWEUP, 8, 1), 160 + EIC7700_RESET(EIC7700_RESET_PCIE_PERST, 8, 2), 161 + EIC7700_RESET(EIC7700_RESET_I2C0, 9, 0), 162 + EIC7700_RESET(EIC7700_RESET_I2C1, 9, 1), 163 + EIC7700_RESET(EIC7700_RESET_I2C2, 9, 2), 164 + EIC7700_RESET(EIC7700_RESET_I2C3, 9, 3), 165 + EIC7700_RESET(EIC7700_RESET_I2C4, 9, 4), 166 + EIC7700_RESET(EIC7700_RESET_I2C5, 9, 5), 167 + EIC7700_RESET(EIC7700_RESET_I2C6, 9, 6), 168 + EIC7700_RESET(EIC7700_RESET_I2C7, 9, 7), 169 + EIC7700_RESET(EIC7700_RESET_I2C8, 9, 8), 170 + EIC7700_RESET(EIC7700_RESET_I2C9, 9, 9), 171 + EIC7700_RESET(EIC7700_RESET_FAN, 10, 0), 172 + EIC7700_RESET(EIC7700_RESET_PVT0, 11, 0), 173 + EIC7700_RESET(EIC7700_RESET_PVT1, 11, 1), 174 + EIC7700_RESET(EIC7700_RESET_MBOX0, 12, 0), 175 + EIC7700_RESET(EIC7700_RESET_MBOX1, 12, 1), 176 + EIC7700_RESET(EIC7700_RESET_MBOX2, 12, 2), 177 + EIC7700_RESET(EIC7700_RESET_MBOX3, 12, 3), 178 + EIC7700_RESET(EIC7700_RESET_MBOX4, 12, 4), 179 + EIC7700_RESET(EIC7700_RESET_MBOX5, 12, 5), 180 + EIC7700_RESET(EIC7700_RESET_MBOX6, 12, 6), 181 + EIC7700_RESET(EIC7700_RESET_MBOX7, 12, 7), 182 + EIC7700_RESET(EIC7700_RESET_MBOX8, 12, 8), 183 + EIC7700_RESET(EIC7700_RESET_MBOX9, 12, 9), 184 + EIC7700_RESET(EIC7700_RESET_MBOX10, 12, 10), 185 + EIC7700_RESET(EIC7700_RESET_MBOX11, 12, 11), 186 + EIC7700_RESET(EIC7700_RESET_MBOX12, 12, 12), 187 + EIC7700_RESET(EIC7700_RESET_MBOX13, 12, 13), 188 + EIC7700_RESET(EIC7700_RESET_MBOX14, 12, 14), 189 + EIC7700_RESET(EIC7700_RESET_MBOX15, 12, 15), 190 + EIC7700_RESET(EIC7700_RESET_UART0, 13, 0), 191 + EIC7700_RESET(EIC7700_RESET_UART1, 13, 1), 192 + EIC7700_RESET(EIC7700_RESET_UART2, 13, 2), 193 + EIC7700_RESET(EIC7700_RESET_UART3, 13, 3), 194 + EIC7700_RESET(EIC7700_RESET_UART4, 13, 4), 195 + EIC7700_RESET(EIC7700_RESET_GPIO0, 14, 0), 196 + EIC7700_RESET(EIC7700_RESET_GPIO1, 14, 1), 197 + EIC7700_RESET(EIC7700_RESET_TIMER, 15, 0), 198 + EIC7700_RESET(EIC7700_RESET_SSI0, 16, 0), 199 + EIC7700_RESET(EIC7700_RESET_SSI1, 16, 1), 200 + EIC7700_RESET(EIC7700_RESET_WDT0, 17, 0), 201 + EIC7700_RESET(EIC7700_RESET_WDT1, 17, 1), 202 + EIC7700_RESET(EIC7700_RESET_WDT2, 17, 2), 203 + EIC7700_RESET(EIC7700_RESET_WDT3, 17, 3), 204 + EIC7700_RESET(EIC7700_RESET_LSP_CFG, 18, 0), 205 + EIC7700_RESET(EIC7700_RESET_U84_CORE0, 19, 0), 206 + EIC7700_RESET(EIC7700_RESET_U84_CORE1, 19, 1), 207 + EIC7700_RESET(EIC7700_RESET_U84_CORE2, 19, 2), 208 + EIC7700_RESET(EIC7700_RESET_U84_CORE3, 19, 3), 209 + EIC7700_RESET(EIC7700_RESET_U84_BUS, 19, 4), 210 + EIC7700_RESET(EIC7700_RESET_U84_DBG, 19, 5), 211 + EIC7700_RESET(EIC7700_RESET_U84_TRACECOM, 19, 6), 212 + EIC7700_RESET(EIC7700_RESET_U84_TRACE0, 19, 8), 213 + EIC7700_RESET(EIC7700_RESET_U84_TRACE1, 19, 9), 214 + EIC7700_RESET(EIC7700_RESET_U84_TRACE2, 19, 10), 215 + EIC7700_RESET(EIC7700_RESET_U84_TRACE3, 19, 11), 216 + EIC7700_RESET(EIC7700_RESET_SCPU_CORE, 20, 0), 217 + EIC7700_RESET(EIC7700_RESET_SCPU_BUS, 20, 1), 218 + EIC7700_RESET(EIC7700_RESET_SCPU_DBG, 20, 2), 219 + EIC7700_RESET(EIC7700_RESET_LPCPU_CORE, 21, 0), 220 + EIC7700_RESET(EIC7700_RESET_LPCPU_BUS, 21, 1), 221 + EIC7700_RESET(EIC7700_RESET_LPCPU_DBG, 21, 2), 222 + EIC7700_RESET(EIC7700_RESET_VC_CFG, 22, 0), 223 + EIC7700_RESET(EIC7700_RESET_VC_AXI, 22, 1), 224 + EIC7700_RESET(EIC7700_RESET_VC_MONCFG, 22, 2), 225 + EIC7700_RESET(EIC7700_RESET_JD_CFG, 23, 0), 226 + EIC7700_RESET(EIC7700_RESET_JD_AXI, 23, 1), 227 + EIC7700_RESET(EIC7700_RESET_JE_CFG, 24, 0), 228 + EIC7700_RESET(EIC7700_RESET_JE_AXI, 24, 1), 229 + EIC7700_RESET(EIC7700_RESET_VD_CFG, 25, 0), 230 + EIC7700_RESET(EIC7700_RESET_VD_AXI, 25, 1), 231 + EIC7700_RESET(EIC7700_RESET_VE_AXI, 26, 0), 232 + EIC7700_RESET(EIC7700_RESET_VE_CFG, 26, 1), 233 + EIC7700_RESET(EIC7700_RESET_G2D_CORE, 27, 0), 234 + EIC7700_RESET(EIC7700_RESET_G2D_CFG, 27, 1), 235 + EIC7700_RESET(EIC7700_RESET_G2D_AXI, 27, 2), 236 + EIC7700_RESET(EIC7700_RESET_VI_AXI, 28, 0), 237 + EIC7700_RESET(EIC7700_RESET_VI_CFG, 28, 1), 238 + EIC7700_RESET(EIC7700_RESET_VI_DWE, 28, 2), 239 + EIC7700_RESET(EIC7700_RESET_DVP, 29, 0), 240 + EIC7700_RESET(EIC7700_RESET_ISP0, 30, 0), 241 + EIC7700_RESET(EIC7700_RESET_ISP1, 31, 0), 242 + EIC7700_RESET(EIC7700_RESET_SHUTTR0, 32, 0), 243 + EIC7700_RESET(EIC7700_RESET_SHUTTR1, 32, 1), 244 + EIC7700_RESET(EIC7700_RESET_SHUTTR2, 32, 2), 245 + EIC7700_RESET(EIC7700_RESET_SHUTTR3, 32, 3), 246 + EIC7700_RESET(EIC7700_RESET_SHUTTR4, 32, 4), 247 + EIC7700_RESET(EIC7700_RESET_SHUTTR5, 32, 5), 248 + EIC7700_RESET(EIC7700_RESET_VO_MIPI, 33, 0), 249 + EIC7700_RESET(EIC7700_RESET_VO_PRST, 33, 1), 250 + EIC7700_RESET(EIC7700_RESET_VO_HDMI_PRST, 33, 3), 251 + EIC7700_RESET(EIC7700_RESET_VO_HDMI_PHY, 33, 4), 252 + EIC7700_RESET(EIC7700_RESET_VO_HDMI, 33, 5), 253 + EIC7700_RESET(EIC7700_RESET_VO_I2S, 34, 0), 254 + EIC7700_RESET(EIC7700_RESET_VO_I2S_PRST, 34, 1), 255 + EIC7700_RESET(EIC7700_RESET_VO_AXI, 35, 0), 256 + EIC7700_RESET(EIC7700_RESET_VO_CFG, 35, 1), 257 + EIC7700_RESET(EIC7700_RESET_VO_DC, 35, 2), 258 + EIC7700_RESET(EIC7700_RESET_VO_DC_PRST, 35, 3), 259 + EIC7700_RESET(EIC7700_RESET_BOOTSPI_HRST, 36, 0), 260 + EIC7700_RESET(EIC7700_RESET_BOOTSPI, 36, 1), 261 + EIC7700_RESET(EIC7700_RESET_ANO1, 37, 0), 262 + EIC7700_RESET(EIC7700_RESET_ANO0, 38, 0), 263 + EIC7700_RESET(EIC7700_RESET_DMA1_ARST, 39, 0), 264 + EIC7700_RESET(EIC7700_RESET_DMA1_HRST, 39, 1), 265 + EIC7700_RESET(EIC7700_RESET_FPRT, 40, 0), 266 + EIC7700_RESET(EIC7700_RESET_HBLOCK, 41, 0), 267 + EIC7700_RESET(EIC7700_RESET_SECSR, 42, 0), 268 + EIC7700_RESET(EIC7700_RESET_OTP, 43, 0), 269 + EIC7700_RESET(EIC7700_RESET_PKA, 44, 0), 270 + EIC7700_RESET(EIC7700_RESET_SPACC, 45, 0), 271 + EIC7700_RESET(EIC7700_RESET_TRNG, 46, 0), 272 + EIC7700_RESET(EIC7700_RESET_TIMER0_0, 48, 0), 273 + EIC7700_RESET(EIC7700_RESET_TIMER0_1, 48, 1), 274 + EIC7700_RESET(EIC7700_RESET_TIMER0_2, 48, 2), 275 + EIC7700_RESET(EIC7700_RESET_TIMER0_3, 48, 3), 276 + EIC7700_RESET(EIC7700_RESET_TIMER0_4, 48, 4), 277 + EIC7700_RESET(EIC7700_RESET_TIMER0_5, 48, 5), 278 + EIC7700_RESET(EIC7700_RESET_TIMER0_6, 48, 6), 279 + EIC7700_RESET(EIC7700_RESET_TIMER0_7, 48, 7), 280 + EIC7700_RESET(EIC7700_RESET_TIMER0_N, 48, 8), 281 + EIC7700_RESET(EIC7700_RESET_TIMER1_0, 49, 0), 282 + EIC7700_RESET(EIC7700_RESET_TIMER1_1, 49, 1), 283 + EIC7700_RESET(EIC7700_RESET_TIMER1_2, 49, 2), 284 + EIC7700_RESET(EIC7700_RESET_TIMER1_3, 49, 3), 285 + EIC7700_RESET(EIC7700_RESET_TIMER1_4, 49, 4), 286 + EIC7700_RESET(EIC7700_RESET_TIMER1_5, 49, 5), 287 + EIC7700_RESET(EIC7700_RESET_TIMER1_6, 49, 6), 288 + EIC7700_RESET(EIC7700_RESET_TIMER1_7, 49, 7), 289 + EIC7700_RESET(EIC7700_RESET_TIMER1_N, 49, 8), 290 + EIC7700_RESET(EIC7700_RESET_TIMER2_0, 50, 0), 291 + EIC7700_RESET(EIC7700_RESET_TIMER2_1, 50, 1), 292 + EIC7700_RESET(EIC7700_RESET_TIMER2_2, 50, 2), 293 + EIC7700_RESET(EIC7700_RESET_TIMER2_3, 50, 3), 294 + EIC7700_RESET(EIC7700_RESET_TIMER2_4, 50, 4), 295 + EIC7700_RESET(EIC7700_RESET_TIMER2_5, 50, 5), 296 + EIC7700_RESET(EIC7700_RESET_TIMER2_6, 50, 6), 297 + EIC7700_RESET(EIC7700_RESET_TIMER2_7, 50, 7), 298 + EIC7700_RESET(EIC7700_RESET_TIMER2_N, 50, 8), 299 + EIC7700_RESET(EIC7700_RESET_TIMER3_0, 51, 0), 300 + EIC7700_RESET(EIC7700_RESET_TIMER3_1, 51, 1), 301 + EIC7700_RESET(EIC7700_RESET_TIMER3_2, 51, 2), 302 + EIC7700_RESET(EIC7700_RESET_TIMER3_3, 51, 3), 303 + EIC7700_RESET(EIC7700_RESET_TIMER3_4, 51, 4), 304 + EIC7700_RESET(EIC7700_RESET_TIMER3_5, 51, 5), 305 + EIC7700_RESET(EIC7700_RESET_TIMER3_6, 51, 6), 306 + EIC7700_RESET(EIC7700_RESET_TIMER3_7, 51, 7), 307 + EIC7700_RESET(EIC7700_RESET_TIMER3_N, 51, 8), 308 + EIC7700_RESET(EIC7700_RESET_RTC, 52, 0), 309 + EIC7700_RESET(EIC7700_RESET_MNOC_SNOC_NSP, 53, 0), 310 + EIC7700_RESET(EIC7700_RESET_MNOC_VC, 53, 1), 311 + EIC7700_RESET(EIC7700_RESET_MNOC_CFG, 53, 2), 312 + EIC7700_RESET(EIC7700_RESET_MNOC_HSP, 53, 3), 313 + EIC7700_RESET(EIC7700_RESET_MNOC_GPU, 53, 4), 314 + EIC7700_RESET(EIC7700_RESET_MNOC_DDRC1_P3, 53, 5), 315 + EIC7700_RESET(EIC7700_RESET_MNOC_DDRC0_P3, 53, 6), 316 + EIC7700_RESET(EIC7700_RESET_RNOC_VO, 54, 0), 317 + EIC7700_RESET(EIC7700_RESET_RNOC_VI, 54, 1), 318 + EIC7700_RESET(EIC7700_RESET_RNOC_SNOC_NSP, 54, 2), 319 + EIC7700_RESET(EIC7700_RESET_RNOC_CFG, 54, 3), 320 + EIC7700_RESET(EIC7700_RESET_MNOC_DDRC1_P4, 54, 4), 321 + EIC7700_RESET(EIC7700_RESET_MNOC_DDRC0_P4, 54, 5), 322 + EIC7700_RESET(EIC7700_RESET_CNOC_VO_CFG, 55, 0), 323 + EIC7700_RESET(EIC7700_RESET_CNOC_VI_CFG, 55, 1), 324 + EIC7700_RESET(EIC7700_RESET_CNOC_VC_CFG, 55, 2), 325 + EIC7700_RESET(EIC7700_RESET_CNOC_TCU_CFG, 55, 3), 326 + EIC7700_RESET(EIC7700_RESET_CNOC_PCIE_CFG, 55, 4), 327 + EIC7700_RESET(EIC7700_RESET_CNOC_NPU_CFG, 55, 5), 328 + EIC7700_RESET(EIC7700_RESET_CNOC_LSP_CFG, 55, 6), 329 + EIC7700_RESET(EIC7700_RESET_CNOC_HSP_CFG, 55, 7), 330 + EIC7700_RESET(EIC7700_RESET_CNOC_GPU_CFG, 55, 8), 331 + EIC7700_RESET(EIC7700_RESET_CNOC_DSPT_CFG, 55, 9), 332 + EIC7700_RESET(EIC7700_RESET_CNOC_DDRT1_CFG, 55, 10), 333 + EIC7700_RESET(EIC7700_RESET_CNOC_DDRT0_CFG, 55, 11), 334 + EIC7700_RESET(EIC7700_RESET_CNOC_D2D_CFG, 55, 12), 335 + EIC7700_RESET(EIC7700_RESET_CNOC_CFG, 55, 13), 336 + EIC7700_RESET(EIC7700_RESET_CNOC_CLMM_CFG, 55, 14), 337 + EIC7700_RESET(EIC7700_RESET_CNOC_AON_CFG, 55, 15), 338 + EIC7700_RESET(EIC7700_RESET_LNOC_CFG, 56, 0), 339 + EIC7700_RESET(EIC7700_RESET_LNOC_NPU_LLC, 56, 1), 340 + EIC7700_RESET(EIC7700_RESET_LNOC_DDRC1_P0, 56, 2), 341 + EIC7700_RESET(EIC7700_RESET_LNOC_DDRC0_P0, 56, 3), 342 + }; 343 + 344 + static int eic7700_reset_assert(struct reset_controller_dev *rcdev, 345 + unsigned long id) 346 + { 347 + struct eic7700_reset_data *data = to_eic7700_reset_data(rcdev); 348 + 349 + return regmap_clear_bits(data->regmap, eic7700_reset[id].reg, 350 + eic7700_reset[id].bit); 351 + } 352 + 353 + static int eic7700_reset_deassert(struct reset_controller_dev *rcdev, 354 + unsigned long id) 355 + { 356 + struct eic7700_reset_data *data = to_eic7700_reset_data(rcdev); 357 + 358 + return regmap_set_bits(data->regmap, eic7700_reset[id].reg, 359 + eic7700_reset[id].bit); 360 + } 361 + 362 + static int eic7700_reset_reset(struct reset_controller_dev *rcdev, 363 + unsigned long id) 364 + { 365 + int ret; 366 + 367 + ret = eic7700_reset_assert(rcdev, id); 368 + if (ret) 369 + return ret; 370 + 371 + usleep_range(10, 15); 372 + 373 + return eic7700_reset_deassert(rcdev, id); 374 + } 375 + 376 + static const struct reset_control_ops eic7700_reset_ops = { 377 + .reset = eic7700_reset_reset, 378 + .assert = eic7700_reset_assert, 379 + .deassert = eic7700_reset_deassert, 380 + }; 381 + 382 + static const struct of_device_id eic7700_reset_dt_ids[] = { 383 + { .compatible = "eswin,eic7700-reset", }, 384 + { /* sentinel */ } 385 + }; 386 + 387 + static int eic7700_reset_probe(struct platform_device *pdev) 388 + { 389 + struct eic7700_reset_data *data; 390 + struct device *dev = &pdev->dev; 391 + void __iomem *base; 392 + 393 + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 394 + if (!data) 395 + return -ENOMEM; 396 + 397 + base = devm_platform_ioremap_resource(pdev, 0); 398 + if (IS_ERR(base)) 399 + return PTR_ERR(base); 400 + 401 + data->regmap = devm_regmap_init_mmio(dev, base, &eic7700_regmap_config); 402 + if (IS_ERR(data->regmap)) 403 + return dev_err_probe(dev, PTR_ERR(data->regmap), 404 + "failed to get regmap!\n"); 405 + 406 + data->rcdev.owner = THIS_MODULE; 407 + data->rcdev.ops = &eic7700_reset_ops; 408 + data->rcdev.of_node = dev->of_node; 409 + data->rcdev.of_reset_n_cells = 1; 410 + data->rcdev.dev = dev; 411 + data->rcdev.nr_resets = ARRAY_SIZE(eic7700_reset); 412 + 413 + /* clear boot flag so u84 and scpu could be reseted by software */ 414 + regmap_set_bits(data->regmap, SYSCRG_CLEAR_BOOT_INFO_OFFSET, 415 + CLEAR_BOOT_FLAG_BIT); 416 + msleep(50); 417 + 418 + return devm_reset_controller_register(dev, &data->rcdev); 419 + } 420 + 421 + static struct platform_driver eic7700_reset_driver = { 422 + .probe = eic7700_reset_probe, 423 + .driver = { 424 + .name = "eic7700-reset", 425 + .of_match_table = eic7700_reset_dt_ids, 426 + }, 427 + }; 428 + 429 + builtin_platform_driver(eic7700_reset_driver);

+60

drivers/reset/reset-rzg2l-usbphy-ctrl.c

··· 13 13 #include <linux/regmap.h> 14 14 #include <linux/reset.h> 15 15 #include <linux/reset-controller.h> 16 + #include <linux/mfd/syscon.h> 16 17 17 18 #define RESET 0x000 18 19 #define VBENCTL 0x03c ··· 92 91 return !!(readl(priv->base + RESET) & port_mask); 93 92 } 94 93 94 + #define RZG2L_USBPHY_CTRL_PWRRDY 1 95 + 95 96 static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = { 96 97 { .compatible = "renesas,rzg2l-usbphy-ctrl" }, 98 + { 99 + .compatible = "renesas,r9a08g045-usbphy-ctrl", 100 + .data = (void *)RZG2L_USBPHY_CTRL_PWRRDY 101 + }, 97 102 { /* Sentinel */ } 98 103 }; 99 104 MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table); ··· 116 109 .reg_stride = 4, 117 110 .max_register = 1, 118 111 }; 112 + 113 + static void rzg2l_usbphy_ctrl_set_pwrrdy(struct regmap_field *pwrrdy, 114 + bool power_on) 115 + { 116 + u32 val = power_on ? 0 : 1; 117 + 118 + /* The initialization path guarantees that the mask is 1 bit long. */ 119 + regmap_field_update_bits(pwrrdy, 1, val); 120 + } 121 + 122 + static void rzg2l_usbphy_ctrl_pwrrdy_off(void *data) 123 + { 124 + rzg2l_usbphy_ctrl_set_pwrrdy(data, false); 125 + } 126 + 127 + static int rzg2l_usbphy_ctrl_pwrrdy_init(struct device *dev) 128 + { 129 + struct regmap_field *pwrrdy; 130 + struct reg_field field; 131 + struct regmap *regmap; 132 + const int *data; 133 + u32 args[2]; 134 + 135 + data = device_get_match_data(dev); 136 + if ((uintptr_t)data != RZG2L_USBPHY_CTRL_PWRRDY) 137 + return 0; 138 + 139 + regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, 140 + "renesas,sysc-pwrrdy", 141 + ARRAY_SIZE(args), args); 142 + if (IS_ERR(regmap)) 143 + return PTR_ERR(regmap); 144 + 145 + /* Don't allow more than one bit in mask. */ 146 + if (hweight32(args[1]) != 1) 147 + return -EINVAL; 148 + 149 + field.reg = args[0]; 150 + field.lsb = __ffs(args[1]); 151 + field.msb = __fls(args[1]); 152 + 153 + pwrrdy = devm_regmap_field_alloc(dev, regmap, field); 154 + if (IS_ERR(pwrrdy)) 155 + return PTR_ERR(pwrrdy); 156 + 157 + rzg2l_usbphy_ctrl_set_pwrrdy(pwrrdy, true); 158 + 159 + return devm_add_action_or_reset(dev, rzg2l_usbphy_ctrl_pwrrdy_off, pwrrdy); 160 + } 119 161 120 162 static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev) 121 163 { ··· 187 131 regmap = devm_regmap_init_mmio(dev, priv->base + VBENCTL, &rzg2l_usb_regconf); 188 132 if (IS_ERR(regmap)) 189 133 return PTR_ERR(regmap); 134 + 135 + error = rzg2l_usbphy_ctrl_pwrrdy_init(dev); 136 + if (error) 137 + return error; 190 138 191 139 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 192 140 if (IS_ERR(priv->rstc))

+824 -13

drivers/reset/reset-th1520.c

··· 11 11 12 12 #include <dt-bindings/reset/thead,th1520-reset.h> 13 13 14 + /* register offset in RSTGEN_R */ 15 + #define TH1520_BROM_RST_CFG 0x0 16 + #define TH1520_C910_RST_CFG 0x4 17 + #define TH1520_CHIP_DBG_RST_CFG 0xc 18 + #define TH1520_AXI4_CPUSYS2_RST_CFG 0x10 19 + #define TH1520_X2H_CPUSYS_RST_CFG 0x18 20 + #define TH1520_AHB2_CPUSYS_RST_CFG 0x1c 21 + #define TH1520_APB3_CPUSYS_RST_CFG 0x20 22 + #define TH1520_MBOX0_RST_CFG 0x24 23 + #define TH1520_MBOX1_RST_CFG 0x28 24 + #define TH1520_MBOX2_RST_CFG 0x2c 25 + #define TH1520_MBOX3_RST_CFG 0x30 26 + #define TH1520_WDT0_RST_CFG 0x34 27 + #define TH1520_WDT1_RST_CFG 0x38 28 + #define TH1520_TIMER0_RST_CFG 0x3c 29 + #define TH1520_TIMER1_RST_CFG 0x40 30 + #define TH1520_PERISYS_AHB_RST_CFG 0x44 31 + #define TH1520_PERISYS_APB1_RST_CFG 0x48 32 + #define TH1520_PERISYS_APB2_RST_CFG 0x4c 33 + #define TH1520_GMAC0_RST_CFG 0x68 34 + #define TH1520_UART0_RST_CFG 0x70 35 + #define TH1520_UART1_RST_CFG 0x74 36 + #define TH1520_UART2_RST_CFG 0x78 37 + #define TH1520_UART3_RST_CFG 0x7c 38 + #define TH1520_UART4_RST_CFG 0x80 39 + #define TH1520_UART5_RST_CFG 0x84 40 + #define TH1520_QSPI0_RST_CFG 0x8c 41 + #define TH1520_QSPI1_RST_CFG 0x90 42 + #define TH1520_SPI_RST_CFG 0x94 43 + #define TH1520_I2C0_RST_CFG 0x98 44 + #define TH1520_I2C1_RST_CFG 0x9c 45 + #define TH1520_I2C2_RST_CFG 0xa0 46 + #define TH1520_I2C3_RST_CFG 0xa4 47 + #define TH1520_I2C4_RST_CFG 0xa8 48 + #define TH1520_I2C5_RST_CFG 0xac 49 + #define TH1520_GPIO0_RST_CFG 0xb0 50 + #define TH1520_GPIO1_RST_CFG 0xb4 51 + #define TH1520_GPIO2_RST_CFG 0xb8 52 + #define TH1520_PWM_RST_CFG 0xc0 53 + #define TH1520_PADCTRL0_APSYS_RST_CFG 0xc4 54 + #define TH1520_CPU2PERI_X2H_RST_CFG 0xcc 55 + #define TH1520_CPU2AON_X2H_RST_CFG 0xe4 56 + #define TH1520_AON2CPU_A2X_RST_CFG 0xfc 57 + #define TH1520_NPUSYS_AXI_RST_CFG 0x128 58 + #define TH1520_CPU2VP_X2P_RST_CFG 0x12c 59 + #define TH1520_CPU2VI_X2H_RST_CFG 0x138 60 + #define TH1520_BMU_C910_RST_CFG 0x148 61 + #define TH1520_DMAC_CPUSYS_RST_CFG 0x14c 62 + #define TH1520_SPINLOCK_RST_CFG 0x178 63 + #define TH1520_CFG2TEE_X2H_RST_CFG 0x188 64 + #define TH1520_DSMART_RST_CFG 0x18c 65 + #define TH1520_GPIO3_RST_CFG 0x1a8 66 + #define TH1520_I2S_RST_CFG 0x1ac 67 + #define TH1520_IMG_NNA_RST_CFG 0x1b0 68 + #define TH1520_PERI_APB3_RST_CFG 0x1dc 69 + #define TH1520_VP_SUBSYS_RST_CFG 0x1ec 70 + #define TH1520_PERISYS_APB4_RST_CFG 0x1f8 71 + #define TH1520_GMAC1_RST_CFG 0x204 72 + #define TH1520_GMAC_AXI_RST_CFG 0x208 73 + #define TH1520_PADCTRL1_APSYS_RST_CFG 0x20c 74 + #define TH1520_VOSYS_AXI_RST_CFG 0x210 75 + #define TH1520_VOSYS_X2X_RST_CFG 0x214 76 + #define TH1520_MISC2VP_X2X_RST_CFG 0x218 77 + #define TH1520_SUBSYS_RST_CFG 0x220 78 + 79 + /* register offset in DSP_REGMAP */ 80 + #define TH1520_DSPSYS_RST_CFG 0x0 81 + 82 + /* register offset in MISCSYS_REGMAP */ 83 + #define TH1520_EMMC_RST_CFG 0x0 84 + #define TH1520_MISCSYS_AXI_RST_CFG 0x8 85 + #define TH1520_SDIO0_RST_CFG 0xc 86 + #define TH1520_SDIO1_RST_CFG 0x10 87 + #define TH1520_USB3_DRD_RST_CFG 0x14 88 + 89 + /* register offset in VISYS_REGMAP */ 90 + #define TH1520_VISYS_RST_CFG 0x0 91 + #define TH1520_VISYS_2_RST_CFG 0x4 92 + 14 93 /* register offset in VOSYS_REGMAP */ 15 94 #define TH1520_GPU_RST_CFG 0x0 16 95 #define TH1520_GPU_RST_CFG_MASK GENMASK(1, 0) ··· 97 18 #define TH1520_DSI0_RST_CFG 0x8 98 19 #define TH1520_DSI1_RST_CFG 0xc 99 20 #define TH1520_HDMI_RST_CFG 0x14 21 + #define TH1520_AXI4_VO_DW_AXI_RST_CFG 0x18 22 + #define TH1520_X2H_X4_VOSYS_DW_RST_CFG 0x20 100 23 101 24 /* register values */ 102 25 #define TH1520_GPU_SW_GPU_RST BIT(0) ··· 110 29 #define TH1520_HDMI_SW_MAIN_RST BIT(0) 111 30 #define TH1520_HDMI_SW_PRST BIT(1) 112 31 113 - struct th1520_reset_priv { 114 - struct reset_controller_dev rcdev; 115 - struct regmap *map; 116 - }; 32 + /* register offset in VPSYS_REGMAP */ 33 + #define TH1520_AXIBUS_RST_CFG 0x0 34 + #define TH1520_FCE_RST_CFG 0x4 35 + #define TH1520_G2D_RST_CFG 0x8 36 + #define TH1520_VDEC_RST_CFG 0xc 37 + #define TH1520_VENC_RST_CFG 0x10 117 38 118 39 struct th1520_reset_map { 119 40 u32 bit; 120 41 u32 reg; 42 + }; 43 + 44 + struct th1520_reset_priv { 45 + struct reset_controller_dev rcdev; 46 + struct regmap *map; 47 + const struct th1520_reset_map *resets; 48 + }; 49 + 50 + struct th1520_reset_data { 51 + const struct th1520_reset_map *resets; 52 + size_t num; 121 53 }; 122 54 123 55 static const struct th1520_reset_map th1520_resets[] = { ··· 170 76 .bit = TH1520_HDMI_SW_PRST, 171 77 .reg = TH1520_HDMI_RST_CFG, 172 78 }, 79 + [TH1520_RESET_ID_VOAXI] = { 80 + .bit = BIT(0), 81 + .reg = TH1520_AXI4_VO_DW_AXI_RST_CFG, 82 + }, 83 + [TH1520_RESET_ID_VOAXI_APB] = { 84 + .bit = BIT(1), 85 + .reg = TH1520_AXI4_VO_DW_AXI_RST_CFG, 86 + }, 87 + [TH1520_RESET_ID_X2H_DPU_AXI] = { 88 + .bit = BIT(0), 89 + .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, 90 + }, 91 + [TH1520_RESET_ID_X2H_DPU_AHB] = { 92 + .bit = BIT(1), 93 + .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, 94 + }, 95 + [TH1520_RESET_ID_X2H_DPU1_AXI] = { 96 + .bit = BIT(2), 97 + .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, 98 + }, 99 + [TH1520_RESET_ID_X2H_DPU1_AHB] = { 100 + .bit = BIT(3), 101 + .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, 102 + }, 103 + }; 104 + 105 + static const struct th1520_reset_map th1520_ap_resets[] = { 106 + [TH1520_RESET_ID_BROM] = { 107 + .bit = BIT(0), 108 + .reg = TH1520_BROM_RST_CFG, 109 + }, 110 + [TH1520_RESET_ID_C910_TOP] = { 111 + .bit = BIT(0), 112 + .reg = TH1520_C910_RST_CFG, 113 + }, 114 + [TH1520_RESET_ID_NPU] = { 115 + .bit = BIT(0), 116 + .reg = TH1520_IMG_NNA_RST_CFG, 117 + }, 118 + [TH1520_RESET_ID_WDT0] = { 119 + .bit = BIT(0), 120 + .reg = TH1520_WDT0_RST_CFG, 121 + }, 122 + [TH1520_RESET_ID_WDT1] = { 123 + .bit = BIT(0), 124 + .reg = TH1520_WDT1_RST_CFG, 125 + }, 126 + [TH1520_RESET_ID_C910_C0] = { 127 + .bit = BIT(1), 128 + .reg = TH1520_C910_RST_CFG, 129 + }, 130 + [TH1520_RESET_ID_C910_C1] = { 131 + .bit = BIT(2), 132 + .reg = TH1520_C910_RST_CFG, 133 + }, 134 + [TH1520_RESET_ID_C910_C2] = { 135 + .bit = BIT(3), 136 + .reg = TH1520_C910_RST_CFG, 137 + }, 138 + [TH1520_RESET_ID_C910_C3] = { 139 + .bit = BIT(4), 140 + .reg = TH1520_C910_RST_CFG, 141 + }, 142 + [TH1520_RESET_ID_CHIP_DBG_CORE] = { 143 + .bit = BIT(0), 144 + .reg = TH1520_CHIP_DBG_RST_CFG, 145 + }, 146 + [TH1520_RESET_ID_CHIP_DBG_AXI] = { 147 + .bit = BIT(1), 148 + .reg = TH1520_CHIP_DBG_RST_CFG, 149 + }, 150 + [TH1520_RESET_ID_AXI4_CPUSYS2_AXI] = { 151 + .bit = BIT(0), 152 + .reg = TH1520_AXI4_CPUSYS2_RST_CFG, 153 + }, 154 + [TH1520_RESET_ID_AXI4_CPUSYS2_APB] = { 155 + .bit = BIT(1), 156 + .reg = TH1520_AXI4_CPUSYS2_RST_CFG, 157 + }, 158 + [TH1520_RESET_ID_X2H_CPUSYS] = { 159 + .bit = BIT(0), 160 + .reg = TH1520_X2H_CPUSYS_RST_CFG, 161 + }, 162 + [TH1520_RESET_ID_AHB2_CPUSYS] = { 163 + .bit = BIT(0), 164 + .reg = TH1520_AHB2_CPUSYS_RST_CFG, 165 + }, 166 + [TH1520_RESET_ID_APB3_CPUSYS] = { 167 + .bit = BIT(0), 168 + .reg = TH1520_APB3_CPUSYS_RST_CFG, 169 + }, 170 + [TH1520_RESET_ID_MBOX0_APB] = { 171 + .bit = BIT(0), 172 + .reg = TH1520_MBOX0_RST_CFG, 173 + }, 174 + [TH1520_RESET_ID_MBOX1_APB] = { 175 + .bit = BIT(0), 176 + .reg = TH1520_MBOX1_RST_CFG, 177 + }, 178 + [TH1520_RESET_ID_MBOX2_APB] = { 179 + .bit = BIT(0), 180 + .reg = TH1520_MBOX2_RST_CFG, 181 + }, 182 + [TH1520_RESET_ID_MBOX3_APB] = { 183 + .bit = BIT(0), 184 + .reg = TH1520_MBOX3_RST_CFG, 185 + }, 186 + [TH1520_RESET_ID_TIMER0_APB] = { 187 + .bit = BIT(0), 188 + .reg = TH1520_TIMER0_RST_CFG, 189 + }, 190 + [TH1520_RESET_ID_TIMER0_CORE] = { 191 + .bit = BIT(1), 192 + .reg = TH1520_TIMER0_RST_CFG, 193 + }, 194 + [TH1520_RESET_ID_TIMER1_APB] = { 195 + .bit = BIT(0), 196 + .reg = TH1520_TIMER1_RST_CFG, 197 + }, 198 + [TH1520_RESET_ID_TIMER1_CORE] = { 199 + .bit = BIT(1), 200 + .reg = TH1520_TIMER1_RST_CFG, 201 + }, 202 + [TH1520_RESET_ID_PERISYS_AHB] = { 203 + .bit = BIT(0), 204 + .reg = TH1520_PERISYS_AHB_RST_CFG, 205 + }, 206 + [TH1520_RESET_ID_PERISYS_APB1] = { 207 + .bit = BIT(0), 208 + .reg = TH1520_PERISYS_APB1_RST_CFG, 209 + }, 210 + [TH1520_RESET_ID_PERISYS_APB2] = { 211 + .bit = BIT(0), 212 + .reg = TH1520_PERISYS_APB2_RST_CFG, 213 + }, 214 + [TH1520_RESET_ID_GMAC0_APB] = { 215 + .bit = BIT(0), 216 + .reg = TH1520_GMAC0_RST_CFG, 217 + }, 218 + [TH1520_RESET_ID_GMAC0_AHB] = { 219 + .bit = BIT(1), 220 + .reg = TH1520_GMAC0_RST_CFG, 221 + }, 222 + [TH1520_RESET_ID_GMAC0_CLKGEN] = { 223 + .bit = BIT(2), 224 + .reg = TH1520_GMAC0_RST_CFG, 225 + }, 226 + [TH1520_RESET_ID_GMAC0_AXI] = { 227 + .bit = BIT(3), 228 + .reg = TH1520_GMAC0_RST_CFG, 229 + }, 230 + [TH1520_RESET_ID_UART0_APB] = { 231 + .bit = BIT(0), 232 + .reg = TH1520_UART0_RST_CFG, 233 + }, 234 + [TH1520_RESET_ID_UART0_IF] = { 235 + .bit = BIT(1), 236 + .reg = TH1520_UART0_RST_CFG, 237 + }, 238 + [TH1520_RESET_ID_UART1_APB] = { 239 + .bit = BIT(0), 240 + .reg = TH1520_UART1_RST_CFG, 241 + }, 242 + [TH1520_RESET_ID_UART1_IF] = { 243 + .bit = BIT(1), 244 + .reg = TH1520_UART1_RST_CFG, 245 + }, 246 + [TH1520_RESET_ID_UART2_APB] = { 247 + .bit = BIT(0), 248 + .reg = TH1520_UART2_RST_CFG, 249 + }, 250 + [TH1520_RESET_ID_UART2_IF] = { 251 + .bit = BIT(1), 252 + .reg = TH1520_UART2_RST_CFG, 253 + }, 254 + [TH1520_RESET_ID_UART3_APB] = { 255 + .bit = BIT(0), 256 + .reg = TH1520_UART3_RST_CFG, 257 + }, 258 + [TH1520_RESET_ID_UART3_IF] = { 259 + .bit = BIT(1), 260 + .reg = TH1520_UART3_RST_CFG, 261 + }, 262 + [TH1520_RESET_ID_UART4_APB] = { 263 + .bit = BIT(0), 264 + .reg = TH1520_UART4_RST_CFG, 265 + }, 266 + [TH1520_RESET_ID_UART4_IF] = { 267 + .bit = BIT(1), 268 + .reg = TH1520_UART4_RST_CFG, 269 + }, 270 + [TH1520_RESET_ID_UART5_APB] = { 271 + .bit = BIT(0), 272 + .reg = TH1520_UART5_RST_CFG, 273 + }, 274 + [TH1520_RESET_ID_UART5_IF] = { 275 + .bit = BIT(1), 276 + .reg = TH1520_UART5_RST_CFG, 277 + }, 278 + [TH1520_RESET_ID_QSPI0_IF] = { 279 + .bit = BIT(0), 280 + .reg = TH1520_QSPI0_RST_CFG, 281 + }, 282 + [TH1520_RESET_ID_QSPI0_APB] = { 283 + .bit = BIT(1), 284 + .reg = TH1520_QSPI0_RST_CFG, 285 + }, 286 + [TH1520_RESET_ID_QSPI1_IF] = { 287 + .bit = BIT(0), 288 + .reg = TH1520_QSPI1_RST_CFG, 289 + }, 290 + [TH1520_RESET_ID_QSPI1_APB] = { 291 + .bit = BIT(1), 292 + .reg = TH1520_QSPI1_RST_CFG, 293 + }, 294 + [TH1520_RESET_ID_SPI_IF] = { 295 + .bit = BIT(0), 296 + .reg = TH1520_SPI_RST_CFG, 297 + }, 298 + [TH1520_RESET_ID_SPI_APB] = { 299 + .bit = BIT(1), 300 + .reg = TH1520_SPI_RST_CFG, 301 + }, 302 + [TH1520_RESET_ID_I2C0_APB] = { 303 + .bit = BIT(0), 304 + .reg = TH1520_I2C0_RST_CFG, 305 + }, 306 + [TH1520_RESET_ID_I2C0_CORE] = { 307 + .bit = BIT(1), 308 + .reg = TH1520_I2C0_RST_CFG, 309 + }, 310 + [TH1520_RESET_ID_I2C1_APB] = { 311 + .bit = BIT(0), 312 + .reg = TH1520_I2C1_RST_CFG, 313 + }, 314 + [TH1520_RESET_ID_I2C1_CORE] = { 315 + .bit = BIT(1), 316 + .reg = TH1520_I2C1_RST_CFG, 317 + }, 318 + [TH1520_RESET_ID_I2C2_APB] = { 319 + .bit = BIT(0), 320 + .reg = TH1520_I2C2_RST_CFG, 321 + }, 322 + [TH1520_RESET_ID_I2C2_CORE] = { 323 + .bit = BIT(1), 324 + .reg = TH1520_I2C2_RST_CFG, 325 + }, 326 + [TH1520_RESET_ID_I2C3_APB] = { 327 + .bit = BIT(0), 328 + .reg = TH1520_I2C3_RST_CFG, 329 + }, 330 + [TH1520_RESET_ID_I2C3_CORE] = { 331 + .bit = BIT(1), 332 + .reg = TH1520_I2C3_RST_CFG, 333 + }, 334 + [TH1520_RESET_ID_I2C4_APB] = { 335 + .bit = BIT(0), 336 + .reg = TH1520_I2C4_RST_CFG, 337 + }, 338 + [TH1520_RESET_ID_I2C4_CORE] = { 339 + .bit = BIT(1), 340 + .reg = TH1520_I2C4_RST_CFG, 341 + }, 342 + [TH1520_RESET_ID_I2C5_APB] = { 343 + .bit = BIT(0), 344 + .reg = TH1520_I2C5_RST_CFG, 345 + }, 346 + [TH1520_RESET_ID_I2C5_CORE] = { 347 + .bit = BIT(1), 348 + .reg = TH1520_I2C5_RST_CFG, 349 + }, 350 + [TH1520_RESET_ID_GPIO0_DB] = { 351 + .bit = BIT(0), 352 + .reg = TH1520_GPIO0_RST_CFG, 353 + }, 354 + [TH1520_RESET_ID_GPIO0_APB] = { 355 + .bit = BIT(1), 356 + .reg = TH1520_GPIO0_RST_CFG, 357 + }, 358 + [TH1520_RESET_ID_GPIO1_DB] = { 359 + .bit = BIT(0), 360 + .reg = TH1520_GPIO1_RST_CFG, 361 + }, 362 + [TH1520_RESET_ID_GPIO1_APB] = { 363 + .bit = BIT(1), 364 + .reg = TH1520_GPIO1_RST_CFG, 365 + }, 366 + [TH1520_RESET_ID_GPIO2_DB] = { 367 + .bit = BIT(0), 368 + .reg = TH1520_GPIO2_RST_CFG, 369 + }, 370 + [TH1520_RESET_ID_GPIO2_APB] = { 371 + .bit = BIT(1), 372 + .reg = TH1520_GPIO2_RST_CFG, 373 + }, 374 + [TH1520_RESET_ID_PWM_COUNTER] = { 375 + .bit = BIT(0), 376 + .reg = TH1520_PWM_RST_CFG, 377 + }, 378 + [TH1520_RESET_ID_PWM_APB] = { 379 + .bit = BIT(1), 380 + .reg = TH1520_PWM_RST_CFG, 381 + }, 382 + [TH1520_RESET_ID_PADCTRL0_APB] = { 383 + .bit = BIT(0), 384 + .reg = TH1520_PADCTRL0_APSYS_RST_CFG, 385 + }, 386 + [TH1520_RESET_ID_CPU2PERI_X2H] = { 387 + .bit = BIT(1), 388 + .reg = TH1520_CPU2PERI_X2H_RST_CFG, 389 + }, 390 + [TH1520_RESET_ID_CPU2AON_X2H] = { 391 + .bit = BIT(0), 392 + .reg = TH1520_CPU2AON_X2H_RST_CFG, 393 + }, 394 + [TH1520_RESET_ID_AON2CPU_A2X] = { 395 + .bit = BIT(0), 396 + .reg = TH1520_AON2CPU_A2X_RST_CFG, 397 + }, 398 + [TH1520_RESET_ID_NPUSYS_AXI] = { 399 + .bit = BIT(0), 400 + .reg = TH1520_NPUSYS_AXI_RST_CFG, 401 + }, 402 + [TH1520_RESET_ID_NPUSYS_AXI_APB] = { 403 + .bit = BIT(1), 404 + .reg = TH1520_NPUSYS_AXI_RST_CFG, 405 + }, 406 + [TH1520_RESET_ID_CPU2VP_X2P] = { 407 + .bit = BIT(0), 408 + .reg = TH1520_CPU2VP_X2P_RST_CFG, 409 + }, 410 + [TH1520_RESET_ID_CPU2VI_X2H] = { 411 + .bit = BIT(0), 412 + .reg = TH1520_CPU2VI_X2H_RST_CFG, 413 + }, 414 + [TH1520_RESET_ID_BMU_AXI] = { 415 + .bit = BIT(0), 416 + .reg = TH1520_BMU_C910_RST_CFG, 417 + }, 418 + [TH1520_RESET_ID_BMU_APB] = { 419 + .bit = BIT(1), 420 + .reg = TH1520_BMU_C910_RST_CFG, 421 + }, 422 + [TH1520_RESET_ID_DMAC_CPUSYS_AXI] = { 423 + .bit = BIT(0), 424 + .reg = TH1520_DMAC_CPUSYS_RST_CFG, 425 + }, 426 + [TH1520_RESET_ID_DMAC_CPUSYS_AHB] = { 427 + .bit = BIT(1), 428 + .reg = TH1520_DMAC_CPUSYS_RST_CFG, 429 + }, 430 + [TH1520_RESET_ID_SPINLOCK] = { 431 + .bit = BIT(0), 432 + .reg = TH1520_SPINLOCK_RST_CFG, 433 + }, 434 + [TH1520_RESET_ID_CFG2TEE] = { 435 + .bit = BIT(0), 436 + .reg = TH1520_CFG2TEE_X2H_RST_CFG, 437 + }, 438 + [TH1520_RESET_ID_DSMART] = { 439 + .bit = BIT(0), 440 + .reg = TH1520_DSMART_RST_CFG, 441 + }, 442 + [TH1520_RESET_ID_GPIO3_DB] = { 443 + .bit = BIT(0), 444 + .reg = TH1520_GPIO3_RST_CFG, 445 + }, 446 + [TH1520_RESET_ID_GPIO3_APB] = { 447 + .bit = BIT(1), 448 + .reg = TH1520_GPIO3_RST_CFG, 449 + }, 450 + [TH1520_RESET_ID_PERI_I2S] = { 451 + .bit = BIT(0), 452 + .reg = TH1520_I2S_RST_CFG, 453 + }, 454 + [TH1520_RESET_ID_PERI_APB3] = { 455 + .bit = BIT(0), 456 + .reg = TH1520_PERI_APB3_RST_CFG, 457 + }, 458 + [TH1520_RESET_ID_PERI2PERI1_APB] = { 459 + .bit = BIT(1), 460 + .reg = TH1520_PERI_APB3_RST_CFG, 461 + }, 462 + [TH1520_RESET_ID_VPSYS_APB] = { 463 + .bit = BIT(0), 464 + .reg = TH1520_VP_SUBSYS_RST_CFG, 465 + }, 466 + [TH1520_RESET_ID_PERISYS_APB4] = { 467 + .bit = BIT(0), 468 + .reg = TH1520_PERISYS_APB4_RST_CFG, 469 + }, 470 + [TH1520_RESET_ID_GMAC1_APB] = { 471 + .bit = BIT(0), 472 + .reg = TH1520_GMAC1_RST_CFG, 473 + }, 474 + [TH1520_RESET_ID_GMAC1_AHB] = { 475 + .bit = BIT(1), 476 + .reg = TH1520_GMAC1_RST_CFG, 477 + }, 478 + [TH1520_RESET_ID_GMAC1_CLKGEN] = { 479 + .bit = BIT(2), 480 + .reg = TH1520_GMAC1_RST_CFG, 481 + }, 482 + [TH1520_RESET_ID_GMAC1_AXI] = { 483 + .bit = BIT(3), 484 + .reg = TH1520_GMAC1_RST_CFG, 485 + }, 486 + [TH1520_RESET_ID_GMAC_AXI] = { 487 + .bit = BIT(0), 488 + .reg = TH1520_GMAC_AXI_RST_CFG, 489 + }, 490 + [TH1520_RESET_ID_GMAC_AXI_APB] = { 491 + .bit = BIT(1), 492 + .reg = TH1520_GMAC_AXI_RST_CFG, 493 + }, 494 + [TH1520_RESET_ID_PADCTRL1_APB] = { 495 + .bit = BIT(0), 496 + .reg = TH1520_PADCTRL1_APSYS_RST_CFG, 497 + }, 498 + [TH1520_RESET_ID_VOSYS_AXI] = { 499 + .bit = BIT(0), 500 + .reg = TH1520_VOSYS_AXI_RST_CFG, 501 + }, 502 + [TH1520_RESET_ID_VOSYS_AXI_APB] = { 503 + .bit = BIT(1), 504 + .reg = TH1520_VOSYS_AXI_RST_CFG, 505 + }, 506 + [TH1520_RESET_ID_VOSYS_AXI_X2X] = { 507 + .bit = BIT(0), 508 + .reg = TH1520_VOSYS_X2X_RST_CFG, 509 + }, 510 + [TH1520_RESET_ID_MISC2VP_X2X] = { 511 + .bit = BIT(0), 512 + .reg = TH1520_MISC2VP_X2X_RST_CFG, 513 + }, 514 + [TH1520_RESET_ID_DSPSYS] = { 515 + .bit = BIT(0), 516 + .reg = TH1520_SUBSYS_RST_CFG, 517 + }, 518 + [TH1520_RESET_ID_VISYS] = { 519 + .bit = BIT(1), 520 + .reg = TH1520_SUBSYS_RST_CFG, 521 + }, 522 + [TH1520_RESET_ID_VOSYS] = { 523 + .bit = BIT(2), 524 + .reg = TH1520_SUBSYS_RST_CFG, 525 + }, 526 + [TH1520_RESET_ID_VPSYS] = { 527 + .bit = BIT(3), 528 + .reg = TH1520_SUBSYS_RST_CFG, 529 + }, 530 + }; 531 + 532 + static const struct th1520_reset_map th1520_dsp_resets[] = { 533 + [TH1520_RESET_ID_X2X_DSP1] = { 534 + .bit = BIT(0), 535 + .reg = TH1520_DSPSYS_RST_CFG, 536 + }, 537 + [TH1520_RESET_ID_X2X_DSP0] = { 538 + .bit = BIT(1), 539 + .reg = TH1520_DSPSYS_RST_CFG, 540 + }, 541 + [TH1520_RESET_ID_X2X_SLAVE_DSP1] = { 542 + .bit = BIT(2), 543 + .reg = TH1520_DSPSYS_RST_CFG, 544 + }, 545 + [TH1520_RESET_ID_X2X_SLAVE_DSP0] = { 546 + .bit = BIT(3), 547 + .reg = TH1520_DSPSYS_RST_CFG, 548 + }, 549 + [TH1520_RESET_ID_DSP0_CORE] = { 550 + .bit = BIT(8), 551 + .reg = TH1520_DSPSYS_RST_CFG, 552 + }, 553 + [TH1520_RESET_ID_DSP0_DEBUG] = { 554 + .bit = BIT(9), 555 + .reg = TH1520_DSPSYS_RST_CFG, 556 + }, 557 + [TH1520_RESET_ID_DSP0_APB] = { 558 + .bit = BIT(10), 559 + .reg = TH1520_DSPSYS_RST_CFG, 560 + }, 561 + [TH1520_RESET_ID_DSP1_CORE] = { 562 + .bit = BIT(12), 563 + .reg = TH1520_DSPSYS_RST_CFG, 564 + }, 565 + [TH1520_RESET_ID_DSP1_DEBUG] = { 566 + .bit = BIT(13), 567 + .reg = TH1520_DSPSYS_RST_CFG, 568 + }, 569 + [TH1520_RESET_ID_DSP1_APB] = { 570 + .bit = BIT(14), 571 + .reg = TH1520_DSPSYS_RST_CFG, 572 + }, 573 + [TH1520_RESET_ID_DSPSYS_APB] = { 574 + .bit = BIT(16), 575 + .reg = TH1520_DSPSYS_RST_CFG, 576 + }, 577 + [TH1520_RESET_ID_AXI4_DSPSYS_SLV] = { 578 + .bit = BIT(20), 579 + .reg = TH1520_DSPSYS_RST_CFG, 580 + }, 581 + [TH1520_RESET_ID_AXI4_DSPSYS] = { 582 + .bit = BIT(24), 583 + .reg = TH1520_DSPSYS_RST_CFG, 584 + }, 585 + [TH1520_RESET_ID_AXI4_DSP_RS] = { 586 + .bit = BIT(26), 587 + .reg = TH1520_DSPSYS_RST_CFG, 588 + }, 589 + }; 590 + 591 + static const struct th1520_reset_map th1520_misc_resets[] = { 592 + [TH1520_RESET_ID_EMMC_SDIO_CLKGEN] = { 593 + .bit = BIT(0), 594 + .reg = TH1520_EMMC_RST_CFG, 595 + }, 596 + [TH1520_RESET_ID_EMMC] = { 597 + .bit = BIT(1), 598 + .reg = TH1520_EMMC_RST_CFG, 599 + }, 600 + [TH1520_RESET_ID_MISCSYS_AXI] = { 601 + .bit = BIT(0), 602 + .reg = TH1520_MISCSYS_AXI_RST_CFG, 603 + }, 604 + [TH1520_RESET_ID_MISCSYS_AXI_APB] = { 605 + .bit = BIT(1), 606 + .reg = TH1520_MISCSYS_AXI_RST_CFG, 607 + }, 608 + [TH1520_RESET_ID_SDIO0] = { 609 + .bit = BIT(0), 610 + .reg = TH1520_SDIO0_RST_CFG, 611 + }, 612 + [TH1520_RESET_ID_SDIO1] = { 613 + .bit = BIT(1), 614 + .reg = TH1520_SDIO1_RST_CFG, 615 + }, 616 + [TH1520_RESET_ID_USB3_APB] = { 617 + .bit = BIT(0), 618 + .reg = TH1520_USB3_DRD_RST_CFG, 619 + }, 620 + [TH1520_RESET_ID_USB3_PHY] = { 621 + .bit = BIT(1), 622 + .reg = TH1520_USB3_DRD_RST_CFG, 623 + }, 624 + [TH1520_RESET_ID_USB3_VCC] = { 625 + .bit = BIT(2), 626 + .reg = TH1520_USB3_DRD_RST_CFG, 627 + }, 628 + }; 629 + 630 + static const struct th1520_reset_map th1520_vi_resets[] = { 631 + [TH1520_RESET_ID_ISP0] = { 632 + .bit = BIT(0), 633 + .reg = TH1520_VISYS_RST_CFG, 634 + }, 635 + [TH1520_RESET_ID_ISP1] = { 636 + .bit = BIT(4), 637 + .reg = TH1520_VISYS_RST_CFG, 638 + }, 639 + [TH1520_RESET_ID_CSI0_APB] = { 640 + .bit = BIT(16), 641 + .reg = TH1520_VISYS_RST_CFG, 642 + }, 643 + [TH1520_RESET_ID_CSI1_APB] = { 644 + .bit = BIT(17), 645 + .reg = TH1520_VISYS_RST_CFG, 646 + }, 647 + [TH1520_RESET_ID_CSI2_APB] = { 648 + .bit = BIT(18), 649 + .reg = TH1520_VISYS_RST_CFG, 650 + }, 651 + [TH1520_RESET_ID_MIPI_FIFO] = { 652 + .bit = BIT(20), 653 + .reg = TH1520_VISYS_RST_CFG, 654 + }, 655 + [TH1520_RESET_ID_ISP_VENC_APB] = { 656 + .bit = BIT(24), 657 + .reg = TH1520_VISYS_RST_CFG, 658 + }, 659 + [TH1520_RESET_ID_VIPRE_APB] = { 660 + .bit = BIT(28), 661 + .reg = TH1520_VISYS_RST_CFG, 662 + }, 663 + [TH1520_RESET_ID_VIPRE_AXI] = { 664 + .bit = BIT(29), 665 + .reg = TH1520_VISYS_RST_CFG, 666 + }, 667 + [TH1520_RESET_ID_DW200_APB] = { 668 + .bit = BIT(31), 669 + .reg = TH1520_VISYS_RST_CFG, 670 + }, 671 + [TH1520_RESET_ID_VISYS3_AXI] = { 672 + .bit = BIT(8), 673 + .reg = TH1520_VISYS_2_RST_CFG, 674 + }, 675 + [TH1520_RESET_ID_VISYS2_AXI] = { 676 + .bit = BIT(9), 677 + .reg = TH1520_VISYS_2_RST_CFG, 678 + }, 679 + [TH1520_RESET_ID_VISYS1_AXI] = { 680 + .bit = BIT(10), 681 + .reg = TH1520_VISYS_2_RST_CFG, 682 + }, 683 + [TH1520_RESET_ID_VISYS_AXI] = { 684 + .bit = BIT(12), 685 + .reg = TH1520_VISYS_2_RST_CFG, 686 + }, 687 + [TH1520_RESET_ID_VISYS_APB] = { 688 + .bit = BIT(16), 689 + .reg = TH1520_VISYS_2_RST_CFG, 690 + }, 691 + [TH1520_RESET_ID_ISP_VENC_AXI] = { 692 + .bit = BIT(20), 693 + .reg = TH1520_VISYS_2_RST_CFG, 694 + }, 695 + }; 696 + 697 + static const struct th1520_reset_map th1520_vp_resets[] = { 698 + [TH1520_RESET_ID_VPSYS_AXI_APB] = { 699 + .bit = BIT(0), 700 + .reg = TH1520_AXIBUS_RST_CFG, 701 + }, 702 + [TH1520_RESET_ID_VPSYS_AXI] = { 703 + .bit = BIT(1), 704 + .reg = TH1520_AXIBUS_RST_CFG, 705 + }, 706 + [TH1520_RESET_ID_FCE_APB] = { 707 + .bit = BIT(0), 708 + .reg = TH1520_FCE_RST_CFG, 709 + }, 710 + [TH1520_RESET_ID_FCE_CORE] = { 711 + .bit = BIT(1), 712 + .reg = TH1520_FCE_RST_CFG, 713 + }, 714 + [TH1520_RESET_ID_FCE_X2X_MASTER] = { 715 + .bit = BIT(4), 716 + .reg = TH1520_FCE_RST_CFG, 717 + }, 718 + [TH1520_RESET_ID_FCE_X2X_SLAVE] = { 719 + .bit = BIT(5), 720 + .reg = TH1520_FCE_RST_CFG, 721 + }, 722 + [TH1520_RESET_ID_G2D_APB] = { 723 + .bit = BIT(0), 724 + .reg = TH1520_G2D_RST_CFG, 725 + }, 726 + [TH1520_RESET_ID_G2D_ACLK] = { 727 + .bit = BIT(1), 728 + .reg = TH1520_G2D_RST_CFG, 729 + }, 730 + [TH1520_RESET_ID_G2D_CORE] = { 731 + .bit = BIT(2), 732 + .reg = TH1520_G2D_RST_CFG, 733 + }, 734 + [TH1520_RESET_ID_VDEC_APB] = { 735 + .bit = BIT(0), 736 + .reg = TH1520_VDEC_RST_CFG, 737 + }, 738 + [TH1520_RESET_ID_VDEC_ACLK] = { 739 + .bit = BIT(1), 740 + .reg = TH1520_VDEC_RST_CFG, 741 + }, 742 + [TH1520_RESET_ID_VDEC_CORE] = { 743 + .bit = BIT(2), 744 + .reg = TH1520_VDEC_RST_CFG, 745 + }, 746 + [TH1520_RESET_ID_VENC_APB] = { 747 + .bit = BIT(0), 748 + .reg = TH1520_VENC_RST_CFG, 749 + }, 750 + [TH1520_RESET_ID_VENC_CORE] = { 751 + .bit = BIT(1), 752 + .reg = TH1520_VENC_RST_CFG, 753 + }, 173 754 }; 174 755 175 756 static inline struct th1520_reset_priv * ··· 859 90 struct th1520_reset_priv *priv = to_th1520_reset(rcdev); 860 91 const struct th1520_reset_map *reset; 861 92 862 - reset = &th1520_resets[id]; 93 + reset = &priv->resets[id]; 863 94 864 95 return regmap_update_bits(priv->map, reset->reg, reset->bit, 0); 865 96 } ··· 870 101 struct th1520_reset_priv *priv = to_th1520_reset(rcdev); 871 102 const struct th1520_reset_map *reset; 872 103 873 - reset = &th1520_resets[id]; 104 + reset = &priv->resets[id]; 874 105 875 106 return regmap_update_bits(priv->map, reset->reg, reset->bit, 876 107 reset->bit); ··· 889 120 890 121 static int th1520_reset_probe(struct platform_device *pdev) 891 122 { 123 + const struct th1520_reset_data *data; 892 124 struct device *dev = &pdev->dev; 893 125 struct th1520_reset_priv *priv; 894 126 void __iomem *base; 895 127 int ret; 128 + 129 + data = device_get_match_data(dev); 896 130 897 131 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 898 132 if (!priv) ··· 910 138 if (IS_ERR(priv->map)) 911 139 return PTR_ERR(priv->map); 912 140 913 - /* Initialize GPU resets to asserted state */ 914 - ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG, 915 - TH1520_GPU_RST_CFG_MASK, 0); 916 - if (ret) 917 - return ret; 141 + if (of_device_is_compatible(dev->of_node, "thead,th1520-reset")) { 142 + /* Initialize GPU resets to asserted state */ 143 + ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG, 144 + TH1520_GPU_RST_CFG_MASK, 0); 145 + if (ret) 146 + return ret; 147 + } 918 148 919 149 priv->rcdev.owner = THIS_MODULE; 920 - priv->rcdev.nr_resets = ARRAY_SIZE(th1520_resets); 150 + priv->rcdev.nr_resets = data->num; 921 151 priv->rcdev.ops = &th1520_reset_ops; 922 152 priv->rcdev.of_node = dev->of_node; 153 + 154 + priv->resets = data->resets; 923 155 924 156 return devm_reset_controller_register(dev, &priv->rcdev); 925 157 } 926 158 159 + static const struct th1520_reset_data th1520_reset_data = { 160 + .resets = th1520_resets, 161 + .num = ARRAY_SIZE(th1520_resets), 162 + }; 163 + 164 + static const struct th1520_reset_data th1520_ap_reset_data = { 165 + .resets = th1520_ap_resets, 166 + .num = ARRAY_SIZE(th1520_ap_resets), 167 + }; 168 + 169 + static const struct th1520_reset_data th1520_dsp_reset_data = { 170 + .resets = th1520_dsp_resets, 171 + .num = ARRAY_SIZE(th1520_dsp_resets), 172 + }; 173 + 174 + static const struct th1520_reset_data th1520_misc_reset_data = { 175 + .resets = th1520_misc_resets, 176 + .num = ARRAY_SIZE(th1520_misc_resets), 177 + }; 178 + 179 + static const struct th1520_reset_data th1520_vi_reset_data = { 180 + .resets = th1520_vi_resets, 181 + .num = ARRAY_SIZE(th1520_vi_resets), 182 + }; 183 + 184 + static const struct th1520_reset_data th1520_vp_reset_data = { 185 + .resets = th1520_vp_resets, 186 + .num = ARRAY_SIZE(th1520_vp_resets), 187 + }; 188 + 927 189 static const struct of_device_id th1520_reset_match[] = { 928 - { .compatible = "thead,th1520-reset" }, 190 + { .compatible = "thead,th1520-reset", .data = &th1520_reset_data }, 191 + { .compatible = "thead,th1520-reset-ap", .data = &th1520_ap_reset_data }, 192 + { .compatible = "thead,th1520-reset-dsp", .data = &th1520_dsp_reset_data }, 193 + { .compatible = "thead,th1520-reset-misc", .data = &th1520_misc_reset_data }, 194 + { .compatible = "thead,th1520-reset-vi", .data = &th1520_vi_reset_data }, 195 + { .compatible = "thead,th1520-reset-vp", .data = &th1520_vp_reset_data }, 929 196 { /* sentinel */ } 930 197 }; 931 198 MODULE_DEVICE_TABLE(of, th1520_reset_match);

+298

include/dt-bindings/reset/eswin,eic7700-reset.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. 4 + * All rights reserved. 5 + * 6 + * Device Tree binding constants for EIC7700 reset controller. 7 + * 8 + * Authors: 9 + * Yifeng Huang <huangyifeng@eswincomputing.com> 10 + * Xuyang Dong <dongxuyang@eswincomputing.com> 11 + */ 12 + 13 + #ifndef __DT_ESWIN_EIC7700_RESET_H__ 14 + #define __DT_ESWIN_EIC7700_RESET_H__ 15 + 16 + #define EIC7700_RESET_NOC_NSP 0 17 + #define EIC7700_RESET_NOC_CFG 1 18 + #define EIC7700_RESET_RNOC_NSP 2 19 + #define EIC7700_RESET_SNOC_TCU 3 20 + #define EIC7700_RESET_SNOC_U84 4 21 + #define EIC7700_RESET_SNOC_PCIE_XSR 5 22 + #define EIC7700_RESET_SNOC_PCIE_XMR 6 23 + #define EIC7700_RESET_SNOC_PCIE_PR 7 24 + #define EIC7700_RESET_SNOC_NPU 8 25 + #define EIC7700_RESET_SNOC_JTAG 9 26 + #define EIC7700_RESET_SNOC_DSP 10 27 + #define EIC7700_RESET_SNOC_DDRC1_P2 11 28 + #define EIC7700_RESET_SNOC_DDRC1_P1 12 29 + #define EIC7700_RESET_SNOC_DDRC0_P2 13 30 + #define EIC7700_RESET_SNOC_DDRC0_P1 14 31 + #define EIC7700_RESET_SNOC_D2D 15 32 + #define EIC7700_RESET_SNOC_AON 16 33 + #define EIC7700_RESET_GPU_AXI 17 34 + #define EIC7700_RESET_GPU_CFG 18 35 + #define EIC7700_RESET_GPU_GRAY 19 36 + #define EIC7700_RESET_GPU_JONES 20 37 + #define EIC7700_RESET_GPU_SPU 21 38 + #define EIC7700_RESET_DSP_AXI 22 39 + #define EIC7700_RESET_DSP_CFG 23 40 + #define EIC7700_RESET_DSP_DIV4 24 41 + #define EIC7700_RESET_DSP_DIV0 25 42 + #define EIC7700_RESET_DSP_DIV1 26 43 + #define EIC7700_RESET_DSP_DIV2 27 44 + #define EIC7700_RESET_DSP_DIV3 28 45 + #define EIC7700_RESET_D2D_AXI 29 46 + #define EIC7700_RESET_D2D_CFG 30 47 + #define EIC7700_RESET_D2D_PRST 31 48 + #define EIC7700_RESET_D2D_RAW_PCS 32 49 + #define EIC7700_RESET_D2D_RX 33 50 + #define EIC7700_RESET_D2D_TX 34 51 + #define EIC7700_RESET_D2D_CORE 35 52 + #define EIC7700_RESET_DDR1_ARST 36 53 + #define EIC7700_RESET_DDR1_TRACE 37 54 + #define EIC7700_RESET_DDR0_ARST 38 55 + #define EIC7700_RESET_DDR_CFG 39 56 + #define EIC7700_RESET_DDR0_TRACE 40 57 + #define EIC7700_RESET_DDR_CORE 41 58 + #define EIC7700_RESET_DDR_PRST 42 59 + #define EIC7700_RESET_TCU_AXI 43 60 + #define EIC7700_RESET_TCU_CFG 44 61 + #define EIC7700_RESET_TCU_TBU0 45 62 + #define EIC7700_RESET_TCU_TBU1 46 63 + #define EIC7700_RESET_TCU_TBU2 47 64 + #define EIC7700_RESET_TCU_TBU3 48 65 + #define EIC7700_RESET_TCU_TBU4 49 66 + #define EIC7700_RESET_TCU_TBU5 50 67 + #define EIC7700_RESET_TCU_TBU6 51 68 + #define EIC7700_RESET_TCU_TBU7 52 69 + #define EIC7700_RESET_TCU_TBU8 53 70 + #define EIC7700_RESET_TCU_TBU9 54 71 + #define EIC7700_RESET_TCU_TBU10 55 72 + #define EIC7700_RESET_TCU_TBU11 56 73 + #define EIC7700_RESET_TCU_TBU12 57 74 + #define EIC7700_RESET_TCU_TBU13 58 75 + #define EIC7700_RESET_TCU_TBU14 59 76 + #define EIC7700_RESET_TCU_TBU15 60 77 + #define EIC7700_RESET_TCU_TBU16 61 78 + #define EIC7700_RESET_NPU_AXI 62 79 + #define EIC7700_RESET_NPU_CFG 63 80 + #define EIC7700_RESET_NPU_CORE 64 81 + #define EIC7700_RESET_NPU_E31CORE 65 82 + #define EIC7700_RESET_NPU_E31BUS 66 83 + #define EIC7700_RESET_NPU_E31DBG 67 84 + #define EIC7700_RESET_NPU_LLC 68 85 + #define EIC7700_RESET_HSP_AXI 69 86 + #define EIC7700_RESET_HSP_CFG 70 87 + #define EIC7700_RESET_HSP_POR 71 88 + #define EIC7700_RESET_MSHC0_PHY 72 89 + #define EIC7700_RESET_MSHC1_PHY 73 90 + #define EIC7700_RESET_MSHC2_PHY 74 91 + #define EIC7700_RESET_MSHC0_TXRX 75 92 + #define EIC7700_RESET_MSHC1_TXRX 76 93 + #define EIC7700_RESET_MSHC2_TXRX 77 94 + #define EIC7700_RESET_SATA_ASIC0 78 95 + #define EIC7700_RESET_SATA_OOB 79 96 + #define EIC7700_RESET_SATA_PMALIVE 80 97 + #define EIC7700_RESET_SATA_RBC 81 98 + #define EIC7700_RESET_DMA0 82 99 + #define EIC7700_RESET_HSP_DMA 83 100 + #define EIC7700_RESET_USB0_VAUX 84 101 + #define EIC7700_RESET_USB1_VAUX 85 102 + #define EIC7700_RESET_HSP_SD1_PRST 86 103 + #define EIC7700_RESET_HSP_SD0_PRST 87 104 + #define EIC7700_RESET_HSP_EMMC_PRST 88 105 + #define EIC7700_RESET_HSP_DMA_PRST 89 106 + #define EIC7700_RESET_HSP_SD1_ARST 90 107 + #define EIC7700_RESET_HSP_SD0_ARST 91 108 + #define EIC7700_RESET_HSP_EMMC_ARST 92 109 + #define EIC7700_RESET_HSP_DMA_ARST 93 110 + #define EIC7700_RESET_HSP_ETH1_ARST 94 111 + #define EIC7700_RESET_HSP_ETH0_ARST 95 112 + #define EIC7700_RESET_SATA_ARST 96 113 + #define EIC7700_RESET_PCIE_CFG 97 114 + #define EIC7700_RESET_PCIE_POWEUP 98 115 + #define EIC7700_RESET_PCIE_PERST 99 116 + #define EIC7700_RESET_I2C0 100 117 + #define EIC7700_RESET_I2C1 101 118 + #define EIC7700_RESET_I2C2 102 119 + #define EIC7700_RESET_I2C3 103 120 + #define EIC7700_RESET_I2C4 104 121 + #define EIC7700_RESET_I2C5 105 122 + #define EIC7700_RESET_I2C6 106 123 + #define EIC7700_RESET_I2C7 107 124 + #define EIC7700_RESET_I2C8 108 125 + #define EIC7700_RESET_I2C9 109 126 + #define EIC7700_RESET_FAN 110 127 + #define EIC7700_RESET_PVT0 111 128 + #define EIC7700_RESET_PVT1 112 129 + #define EIC7700_RESET_MBOX0 113 130 + #define EIC7700_RESET_MBOX1 114 131 + #define EIC7700_RESET_MBOX2 115 132 + #define EIC7700_RESET_MBOX3 116 133 + #define EIC7700_RESET_MBOX4 117 134 + #define EIC7700_RESET_MBOX5 118 135 + #define EIC7700_RESET_MBOX6 119 136 + #define EIC7700_RESET_MBOX7 120 137 + #define EIC7700_RESET_MBOX8 121 138 + #define EIC7700_RESET_MBOX9 122 139 + #define EIC7700_RESET_MBOX10 123 140 + #define EIC7700_RESET_MBOX11 124 141 + #define EIC7700_RESET_MBOX12 125 142 + #define EIC7700_RESET_MBOX13 126 143 + #define EIC7700_RESET_MBOX14 127 144 + #define EIC7700_RESET_MBOX15 128 145 + #define EIC7700_RESET_UART0 129 146 + #define EIC7700_RESET_UART1 130 147 + #define EIC7700_RESET_UART2 131 148 + #define EIC7700_RESET_UART3 132 149 + #define EIC7700_RESET_UART4 133 150 + #define EIC7700_RESET_GPIO0 134 151 + #define EIC7700_RESET_GPIO1 135 152 + #define EIC7700_RESET_TIMER 136 153 + #define EIC7700_RESET_SSI0 137 154 + #define EIC7700_RESET_SSI1 138 155 + #define EIC7700_RESET_WDT0 139 156 + #define EIC7700_RESET_WDT1 140 157 + #define EIC7700_RESET_WDT2 141 158 + #define EIC7700_RESET_WDT3 142 159 + #define EIC7700_RESET_LSP_CFG 143 160 + #define EIC7700_RESET_U84_CORE0 144 161 + #define EIC7700_RESET_U84_CORE1 145 162 + #define EIC7700_RESET_U84_CORE2 146 163 + #define EIC7700_RESET_U84_CORE3 147 164 + #define EIC7700_RESET_U84_BUS 148 165 + #define EIC7700_RESET_U84_DBG 149 166 + #define EIC7700_RESET_U84_TRACECOM 150 167 + #define EIC7700_RESET_U84_TRACE0 151 168 + #define EIC7700_RESET_U84_TRACE1 152 169 + #define EIC7700_RESET_U84_TRACE2 153 170 + #define EIC7700_RESET_U84_TRACE3 154 171 + #define EIC7700_RESET_SCPU_CORE 155 172 + #define EIC7700_RESET_SCPU_BUS 156 173 + #define EIC7700_RESET_SCPU_DBG 157 174 + #define EIC7700_RESET_LPCPU_CORE 158 175 + #define EIC7700_RESET_LPCPU_BUS 159 176 + #define EIC7700_RESET_LPCPU_DBG 160 177 + #define EIC7700_RESET_VC_CFG 161 178 + #define EIC7700_RESET_VC_AXI 162 179 + #define EIC7700_RESET_VC_MONCFG 163 180 + #define EIC7700_RESET_JD_CFG 164 181 + #define EIC7700_RESET_JD_AXI 165 182 + #define EIC7700_RESET_JE_CFG 166 183 + #define EIC7700_RESET_JE_AXI 167 184 + #define EIC7700_RESET_VD_CFG 168 185 + #define EIC7700_RESET_VD_AXI 169 186 + #define EIC7700_RESET_VE_AXI 170 187 + #define EIC7700_RESET_VE_CFG 171 188 + #define EIC7700_RESET_G2D_CORE 172 189 + #define EIC7700_RESET_G2D_CFG 173 190 + #define EIC7700_RESET_G2D_AXI 174 191 + #define EIC7700_RESET_VI_AXI 175 192 + #define EIC7700_RESET_VI_CFG 176 193 + #define EIC7700_RESET_VI_DWE 177 194 + #define EIC7700_RESET_DVP 178 195 + #define EIC7700_RESET_ISP0 179 196 + #define EIC7700_RESET_ISP1 180 197 + #define EIC7700_RESET_SHUTTR0 181 198 + #define EIC7700_RESET_SHUTTR1 182 199 + #define EIC7700_RESET_SHUTTR2 183 200 + #define EIC7700_RESET_SHUTTR3 184 201 + #define EIC7700_RESET_SHUTTR4 185 202 + #define EIC7700_RESET_SHUTTR5 186 203 + #define EIC7700_RESET_VO_MIPI 187 204 + #define EIC7700_RESET_VO_PRST 188 205 + #define EIC7700_RESET_VO_HDMI_PRST 189 206 + #define EIC7700_RESET_VO_HDMI_PHY 190 207 + #define EIC7700_RESET_VO_HDMI 191 208 + #define EIC7700_RESET_VO_I2S 192 209 + #define EIC7700_RESET_VO_I2S_PRST 193 210 + #define EIC7700_RESET_VO_AXI 194 211 + #define EIC7700_RESET_VO_CFG 195 212 + #define EIC7700_RESET_VO_DC 196 213 + #define EIC7700_RESET_VO_DC_PRST 197 214 + #define EIC7700_RESET_BOOTSPI_HRST 198 215 + #define EIC7700_RESET_BOOTSPI 199 216 + #define EIC7700_RESET_ANO1 200 217 + #define EIC7700_RESET_ANO0 201 218 + #define EIC7700_RESET_DMA1_ARST 202 219 + #define EIC7700_RESET_DMA1_HRST 203 220 + #define EIC7700_RESET_FPRT 204 221 + #define EIC7700_RESET_HBLOCK 205 222 + #define EIC7700_RESET_SECSR 206 223 + #define EIC7700_RESET_OTP 207 224 + #define EIC7700_RESET_PKA 208 225 + #define EIC7700_RESET_SPACC 209 226 + #define EIC7700_RESET_TRNG 210 227 + #define EIC7700_RESET_TIMER0_0 211 228 + #define EIC7700_RESET_TIMER0_1 212 229 + #define EIC7700_RESET_TIMER0_2 213 230 + #define EIC7700_RESET_TIMER0_3 214 231 + #define EIC7700_RESET_TIMER0_4 215 232 + #define EIC7700_RESET_TIMER0_5 216 233 + #define EIC7700_RESET_TIMER0_6 217 234 + #define EIC7700_RESET_TIMER0_7 218 235 + #define EIC7700_RESET_TIMER0_N 219 236 + #define EIC7700_RESET_TIMER1_0 220 237 + #define EIC7700_RESET_TIMER1_1 221 238 + #define EIC7700_RESET_TIMER1_2 222 239 + #define EIC7700_RESET_TIMER1_3 223 240 + #define EIC7700_RESET_TIMER1_4 224 241 + #define EIC7700_RESET_TIMER1_5 225 242 + #define EIC7700_RESET_TIMER1_6 226 243 + #define EIC7700_RESET_TIMER1_7 227 244 + #define EIC7700_RESET_TIMER1_N 228 245 + #define EIC7700_RESET_TIMER2_0 229 246 + #define EIC7700_RESET_TIMER2_1 230 247 + #define EIC7700_RESET_TIMER2_2 231 248 + #define EIC7700_RESET_TIMER2_3 232 249 + #define EIC7700_RESET_TIMER2_4 233 250 + #define EIC7700_RESET_TIMER2_5 234 251 + #define EIC7700_RESET_TIMER2_6 235 252 + #define EIC7700_RESET_TIMER2_7 236 253 + #define EIC7700_RESET_TIMER2_N 237 254 + #define EIC7700_RESET_TIMER3_0 238 255 + #define EIC7700_RESET_TIMER3_1 239 256 + #define EIC7700_RESET_TIMER3_2 240 257 + #define EIC7700_RESET_TIMER3_3 241 258 + #define EIC7700_RESET_TIMER3_4 242 259 + #define EIC7700_RESET_TIMER3_5 243 260 + #define EIC7700_RESET_TIMER3_6 244 261 + #define EIC7700_RESET_TIMER3_7 245 262 + #define EIC7700_RESET_TIMER3_N 246 263 + #define EIC7700_RESET_RTC 247 264 + #define EIC7700_RESET_MNOC_SNOC_NSP 248 265 + #define EIC7700_RESET_MNOC_VC 249 266 + #define EIC7700_RESET_MNOC_CFG 250 267 + #define EIC7700_RESET_MNOC_HSP 251 268 + #define EIC7700_RESET_MNOC_GPU 252 269 + #define EIC7700_RESET_MNOC_DDRC1_P3 253 270 + #define EIC7700_RESET_MNOC_DDRC0_P3 254 271 + #define EIC7700_RESET_RNOC_VO 255 272 + #define EIC7700_RESET_RNOC_VI 256 273 + #define EIC7700_RESET_RNOC_SNOC_NSP 257 274 + #define EIC7700_RESET_RNOC_CFG 258 275 + #define EIC7700_RESET_MNOC_DDRC1_P4 259 276 + #define EIC7700_RESET_MNOC_DDRC0_P4 260 277 + #define EIC7700_RESET_CNOC_VO_CFG 261 278 + #define EIC7700_RESET_CNOC_VI_CFG 262 279 + #define EIC7700_RESET_CNOC_VC_CFG 263 280 + #define EIC7700_RESET_CNOC_TCU_CFG 264 281 + #define EIC7700_RESET_CNOC_PCIE_CFG 265 282 + #define EIC7700_RESET_CNOC_NPU_CFG 266 283 + #define EIC7700_RESET_CNOC_LSP_CFG 267 284 + #define EIC7700_RESET_CNOC_HSP_CFG 268 285 + #define EIC7700_RESET_CNOC_GPU_CFG 269 286 + #define EIC7700_RESET_CNOC_DSPT_CFG 270 287 + #define EIC7700_RESET_CNOC_DDRT1_CFG 271 288 + #define EIC7700_RESET_CNOC_DDRT0_CFG 272 289 + #define EIC7700_RESET_CNOC_D2D_CFG 273 290 + #define EIC7700_RESET_CNOC_CFG 274 291 + #define EIC7700_RESET_CNOC_CLMM_CFG 275 292 + #define EIC7700_RESET_CNOC_AON_CFG 276 293 + #define EIC7700_RESET_LNOC_CFG 277 294 + #define EIC7700_RESET_LNOC_NPU_LLC 278 295 + #define EIC7700_RESET_LNOC_DDRC1_P0 279 296 + #define EIC7700_RESET_LNOC_DDRC0_P0 280 297 + 298 + #endif /* __DT_ESWIN_EIC7700_RESET_H__ */

+216 -3

include/dt-bindings/reset/thead,th1520-reset.h

··· 7 7 #ifndef _DT_BINDINGS_TH1520_RESET_H 8 8 #define _DT_BINDINGS_TH1520_RESET_H 9 9 10 + /* AO Subsystem */ 11 + #define TH1520_RESET_ID_SYSTEM 0 12 + #define TH1520_RESET_ID_RTC_APB 1 13 + #define TH1520_RESET_ID_RTC_REF 2 14 + #define TH1520_RESET_ID_AOGPIO_DB 3 15 + #define TH1520_RESET_ID_AOGPIO_APB 4 16 + #define TH1520_RESET_ID_AOI2C_APB 5 17 + #define TH1520_RESET_ID_PVT_APB 6 18 + #define TH1520_RESET_ID_E902_CORE 7 19 + #define TH1520_RESET_ID_E902_HAD 8 20 + #define TH1520_RESET_ID_AOTIMER_APB 9 21 + #define TH1520_RESET_ID_AOTIMER_CORE 10 22 + #define TH1520_RESET_ID_AOWDT_APB 11 23 + #define TH1520_RESET_ID_APSYS 12 24 + #define TH1520_RESET_ID_NPUSYS 13 25 + #define TH1520_RESET_ID_DDRSYS 14 26 + #define TH1520_RESET_ID_AXI_AP2CP 15 27 + #define TH1520_RESET_ID_AXI_CP2AP 16 28 + #define TH1520_RESET_ID_AXI_CP2SRAM 17 29 + #define TH1520_RESET_ID_AUDSYS_CORE 18 30 + #define TH1520_RESET_ID_AUDSYS_IOPMP 19 31 + #define TH1520_RESET_ID_AUDSYS 20 32 + #define TH1520_RESET_ID_DSP0 21 33 + #define TH1520_RESET_ID_DSP1 22 34 + #define TH1520_RESET_ID_GPU_MODULE 23 35 + #define TH1520_RESET_ID_VDEC 24 36 + #define TH1520_RESET_ID_VENC 25 37 + #define TH1520_RESET_ID_ADC_APB 26 38 + #define TH1520_RESET_ID_AUDGPIO_DB 27 39 + #define TH1520_RESET_ID_AUDGPIO_APB 28 40 + #define TH1520_RESET_ID_AOUART_IF 29 41 + #define TH1520_RESET_ID_AOUART_APB 30 42 + #define TH1520_RESET_ID_SRAM_AXI_P0 31 43 + #define TH1520_RESET_ID_SRAM_AXI_P1 32 44 + #define TH1520_RESET_ID_SRAM_AXI_P2 33 45 + #define TH1520_RESET_ID_SRAM_AXI_P3 34 46 + #define TH1520_RESET_ID_SRAM_AXI_P4 35 47 + #define TH1520_RESET_ID_SRAM_AXI_CORE 36 48 + #define TH1520_RESET_ID_SE 37 49 + 50 + /* AP Subsystem */ 51 + #define TH1520_RESET_ID_BROM 0 52 + #define TH1520_RESET_ID_C910_TOP 1 53 + #define TH1520_RESET_ID_NPU 2 54 + #define TH1520_RESET_ID_WDT0 3 55 + #define TH1520_RESET_ID_WDT1 4 56 + #define TH1520_RESET_ID_C910_C0 5 57 + #define TH1520_RESET_ID_C910_C1 6 58 + #define TH1520_RESET_ID_C910_C2 7 59 + #define TH1520_RESET_ID_C910_C3 8 60 + #define TH1520_RESET_ID_CHIP_DBG_CORE 9 61 + #define TH1520_RESET_ID_CHIP_DBG_AXI 10 62 + #define TH1520_RESET_ID_AXI4_CPUSYS2_AXI 11 63 + #define TH1520_RESET_ID_AXI4_CPUSYS2_APB 12 64 + #define TH1520_RESET_ID_X2H_CPUSYS 13 65 + #define TH1520_RESET_ID_AHB2_CPUSYS 14 66 + #define TH1520_RESET_ID_APB3_CPUSYS 15 67 + #define TH1520_RESET_ID_MBOX0_APB 16 68 + #define TH1520_RESET_ID_MBOX1_APB 17 69 + #define TH1520_RESET_ID_MBOX2_APB 18 70 + #define TH1520_RESET_ID_MBOX3_APB 19 71 + #define TH1520_RESET_ID_TIMER0_APB 20 72 + #define TH1520_RESET_ID_TIMER0_CORE 21 73 + #define TH1520_RESET_ID_TIMER1_APB 22 74 + #define TH1520_RESET_ID_TIMER1_CORE 23 75 + #define TH1520_RESET_ID_PERISYS_AHB 24 76 + #define TH1520_RESET_ID_PERISYS_APB1 25 77 + #define TH1520_RESET_ID_PERISYS_APB2 26 78 + #define TH1520_RESET_ID_GMAC0_APB 27 79 + #define TH1520_RESET_ID_GMAC0_AHB 28 80 + #define TH1520_RESET_ID_GMAC0_CLKGEN 29 81 + #define TH1520_RESET_ID_GMAC0_AXI 30 82 + #define TH1520_RESET_ID_UART0_APB 31 83 + #define TH1520_RESET_ID_UART0_IF 32 84 + #define TH1520_RESET_ID_UART1_APB 33 85 + #define TH1520_RESET_ID_UART1_IF 34 86 + #define TH1520_RESET_ID_UART2_APB 35 87 + #define TH1520_RESET_ID_UART2_IF 36 88 + #define TH1520_RESET_ID_UART3_APB 37 89 + #define TH1520_RESET_ID_UART3_IF 38 90 + #define TH1520_RESET_ID_UART4_APB 39 91 + #define TH1520_RESET_ID_UART4_IF 40 92 + #define TH1520_RESET_ID_UART5_APB 41 93 + #define TH1520_RESET_ID_UART5_IF 42 94 + #define TH1520_RESET_ID_QSPI0_IF 43 95 + #define TH1520_RESET_ID_QSPI0_APB 44 96 + #define TH1520_RESET_ID_QSPI1_IF 45 97 + #define TH1520_RESET_ID_QSPI1_APB 46 98 + #define TH1520_RESET_ID_SPI_IF 47 99 + #define TH1520_RESET_ID_SPI_APB 48 100 + #define TH1520_RESET_ID_I2C0_APB 49 101 + #define TH1520_RESET_ID_I2C0_CORE 50 102 + #define TH1520_RESET_ID_I2C1_APB 51 103 + #define TH1520_RESET_ID_I2C1_CORE 52 104 + #define TH1520_RESET_ID_I2C2_APB 53 105 + #define TH1520_RESET_ID_I2C2_CORE 54 106 + #define TH1520_RESET_ID_I2C3_APB 55 107 + #define TH1520_RESET_ID_I2C3_CORE 56 108 + #define TH1520_RESET_ID_I2C4_APB 57 109 + #define TH1520_RESET_ID_I2C4_CORE 58 110 + #define TH1520_RESET_ID_I2C5_APB 59 111 + #define TH1520_RESET_ID_I2C5_CORE 60 112 + #define TH1520_RESET_ID_GPIO0_DB 61 113 + #define TH1520_RESET_ID_GPIO0_APB 62 114 + #define TH1520_RESET_ID_GPIO1_DB 63 115 + #define TH1520_RESET_ID_GPIO1_APB 64 116 + #define TH1520_RESET_ID_GPIO2_DB 65 117 + #define TH1520_RESET_ID_GPIO2_APB 66 118 + #define TH1520_RESET_ID_PWM_COUNTER 67 119 + #define TH1520_RESET_ID_PWM_APB 68 120 + #define TH1520_RESET_ID_PADCTRL0_APB 69 121 + #define TH1520_RESET_ID_CPU2PERI_X2H 70 122 + #define TH1520_RESET_ID_CPU2AON_X2H 71 123 + #define TH1520_RESET_ID_AON2CPU_A2X 72 124 + #define TH1520_RESET_ID_NPUSYS_AXI 73 125 + #define TH1520_RESET_ID_NPUSYS_AXI_APB 74 126 + #define TH1520_RESET_ID_CPU2VP_X2P 75 127 + #define TH1520_RESET_ID_CPU2VI_X2H 76 128 + #define TH1520_RESET_ID_BMU_AXI 77 129 + #define TH1520_RESET_ID_BMU_APB 78 130 + #define TH1520_RESET_ID_DMAC_CPUSYS_AXI 79 131 + #define TH1520_RESET_ID_DMAC_CPUSYS_AHB 80 132 + #define TH1520_RESET_ID_SPINLOCK 81 133 + #define TH1520_RESET_ID_CFG2TEE 82 134 + #define TH1520_RESET_ID_DSMART 83 135 + #define TH1520_RESET_ID_GPIO3_DB 84 136 + #define TH1520_RESET_ID_GPIO3_APB 85 137 + #define TH1520_RESET_ID_PERI_I2S 86 138 + #define TH1520_RESET_ID_PERI_APB3 87 139 + #define TH1520_RESET_ID_PERI2PERI1_APB 88 140 + #define TH1520_RESET_ID_VPSYS_APB 89 141 + #define TH1520_RESET_ID_PERISYS_APB4 90 142 + #define TH1520_RESET_ID_GMAC1_APB 91 143 + #define TH1520_RESET_ID_GMAC1_AHB 92 144 + #define TH1520_RESET_ID_GMAC1_CLKGEN 93 145 + #define TH1520_RESET_ID_GMAC1_AXI 94 146 + #define TH1520_RESET_ID_GMAC_AXI 95 147 + #define TH1520_RESET_ID_GMAC_AXI_APB 96 148 + #define TH1520_RESET_ID_PADCTRL1_APB 97 149 + #define TH1520_RESET_ID_VOSYS_AXI 98 150 + #define TH1520_RESET_ID_VOSYS_AXI_APB 99 151 + #define TH1520_RESET_ID_VOSYS_AXI_X2X 100 152 + #define TH1520_RESET_ID_MISC2VP_X2X 101 153 + #define TH1520_RESET_ID_DSPSYS 102 154 + #define TH1520_RESET_ID_VISYS 103 155 + #define TH1520_RESET_ID_VOSYS 104 156 + #define TH1520_RESET_ID_VPSYS 105 157 + 158 + /* DSP Subsystem */ 159 + #define TH1520_RESET_ID_X2X_DSP1 0 160 + #define TH1520_RESET_ID_X2X_DSP0 1 161 + #define TH1520_RESET_ID_X2X_SLAVE_DSP1 2 162 + #define TH1520_RESET_ID_X2X_SLAVE_DSP0 3 163 + #define TH1520_RESET_ID_DSP0_CORE 4 164 + #define TH1520_RESET_ID_DSP0_DEBUG 5 165 + #define TH1520_RESET_ID_DSP0_APB 6 166 + #define TH1520_RESET_ID_DSP1_CORE 7 167 + #define TH1520_RESET_ID_DSP1_DEBUG 8 168 + #define TH1520_RESET_ID_DSP1_APB 9 169 + #define TH1520_RESET_ID_DSPSYS_APB 10 170 + #define TH1520_RESET_ID_AXI4_DSPSYS_SLV 11 171 + #define TH1520_RESET_ID_AXI4_DSPSYS 12 172 + #define TH1520_RESET_ID_AXI4_DSP_RS 13 173 + 174 + /* MISC Subsystem */ 175 + #define TH1520_RESET_ID_EMMC_SDIO_CLKGEN 0 176 + #define TH1520_RESET_ID_EMMC 1 177 + #define TH1520_RESET_ID_MISCSYS_AXI 2 178 + #define TH1520_RESET_ID_MISCSYS_AXI_APB 3 179 + #define TH1520_RESET_ID_SDIO0 4 180 + #define TH1520_RESET_ID_SDIO1 5 181 + #define TH1520_RESET_ID_USB3_APB 6 182 + #define TH1520_RESET_ID_USB3_PHY 7 183 + #define TH1520_RESET_ID_USB3_VCC 8 184 + 185 + /* VI Subsystem */ 186 + #define TH1520_RESET_ID_ISP0 0 187 + #define TH1520_RESET_ID_ISP1 1 188 + #define TH1520_RESET_ID_CSI0_APB 2 189 + #define TH1520_RESET_ID_CSI1_APB 3 190 + #define TH1520_RESET_ID_CSI2_APB 4 191 + #define TH1520_RESET_ID_MIPI_FIFO 5 192 + #define TH1520_RESET_ID_ISP_VENC_APB 6 193 + #define TH1520_RESET_ID_VIPRE_APB 7 194 + #define TH1520_RESET_ID_VIPRE_AXI 8 195 + #define TH1520_RESET_ID_DW200_APB 9 196 + #define TH1520_RESET_ID_VISYS3_AXI 10 197 + #define TH1520_RESET_ID_VISYS2_AXI 11 198 + #define TH1520_RESET_ID_VISYS1_AXI 12 199 + #define TH1520_RESET_ID_VISYS_AXI 13 200 + #define TH1520_RESET_ID_VISYS_APB 14 201 + #define TH1520_RESET_ID_ISP_VENC_AXI 15 202 + 203 + /* VO Subsystem */ 10 204 #define TH1520_RESET_ID_GPU 0 11 205 #define TH1520_RESET_ID_GPU_CLKGEN 1 12 - #define TH1520_RESET_ID_NPU 2 13 - #define TH1520_RESET_ID_WDT0 3 14 - #define TH1520_RESET_ID_WDT1 4 15 206 #define TH1520_RESET_ID_DPU_AHB 5 16 207 #define TH1520_RESET_ID_DPU_AXI 6 17 208 #define TH1520_RESET_ID_DPU_CORE 7 ··· 210 19 #define TH1520_RESET_ID_DSI1_APB 9 211 20 #define TH1520_RESET_ID_HDMI 10 212 21 #define TH1520_RESET_ID_HDMI_APB 11 22 + #define TH1520_RESET_ID_VOAXI 12 23 + #define TH1520_RESET_ID_VOAXI_APB 13 24 + #define TH1520_RESET_ID_X2H_DPU_AXI 14 25 + #define TH1520_RESET_ID_X2H_DPU_AHB 15 26 + #define TH1520_RESET_ID_X2H_DPU1_AXI 16 27 + #define TH1520_RESET_ID_X2H_DPU1_AHB 17 28 + 29 + /* VP Subsystem */ 30 + #define TH1520_RESET_ID_VPSYS_AXI_APB 0 31 + #define TH1520_RESET_ID_VPSYS_AXI 1 32 + #define TH1520_RESET_ID_FCE_APB 2 33 + #define TH1520_RESET_ID_FCE_CORE 3 34 + #define TH1520_RESET_ID_FCE_X2X_MASTER 4 35 + #define TH1520_RESET_ID_FCE_X2X_SLAVE 5 36 + #define TH1520_RESET_ID_G2D_APB 6 37 + #define TH1520_RESET_ID_G2D_ACLK 7 38 + #define TH1520_RESET_ID_G2D_CORE 8 39 + #define TH1520_RESET_ID_VDEC_APB 9 40 + #define TH1520_RESET_ID_VDEC_ACLK 10 41 + #define TH1520_RESET_ID_VDEC_CORE 11 42 + #define TH1520_RESET_ID_VENC_APB 12 43 + #define TH1520_RESET_ID_VENC_CORE 13 213 44 214 45 #endif /* _DT_BINDINGS_TH1520_RESET_H */

-33

include/linux/reset-controller.h

··· 27 27 struct of_phandle_args; 28 28 29 29 /** 30 - * struct reset_control_lookup - represents a single lookup entry 31 - * 32 - * @list: internal list of all reset lookup entries 33 - * @provider: name of the reset controller device controlling this reset line 34 - * @index: ID of the reset controller in the reset controller device 35 - * @dev_id: name of the device associated with this reset line 36 - * @con_id: name of the reset line (can be NULL) 37 - */ 38 - struct reset_control_lookup { 39 - struct list_head list; 40 - const char *provider; 41 - unsigned int index; 42 - const char *dev_id; 43 - const char *con_id; 44 - }; 45 - 46 - #define RESET_LOOKUP(_provider, _index, _dev_id, _con_id) \ 47 - { \ 48 - .provider = _provider, \ 49 - .index = _index, \ 50 - .dev_id = _dev_id, \ 51 - .con_id = _con_id, \ 52 - } 53 - 54 - /** 55 30 * struct reset_controller_dev - reset controller entity that might 56 31 * provide multiple reset controls 57 32 * @ops: a pointer to device specific struct reset_control_ops ··· 65 90 struct device; 66 91 int devm_reset_controller_register(struct device *dev, 67 92 struct reset_controller_dev *rcdev); 68 - 69 - void reset_controller_add_lookup(struct reset_control_lookup *lookup, 70 - unsigned int num_entries); 71 93 #else 72 94 static inline int reset_controller_register(struct reset_controller_dev *rcdev) 73 95 { ··· 79 107 struct reset_controller_dev *rcdev) 80 108 { 81 109 return 0; 82 - } 83 - 84 - static inline void reset_controller_add_lookup(struct reset_control_lookup *lookup, 85 - unsigned int num_entries) 86 - { 87 110 } 88 111 #endif 89 112

+1

include/linux/reset.h

··· 2 2 #ifndef _LINUX_RESET_H_ 3 3 #define _LINUX_RESET_H_ 4 4 5 + #include <linux/bits.h> 5 6 #include <linux/err.h> 6 7 #include <linux/errno.h> 7 8 #include <linux/types.h>