crypto: atmel-{aes,sha,tdes} - Group common alg type init in dedicated methods

+18 -64

drivers/crypto/atmel-aes.c

··· 1288 1288 { 1289 1289 .base.cra_name = "ecb(aes)", 1290 1290 .base.cra_driver_name = "atmel-ecb-aes", 1291 - .base.cra_priority = ATMEL_AES_PRIORITY, 1292 - .base.cra_flags = CRYPTO_ALG_ASYNC, 1293 1291 .base.cra_blocksize = AES_BLOCK_SIZE, 1294 1292 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx), 1295 - .base.cra_alignmask = 0xf, 1296 - .base.cra_module = THIS_MODULE, 1297 1293 1298 1294 .init = atmel_aes_init_tfm, 1299 1295 .min_keysize = AES_MIN_KEY_SIZE, ··· 1301 1305 { 1302 1306 .base.cra_name = "cbc(aes)", 1303 1307 .base.cra_driver_name = "atmel-cbc-aes", 1304 - .base.cra_priority = ATMEL_AES_PRIORITY, 1305 - .base.cra_flags = CRYPTO_ALG_ASYNC, 1306 1308 .base.cra_blocksize = AES_BLOCK_SIZE, 1307 1309 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx), 1308 - .base.cra_alignmask = 0xf, 1309 - .base.cra_module = THIS_MODULE, 1310 1310 1311 1311 .init = atmel_aes_init_tfm, 1312 1312 .min_keysize = AES_MIN_KEY_SIZE, ··· 1315 1323 { 1316 1324 .base.cra_name = "ofb(aes)", 1317 1325 .base.cra_driver_name = "atmel-ofb-aes", 1318 - .base.cra_priority = ATMEL_AES_PRIORITY, 1319 - .base.cra_flags = CRYPTO_ALG_ASYNC, 1320 1326 .base.cra_blocksize = AES_BLOCK_SIZE, 1321 1327 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx), 1322 - .base.cra_alignmask = 0xf, 1323 - .base.cra_module = THIS_MODULE, 1324 1328 1325 1329 .init = atmel_aes_init_tfm, 1326 1330 .min_keysize = AES_MIN_KEY_SIZE, ··· 1329 1341 { 1330 1342 .base.cra_name = "cfb(aes)", 1331 1343 .base.cra_driver_name = "atmel-cfb-aes", 1332 - .base.cra_priority = ATMEL_AES_PRIORITY, 1333 - .base.cra_flags = CRYPTO_ALG_ASYNC, 1334 1344 .base.cra_blocksize = AES_BLOCK_SIZE, 1335 1345 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx), 1336 - .base.cra_alignmask = 0xf, 1337 - .base.cra_module = THIS_MODULE, 1338 1346 1339 1347 .init = atmel_aes_init_tfm, 1340 1348 .min_keysize = AES_MIN_KEY_SIZE, ··· 1343 1359 { 1344 1360 .base.cra_name = "cfb32(aes)", 1345 1361 .base.cra_driver_name = "atmel-cfb32-aes", 1346 - .base.cra_priority = ATMEL_AES_PRIORITY, 1347 - .base.cra_flags = CRYPTO_ALG_ASYNC, 1348 1362 .base.cra_blocksize = CFB32_BLOCK_SIZE, 1349 1363 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx), 1350 - .base.cra_alignmask = 0xf, 1351 - .base.cra_module = THIS_MODULE, 1352 1364 1353 1365 .init = atmel_aes_init_tfm, 1354 1366 .min_keysize = AES_MIN_KEY_SIZE, ··· 1357 1377 { 1358 1378 .base.cra_name = "cfb16(aes)", 1359 1379 .base.cra_driver_name = "atmel-cfb16-aes", 1360 - .base.cra_priority = ATMEL_AES_PRIORITY, 1361 - .base.cra_flags = CRYPTO_ALG_ASYNC, 1362 1380 .base.cra_blocksize = CFB16_BLOCK_SIZE, 1363 1381 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx), 1364 - .base.cra_alignmask = 0xf, 1365 - .base.cra_module = THIS_MODULE, 1366 1382 1367 1383 .init = atmel_aes_init_tfm, 1368 1384 .min_keysize = AES_MIN_KEY_SIZE, ··· 1371 1395 { 1372 1396 .base.cra_name = "cfb8(aes)", 1373 1397 .base.cra_driver_name = "atmel-cfb8-aes", 1374 - .base.cra_priority = ATMEL_AES_PRIORITY, 1375 - .base.cra_flags = CRYPTO_ALG_ASYNC, 1376 1398 .base.cra_blocksize = CFB8_BLOCK_SIZE, 1377 1399 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx), 1378 - .base.cra_alignmask = 0xf, 1379 - .base.cra_module = THIS_MODULE, 1380 1400 1381 1401 .init = atmel_aes_init_tfm, 1382 1402 .min_keysize = AES_MIN_KEY_SIZE, ··· 1385 1413 { 1386 1414 .base.cra_name = "ctr(aes)", 1387 1415 .base.cra_driver_name = "atmel-ctr-aes", 1388 - .base.cra_priority = ATMEL_AES_PRIORITY, 1389 - .base.cra_flags = CRYPTO_ALG_ASYNC, 1390 1416 .base.cra_blocksize = 1, 1391 1417 .base.cra_ctxsize = sizeof(struct atmel_aes_ctr_ctx), 1392 - .base.cra_alignmask = 0xf, 1393 - .base.cra_module = THIS_MODULE, 1394 1418 1395 1419 .init = atmel_aes_ctr_init_tfm, 1396 1420 .min_keysize = AES_MIN_KEY_SIZE, ··· 1401 1433 static struct skcipher_alg aes_cfb64_alg = { 1402 1434 .base.cra_name = "cfb64(aes)", 1403 1435 .base.cra_driver_name = "atmel-cfb64-aes", 1404 - .base.cra_priority = ATMEL_AES_PRIORITY, 1405 - .base.cra_flags = CRYPTO_ALG_ASYNC, 1406 1436 .base.cra_blocksize = CFB64_BLOCK_SIZE, 1407 1437 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx), 1408 - .base.cra_alignmask = 0xf, 1409 - .base.cra_module = THIS_MODULE, 1410 1438 1411 1439 .init = atmel_aes_init_tfm, 1412 1440 .min_keysize = AES_MIN_KEY_SIZE, ··· 1788 1824 .base = { 1789 1825 .cra_name = "gcm(aes)", 1790 1826 .cra_driver_name = "atmel-gcm-aes", 1791 - .cra_priority = ATMEL_AES_PRIORITY, 1792 - .cra_flags = CRYPTO_ALG_ASYNC, 1793 1827 .cra_blocksize = 1, 1794 1828 .cra_ctxsize = sizeof(struct atmel_aes_gcm_ctx), 1795 - .cra_alignmask = 0xf, 1796 - .cra_module = THIS_MODULE, 1797 1829 }, 1798 1830 }; 1799 1831 ··· 1906 1946 static struct skcipher_alg aes_xts_alg = { 1907 1947 .base.cra_name = "xts(aes)", 1908 1948 .base.cra_driver_name = "atmel-xts-aes", 1909 - .base.cra_priority = ATMEL_AES_PRIORITY, 1910 - .base.cra_flags = CRYPTO_ALG_ASYNC, 1911 1949 .base.cra_blocksize = AES_BLOCK_SIZE, 1912 1950 .base.cra_ctxsize = sizeof(struct atmel_aes_xts_ctx), 1913 - .base.cra_alignmask = 0xf, 1914 - .base.cra_module = THIS_MODULE, 1915 1951 1916 1952 .min_keysize = 2 * AES_MIN_KEY_SIZE, 1917 1953 .max_keysize = 2 * AES_MAX_KEY_SIZE, ··· 2207 2251 .base = { 2208 2252 .cra_name = "authenc(hmac(sha1),cbc(aes))", 2209 2253 .cra_driver_name = "atmel-authenc-hmac-sha1-cbc-aes", 2210 - .cra_priority = ATMEL_AES_PRIORITY, 2211 - .cra_flags = CRYPTO_ALG_ASYNC, 2212 2254 .cra_blocksize = AES_BLOCK_SIZE, 2213 2255 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx), 2214 - .cra_alignmask = 0xf, 2215 - .cra_module = THIS_MODULE, 2216 2256 }, 2217 2257 }, 2218 2258 { ··· 2223 2271 .base = { 2224 2272 .cra_name = "authenc(hmac(sha224),cbc(aes))", 2225 2273 .cra_driver_name = "atmel-authenc-hmac-sha224-cbc-aes", 2226 - .cra_priority = ATMEL_AES_PRIORITY, 2227 - .cra_flags = CRYPTO_ALG_ASYNC, 2228 2274 .cra_blocksize = AES_BLOCK_SIZE, 2229 2275 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx), 2230 - .cra_alignmask = 0xf, 2231 - .cra_module = THIS_MODULE, 2232 2276 }, 2233 2277 }, 2234 2278 { ··· 2239 2291 .base = { 2240 2292 .cra_name = "authenc(hmac(sha256),cbc(aes))", 2241 2293 .cra_driver_name = "atmel-authenc-hmac-sha256-cbc-aes", 2242 - .cra_priority = ATMEL_AES_PRIORITY, 2243 - .cra_flags = CRYPTO_ALG_ASYNC, 2244 2294 .cra_blocksize = AES_BLOCK_SIZE, 2245 2295 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx), 2246 - .cra_alignmask = 0xf, 2247 - .cra_module = THIS_MODULE, 2248 2296 }, 2249 2297 }, 2250 2298 { ··· 2255 2311 .base = { 2256 2312 .cra_name = "authenc(hmac(sha384),cbc(aes))", 2257 2313 .cra_driver_name = "atmel-authenc-hmac-sha384-cbc-aes", 2258 - .cra_priority = ATMEL_AES_PRIORITY, 2259 - .cra_flags = CRYPTO_ALG_ASYNC, 2260 2314 .cra_blocksize = AES_BLOCK_SIZE, 2261 2315 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx), 2262 - .cra_alignmask = 0xf, 2263 - .cra_module = THIS_MODULE, 2264 2316 }, 2265 2317 }, 2266 2318 { ··· 2271 2331 .base = { 2272 2332 .cra_name = "authenc(hmac(sha512),cbc(aes))", 2273 2333 .cra_driver_name = "atmel-authenc-hmac-sha512-cbc-aes", 2274 - .cra_priority = ATMEL_AES_PRIORITY, 2275 - .cra_flags = CRYPTO_ALG_ASYNC, 2276 2334 .cra_blocksize = AES_BLOCK_SIZE, 2277 2335 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx), 2278 - .cra_alignmask = 0xf, 2279 - .cra_module = THIS_MODULE, 2280 2336 }, 2281 2337 }, 2282 2338 }; ··· 2388 2452 crypto_unregister_skcipher(&aes_algs[i]); 2389 2453 } 2390 2454 2455 + static void atmel_aes_crypto_alg_init(struct crypto_alg *alg) 2456 + { 2457 + alg->cra_flags = CRYPTO_ALG_ASYNC; 2458 + alg->cra_alignmask = 0xf; 2459 + alg->cra_priority = ATMEL_AES_PRIORITY; 2460 + alg->cra_module = THIS_MODULE; 2461 + } 2462 + 2391 2463 static int atmel_aes_register_algs(struct atmel_aes_dev *dd) 2392 2464 { 2393 2465 int err, i, j; 2394 2466 2395 2467 for (i = 0; i < ARRAY_SIZE(aes_algs); i++) { 2468 + atmel_aes_crypto_alg_init(&aes_algs[i].base); 2469 + 2396 2470 err = crypto_register_skcipher(&aes_algs[i]); 2397 2471 if (err) 2398 2472 goto err_aes_algs; 2399 2473 } 2400 2474 2401 2475 if (dd->caps.has_cfb64) { 2476 + atmel_aes_crypto_alg_init(&aes_cfb64_alg.base); 2477 + 2402 2478 err = crypto_register_skcipher(&aes_cfb64_alg); 2403 2479 if (err) 2404 2480 goto err_aes_cfb64_alg; 2405 2481 } 2406 2482 2407 2483 if (dd->caps.has_gcm) { 2484 + atmel_aes_crypto_alg_init(&aes_gcm_alg.base); 2485 + 2408 2486 err = crypto_register_aead(&aes_gcm_alg); 2409 2487 if (err) 2410 2488 goto err_aes_gcm_alg; 2411 2489 } 2412 2490 2413 2491 if (dd->caps.has_xts) { 2492 + atmel_aes_crypto_alg_init(&aes_xts_alg.base); 2493 + 2414 2494 err = crypto_register_skcipher(&aes_xts_alg); 2415 2495 if (err) 2416 2496 goto err_aes_xts_alg; ··· 2435 2483 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC) 2436 2484 if (dd->caps.has_authenc) { 2437 2485 for (i = 0; i < ARRAY_SIZE(aes_authenc_algs); i++) { 2486 + atmel_aes_crypto_alg_init(&aes_authenc_algs[i].base); 2487 + 2438 2488 err = crypto_register_aead(&aes_authenc_algs[i]); 2439 2489 if (err) 2440 2490 goto err_aes_authenc_alg;

+99 -225

drivers/crypto/atmel-sha.c

··· 1252 1252 return 0; 1253 1253 } 1254 1254 1255 + static void atmel_sha_alg_init(struct ahash_alg *alg) 1256 + { 1257 + alg->halg.base.cra_priority = ATMEL_SHA_PRIORITY; 1258 + alg->halg.base.cra_flags = CRYPTO_ALG_ASYNC; 1259 + alg->halg.base.cra_ctxsize = sizeof(struct atmel_sha_ctx); 1260 + alg->halg.base.cra_module = THIS_MODULE; 1261 + alg->halg.base.cra_init = atmel_sha_cra_init; 1262 + 1263 + alg->halg.statesize = sizeof(struct atmel_sha_reqctx); 1264 + 1265 + alg->init = atmel_sha_init; 1266 + alg->update = atmel_sha_update; 1267 + alg->final = atmel_sha_final; 1268 + alg->finup = atmel_sha_finup; 1269 + alg->digest = atmel_sha_digest; 1270 + alg->export = atmel_sha_export; 1271 + alg->import = atmel_sha_import; 1272 + } 1273 + 1255 1274 static struct ahash_alg sha_1_256_algs[] = { 1256 1275 { 1257 - .init = atmel_sha_init, 1258 - .update = atmel_sha_update, 1259 - .final = atmel_sha_final, 1260 - .finup = atmel_sha_finup, 1261 - .digest = atmel_sha_digest, 1262 - .export = atmel_sha_export, 1263 - .import = atmel_sha_import, 1264 - .halg = { 1265 - .digestsize = SHA1_DIGEST_SIZE, 1266 - .statesize = sizeof(struct atmel_sha_reqctx), 1267 - .base = { 1268 - .cra_name = "sha1", 1269 - .cra_driver_name = "atmel-sha1", 1270 - .cra_priority = ATMEL_SHA_PRIORITY, 1271 - .cra_flags = CRYPTO_ALG_ASYNC, 1272 - .cra_blocksize = SHA1_BLOCK_SIZE, 1273 - .cra_ctxsize = sizeof(struct atmel_sha_ctx), 1274 - .cra_alignmask = 0, 1275 - .cra_module = THIS_MODULE, 1276 - .cra_init = atmel_sha_cra_init, 1277 - } 1278 - } 1276 + .halg.base.cra_name = "sha1", 1277 + .halg.base.cra_driver_name = "atmel-sha1", 1278 + .halg.base.cra_blocksize = SHA1_BLOCK_SIZE, 1279 + 1280 + .halg.digestsize = SHA1_DIGEST_SIZE, 1279 1281 }, 1280 1282 { 1281 - .init = atmel_sha_init, 1282 - .update = atmel_sha_update, 1283 - .final = atmel_sha_final, 1284 - .finup = atmel_sha_finup, 1285 - .digest = atmel_sha_digest, 1286 - .export = atmel_sha_export, 1287 - .import = atmel_sha_import, 1288 - .halg = { 1289 - .digestsize = SHA256_DIGEST_SIZE, 1290 - .statesize = sizeof(struct atmel_sha_reqctx), 1291 - .base = { 1292 - .cra_name = "sha256", 1293 - .cra_driver_name = "atmel-sha256", 1294 - .cra_priority = ATMEL_SHA_PRIORITY, 1295 - .cra_flags = CRYPTO_ALG_ASYNC, 1296 - .cra_blocksize = SHA256_BLOCK_SIZE, 1297 - .cra_ctxsize = sizeof(struct atmel_sha_ctx), 1298 - .cra_alignmask = 0, 1299 - .cra_module = THIS_MODULE, 1300 - .cra_init = atmel_sha_cra_init, 1301 - } 1302 - } 1283 + .halg.base.cra_name = "sha256", 1284 + .halg.base.cra_driver_name = "atmel-sha256", 1285 + .halg.base.cra_blocksize = SHA256_BLOCK_SIZE, 1286 + 1287 + .halg.digestsize = SHA256_DIGEST_SIZE, 1303 1288 }, 1304 1289 }; 1305 1290 1306 1291 static struct ahash_alg sha_224_alg = { 1307 - .init = atmel_sha_init, 1308 - .update = atmel_sha_update, 1309 - .final = atmel_sha_final, 1310 - .finup = atmel_sha_finup, 1311 - .digest = atmel_sha_digest, 1312 - .export = atmel_sha_export, 1313 - .import = atmel_sha_import, 1314 - .halg = { 1315 - .digestsize = SHA224_DIGEST_SIZE, 1316 - .statesize = sizeof(struct atmel_sha_reqctx), 1317 - .base = { 1318 - .cra_name = "sha224", 1319 - .cra_driver_name = "atmel-sha224", 1320 - .cra_priority = ATMEL_SHA_PRIORITY, 1321 - .cra_flags = CRYPTO_ALG_ASYNC, 1322 - .cra_blocksize = SHA224_BLOCK_SIZE, 1323 - .cra_ctxsize = sizeof(struct atmel_sha_ctx), 1324 - .cra_alignmask = 0, 1325 - .cra_module = THIS_MODULE, 1326 - .cra_init = atmel_sha_cra_init, 1327 - } 1328 - } 1292 + .halg.base.cra_name = "sha224", 1293 + .halg.base.cra_driver_name = "atmel-sha224", 1294 + .halg.base.cra_blocksize = SHA224_BLOCK_SIZE, 1295 + 1296 + .halg.digestsize = SHA224_DIGEST_SIZE, 1329 1297 }; 1330 1298 1331 1299 static struct ahash_alg sha_384_512_algs[] = { 1332 1300 { 1333 - .init = atmel_sha_init, 1334 - .update = atmel_sha_update, 1335 - .final = atmel_sha_final, 1336 - .finup = atmel_sha_finup, 1337 - .digest = atmel_sha_digest, 1338 - .export = atmel_sha_export, 1339 - .import = atmel_sha_import, 1340 - .halg = { 1341 - .digestsize = SHA384_DIGEST_SIZE, 1342 - .statesize = sizeof(struct atmel_sha_reqctx), 1343 - .base = { 1344 - .cra_name = "sha384", 1345 - .cra_driver_name = "atmel-sha384", 1346 - .cra_priority = ATMEL_SHA_PRIORITY, 1347 - .cra_flags = CRYPTO_ALG_ASYNC, 1348 - .cra_blocksize = SHA384_BLOCK_SIZE, 1349 - .cra_ctxsize = sizeof(struct atmel_sha_ctx), 1350 - .cra_alignmask = 0x3, 1351 - .cra_module = THIS_MODULE, 1352 - .cra_init = atmel_sha_cra_init, 1353 - } 1354 - } 1301 + .halg.base.cra_name = "sha384", 1302 + .halg.base.cra_driver_name = "atmel-sha384", 1303 + .halg.base.cra_blocksize = SHA384_BLOCK_SIZE, 1304 + .halg.base.cra_alignmask = 0x3, 1305 + 1306 + .halg.digestsize = SHA384_DIGEST_SIZE, 1355 1307 }, 1356 1308 { 1357 - .init = atmel_sha_init, 1358 - .update = atmel_sha_update, 1359 - .final = atmel_sha_final, 1360 - .finup = atmel_sha_finup, 1361 - .digest = atmel_sha_digest, 1362 - .export = atmel_sha_export, 1363 - .import = atmel_sha_import, 1364 - .halg = { 1365 - .digestsize = SHA512_DIGEST_SIZE, 1366 - .statesize = sizeof(struct atmel_sha_reqctx), 1367 - .base = { 1368 - .cra_name = "sha512", 1369 - .cra_driver_name = "atmel-sha512", 1370 - .cra_priority = ATMEL_SHA_PRIORITY, 1371 - .cra_flags = CRYPTO_ALG_ASYNC, 1372 - .cra_blocksize = SHA512_BLOCK_SIZE, 1373 - .cra_ctxsize = sizeof(struct atmel_sha_ctx), 1374 - .cra_alignmask = 0x3, 1375 - .cra_module = THIS_MODULE, 1376 - .cra_init = atmel_sha_cra_init, 1377 - } 1378 - } 1309 + .halg.base.cra_name = "sha512", 1310 + .halg.base.cra_driver_name = "atmel-sha512", 1311 + .halg.base.cra_blocksize = SHA512_BLOCK_SIZE, 1312 + .halg.base.cra_alignmask = 0x3, 1313 + 1314 + .halg.digestsize = SHA512_DIGEST_SIZE, 1379 1315 }, 1380 1316 }; 1381 1317 ··· 2020 2084 atmel_sha_hmac_key_release(&hmac->hkey); 2021 2085 } 2022 2086 2087 + static void atmel_sha_hmac_alg_init(struct ahash_alg *alg) 2088 + { 2089 + alg->halg.base.cra_priority = ATMEL_SHA_PRIORITY; 2090 + alg->halg.base.cra_flags = CRYPTO_ALG_ASYNC; 2091 + alg->halg.base.cra_ctxsize = sizeof(struct atmel_sha_hmac_ctx); 2092 + alg->halg.base.cra_module = THIS_MODULE; 2093 + alg->halg.base.cra_init = atmel_sha_hmac_cra_init; 2094 + alg->halg.base.cra_exit = atmel_sha_hmac_cra_exit; 2095 + 2096 + alg->halg.statesize = sizeof(struct atmel_sha_reqctx); 2097 + 2098 + alg->init = atmel_sha_hmac_init; 2099 + alg->update = atmel_sha_update; 2100 + alg->final = atmel_sha_final; 2101 + alg->digest = atmel_sha_hmac_digest; 2102 + alg->setkey = atmel_sha_hmac_setkey; 2103 + alg->export = atmel_sha_export; 2104 + alg->import = atmel_sha_import; 2105 + } 2106 + 2023 2107 static struct ahash_alg sha_hmac_algs[] = { 2024 2108 { 2025 - .init = atmel_sha_hmac_init, 2026 - .update = atmel_sha_update, 2027 - .final = atmel_sha_final, 2028 - .digest = atmel_sha_hmac_digest, 2029 - .setkey = atmel_sha_hmac_setkey, 2030 - .export = atmel_sha_export, 2031 - .import = atmel_sha_import, 2032 - .halg = { 2033 - .digestsize = SHA1_DIGEST_SIZE, 2034 - .statesize = sizeof(struct atmel_sha_reqctx), 2035 - .base = { 2036 - .cra_name = "hmac(sha1)", 2037 - .cra_driver_name = "atmel-hmac-sha1", 2038 - .cra_priority = ATMEL_SHA_PRIORITY, 2039 - .cra_flags = CRYPTO_ALG_ASYNC, 2040 - .cra_blocksize = SHA1_BLOCK_SIZE, 2041 - .cra_ctxsize = sizeof(struct atmel_sha_hmac_ctx), 2042 - .cra_alignmask = 0, 2043 - .cra_module = THIS_MODULE, 2044 - .cra_init = atmel_sha_hmac_cra_init, 2045 - .cra_exit = atmel_sha_hmac_cra_exit, 2046 - } 2047 - } 2109 + .halg.base.cra_name = "hmac(sha1)", 2110 + .halg.base.cra_driver_name = "atmel-hmac-sha1", 2111 + .halg.base.cra_blocksize = SHA1_BLOCK_SIZE, 2112 + 2113 + .halg.digestsize = SHA1_DIGEST_SIZE, 2048 2114 }, 2049 2115 { 2050 - .init = atmel_sha_hmac_init, 2051 - .update = atmel_sha_update, 2052 - .final = atmel_sha_final, 2053 - .digest = atmel_sha_hmac_digest, 2054 - .setkey = atmel_sha_hmac_setkey, 2055 - .export = atmel_sha_export, 2056 - .import = atmel_sha_import, 2057 - .halg = { 2058 - .digestsize = SHA224_DIGEST_SIZE, 2059 - .statesize = sizeof(struct atmel_sha_reqctx), 2060 - .base = { 2061 - .cra_name = "hmac(sha224)", 2062 - .cra_driver_name = "atmel-hmac-sha224", 2063 - .cra_priority = ATMEL_SHA_PRIORITY, 2064 - .cra_flags = CRYPTO_ALG_ASYNC, 2065 - .cra_blocksize = SHA224_BLOCK_SIZE, 2066 - .cra_ctxsize = sizeof(struct atmel_sha_hmac_ctx), 2067 - .cra_alignmask = 0, 2068 - .cra_module = THIS_MODULE, 2069 - .cra_init = atmel_sha_hmac_cra_init, 2070 - .cra_exit = atmel_sha_hmac_cra_exit, 2071 - } 2072 - } 2116 + .halg.base.cra_name = "hmac(sha224)", 2117 + .halg.base.cra_driver_name = "atmel-hmac-sha224", 2118 + .halg.base.cra_blocksize = SHA224_BLOCK_SIZE, 2119 + 2120 + .halg.digestsize = SHA224_DIGEST_SIZE, 2073 2121 }, 2074 2122 { 2075 - .init = atmel_sha_hmac_init, 2076 - .update = atmel_sha_update, 2077 - .final = atmel_sha_final, 2078 - .digest = atmel_sha_hmac_digest, 2079 - .setkey = atmel_sha_hmac_setkey, 2080 - .export = atmel_sha_export, 2081 - .import = atmel_sha_import, 2082 - .halg = { 2083 - .digestsize = SHA256_DIGEST_SIZE, 2084 - .statesize = sizeof(struct atmel_sha_reqctx), 2085 - .base = { 2086 - .cra_name = "hmac(sha256)", 2087 - .cra_driver_name = "atmel-hmac-sha256", 2088 - .cra_priority = ATMEL_SHA_PRIORITY, 2089 - .cra_flags = CRYPTO_ALG_ASYNC, 2090 - .cra_blocksize = SHA256_BLOCK_SIZE, 2091 - .cra_ctxsize = sizeof(struct atmel_sha_hmac_ctx), 2092 - .cra_alignmask = 0, 2093 - .cra_module = THIS_MODULE, 2094 - .cra_init = atmel_sha_hmac_cra_init, 2095 - .cra_exit = atmel_sha_hmac_cra_exit, 2096 - } 2097 - } 2123 + .halg.base.cra_name = "hmac(sha256)", 2124 + .halg.base.cra_driver_name = "atmel-hmac-sha256", 2125 + .halg.base.cra_blocksize = SHA256_BLOCK_SIZE, 2126 + 2127 + .halg.digestsize = SHA256_DIGEST_SIZE, 2098 2128 }, 2099 2129 { 2100 - .init = atmel_sha_hmac_init, 2101 - .update = atmel_sha_update, 2102 - .final = atmel_sha_final, 2103 - .digest = atmel_sha_hmac_digest, 2104 - .setkey = atmel_sha_hmac_setkey, 2105 - .export = atmel_sha_export, 2106 - .import = atmel_sha_import, 2107 - .halg = { 2108 - .digestsize = SHA384_DIGEST_SIZE, 2109 - .statesize = sizeof(struct atmel_sha_reqctx), 2110 - .base = { 2111 - .cra_name = "hmac(sha384)", 2112 - .cra_driver_name = "atmel-hmac-sha384", 2113 - .cra_priority = ATMEL_SHA_PRIORITY, 2114 - .cra_flags = CRYPTO_ALG_ASYNC, 2115 - .cra_blocksize = SHA384_BLOCK_SIZE, 2116 - .cra_ctxsize = sizeof(struct atmel_sha_hmac_ctx), 2117 - .cra_alignmask = 0, 2118 - .cra_module = THIS_MODULE, 2119 - .cra_init = atmel_sha_hmac_cra_init, 2120 - .cra_exit = atmel_sha_hmac_cra_exit, 2121 - } 2122 - } 2130 + .halg.base.cra_name = "hmac(sha384)", 2131 + .halg.base.cra_driver_name = "atmel-hmac-sha384", 2132 + .halg.base.cra_blocksize = SHA384_BLOCK_SIZE, 2133 + 2134 + .halg.digestsize = SHA384_DIGEST_SIZE, 2123 2135 }, 2124 2136 { 2125 - .init = atmel_sha_hmac_init, 2126 - .update = atmel_sha_update, 2127 - .final = atmel_sha_final, 2128 - .digest = atmel_sha_hmac_digest, 2129 - .setkey = atmel_sha_hmac_setkey, 2130 - .export = atmel_sha_export, 2131 - .import = atmel_sha_import, 2132 - .halg = { 2133 - .digestsize = SHA512_DIGEST_SIZE, 2134 - .statesize = sizeof(struct atmel_sha_reqctx), 2135 - .base = { 2136 - .cra_name = "hmac(sha512)", 2137 - .cra_driver_name = "atmel-hmac-sha512", 2138 - .cra_priority = ATMEL_SHA_PRIORITY, 2139 - .cra_flags = CRYPTO_ALG_ASYNC, 2140 - .cra_blocksize = SHA512_BLOCK_SIZE, 2141 - .cra_ctxsize = sizeof(struct atmel_sha_hmac_ctx), 2142 - .cra_alignmask = 0, 2143 - .cra_module = THIS_MODULE, 2144 - .cra_init = atmel_sha_hmac_cra_init, 2145 - .cra_exit = atmel_sha_hmac_cra_exit, 2146 - } 2147 - } 2137 + .halg.base.cra_name = "hmac(sha512)", 2138 + .halg.base.cra_driver_name = "atmel-hmac-sha512", 2139 + .halg.base.cra_blocksize = SHA512_BLOCK_SIZE, 2140 + 2141 + .halg.digestsize = SHA512_DIGEST_SIZE, 2148 2142 }, 2149 2143 }; 2150 2144 ··· 2427 2561 int err, i, j; 2428 2562 2429 2563 for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) { 2564 + atmel_sha_alg_init(&sha_1_256_algs[i]); 2565 + 2430 2566 err = crypto_register_ahash(&sha_1_256_algs[i]); 2431 2567 if (err) 2432 2568 goto err_sha_1_256_algs; 2433 2569 } 2434 2570 2435 2571 if (dd->caps.has_sha224) { 2572 + atmel_sha_alg_init(&sha_224_alg); 2573 + 2436 2574 err = crypto_register_ahash(&sha_224_alg); 2437 2575 if (err) 2438 2576 goto err_sha_224_algs; ··· 2444 2574 2445 2575 if (dd->caps.has_sha_384_512) { 2446 2576 for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) { 2577 + atmel_sha_alg_init(&sha_384_512_algs[i]); 2578 + 2447 2579 err = crypto_register_ahash(&sha_384_512_algs[i]); 2448 2580 if (err) 2449 2581 goto err_sha_384_512_algs; ··· 2454 2582 2455 2583 if (dd->caps.has_hmac) { 2456 2584 for (i = 0; i < ARRAY_SIZE(sha_hmac_algs); i++) { 2585 + atmel_sha_hmac_alg_init(&sha_hmac_algs[i]); 2586 + 2457 2587 err = crypto_register_ahash(&sha_hmac_algs[i]); 2458 2588 if (err) 2459 2589 goto err_sha_hmac_algs;

+12 -50

drivers/crypto/atmel-tdes.c

··· 912 912 return 0; 913 913 } 914 914 915 + static void atmel_tdes_skcipher_alg_init(struct skcipher_alg *alg) 916 + { 917 + alg->base.cra_priority = ATMEL_TDES_PRIORITY; 918 + alg->base.cra_flags = CRYPTO_ALG_ASYNC; 919 + alg->base.cra_ctxsize = sizeof(struct atmel_tdes_ctx), 920 + alg->base.cra_module = THIS_MODULE; 921 + 922 + alg->init = atmel_tdes_init_tfm; 923 + } 924 + 915 925 static struct skcipher_alg tdes_algs[] = { 916 926 { 917 927 .base.cra_name = "ecb(des)", 918 928 .base.cra_driver_name = "atmel-ecb-des", 919 - .base.cra_priority = ATMEL_TDES_PRIORITY, 920 - .base.cra_flags = CRYPTO_ALG_ASYNC, 921 929 .base.cra_blocksize = DES_BLOCK_SIZE, 922 - .base.cra_ctxsize = sizeof(struct atmel_tdes_ctx), 923 930 .base.cra_alignmask = 0x7, 924 - .base.cra_module = THIS_MODULE, 925 931 926 - .init = atmel_tdes_init_tfm, 927 932 .min_keysize = DES_KEY_SIZE, 928 933 .max_keysize = DES_KEY_SIZE, 929 934 .setkey = atmel_des_setkey, ··· 938 933 { 939 934 .base.cra_name = "cbc(des)", 940 935 .base.cra_driver_name = "atmel-cbc-des", 941 - .base.cra_priority = ATMEL_TDES_PRIORITY, 942 - .base.cra_flags = CRYPTO_ALG_ASYNC, 943 936 .base.cra_blocksize = DES_BLOCK_SIZE, 944 - .base.cra_ctxsize = sizeof(struct atmel_tdes_ctx), 945 937 .base.cra_alignmask = 0x7, 946 - .base.cra_module = THIS_MODULE, 947 938 948 - .init = atmel_tdes_init_tfm, 949 939 .min_keysize = DES_KEY_SIZE, 950 940 .max_keysize = DES_KEY_SIZE, 951 941 .ivsize = DES_BLOCK_SIZE, ··· 951 951 { 952 952 .base.cra_name = "cfb(des)", 953 953 .base.cra_driver_name = "atmel-cfb-des", 954 - .base.cra_priority = ATMEL_TDES_PRIORITY, 955 - .base.cra_flags = CRYPTO_ALG_ASYNC, 956 954 .base.cra_blocksize = DES_BLOCK_SIZE, 957 - .base.cra_ctxsize = sizeof(struct atmel_tdes_ctx), 958 955 .base.cra_alignmask = 0x7, 959 - .base.cra_module = THIS_MODULE, 960 956 961 - .init = atmel_tdes_init_tfm, 962 957 .min_keysize = DES_KEY_SIZE, 963 958 .max_keysize = DES_KEY_SIZE, 964 959 .ivsize = DES_BLOCK_SIZE, ··· 964 969 { 965 970 .base.cra_name = "cfb8(des)", 966 971 .base.cra_driver_name = "atmel-cfb8-des", 967 - .base.cra_priority = ATMEL_TDES_PRIORITY, 968 - .base.cra_flags = CRYPTO_ALG_ASYNC, 969 972 .base.cra_blocksize = CFB8_BLOCK_SIZE, 970 - .base.cra_ctxsize = sizeof(struct atmel_tdes_ctx), 971 973 .base.cra_alignmask = 0, 972 - .base.cra_module = THIS_MODULE, 973 974 974 - .init = atmel_tdes_init_tfm, 975 975 .min_keysize = DES_KEY_SIZE, 976 976 .max_keysize = DES_KEY_SIZE, 977 977 .ivsize = DES_BLOCK_SIZE, ··· 977 987 { 978 988 .base.cra_name = "cfb16(des)", 979 989 .base.cra_driver_name = "atmel-cfb16-des", 980 - .base.cra_priority = ATMEL_TDES_PRIORITY, 981 - .base.cra_flags = CRYPTO_ALG_ASYNC, 982 990 .base.cra_blocksize = CFB16_BLOCK_SIZE, 983 - .base.cra_ctxsize = sizeof(struct atmel_tdes_ctx), 984 991 .base.cra_alignmask = 0x1, 985 - .base.cra_module = THIS_MODULE, 986 992 987 - .init = atmel_tdes_init_tfm, 988 993 .min_keysize = DES_KEY_SIZE, 989 994 .max_keysize = DES_KEY_SIZE, 990 995 .ivsize = DES_BLOCK_SIZE, ··· 990 1005 { 991 1006 .base.cra_name = "cfb32(des)", 992 1007 .base.cra_driver_name = "atmel-cfb32-des", 993 - .base.cra_priority = ATMEL_TDES_PRIORITY, 994 - .base.cra_flags = CRYPTO_ALG_ASYNC, 995 1008 .base.cra_blocksize = CFB32_BLOCK_SIZE, 996 - .base.cra_ctxsize = sizeof(struct atmel_tdes_ctx), 997 1009 .base.cra_alignmask = 0x3, 998 - .base.cra_module = THIS_MODULE, 999 1010 1000 - .init = atmel_tdes_init_tfm, 1001 1011 .min_keysize = DES_KEY_SIZE, 1002 1012 .max_keysize = DES_KEY_SIZE, 1003 1013 .ivsize = DES_BLOCK_SIZE, ··· 1003 1023 { 1004 1024 .base.cra_name = "ofb(des)", 1005 1025 .base.cra_driver_name = "atmel-ofb-des", 1006 - .base.cra_priority = ATMEL_TDES_PRIORITY, 1007 - .base.cra_flags = CRYPTO_ALG_ASYNC, 1008 1026 .base.cra_blocksize = DES_BLOCK_SIZE, 1009 - .base.cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1010 1027 .base.cra_alignmask = 0x7, 1011 - .base.cra_module = THIS_MODULE, 1012 1028 1013 - .init = atmel_tdes_init_tfm, 1014 1029 .min_keysize = DES_KEY_SIZE, 1015 1030 .max_keysize = DES_KEY_SIZE, 1016 1031 .ivsize = DES_BLOCK_SIZE, ··· 1016 1041 { 1017 1042 .base.cra_name = "ecb(des3_ede)", 1018 1043 .base.cra_driver_name = "atmel-ecb-tdes", 1019 - .base.cra_priority = ATMEL_TDES_PRIORITY, 1020 - .base.cra_flags = CRYPTO_ALG_ASYNC, 1021 1044 .base.cra_blocksize = DES_BLOCK_SIZE, 1022 - .base.cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1023 1045 .base.cra_alignmask = 0x7, 1024 - .base.cra_module = THIS_MODULE, 1025 1046 1026 - .init = atmel_tdes_init_tfm, 1027 1047 .min_keysize = DES3_EDE_KEY_SIZE, 1028 1048 .max_keysize = DES3_EDE_KEY_SIZE, 1029 1049 .setkey = atmel_tdes_setkey, ··· 1028 1058 { 1029 1059 .base.cra_name = "cbc(des3_ede)", 1030 1060 .base.cra_driver_name = "atmel-cbc-tdes", 1031 - .base.cra_priority = ATMEL_TDES_PRIORITY, 1032 - .base.cra_flags = CRYPTO_ALG_ASYNC, 1033 1061 .base.cra_blocksize = DES_BLOCK_SIZE, 1034 - .base.cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1035 1062 .base.cra_alignmask = 0x7, 1036 - .base.cra_module = THIS_MODULE, 1037 1063 1038 - .init = atmel_tdes_init_tfm, 1039 1064 .min_keysize = DES3_EDE_KEY_SIZE, 1040 1065 .max_keysize = DES3_EDE_KEY_SIZE, 1041 1066 .setkey = atmel_tdes_setkey, ··· 1041 1076 { 1042 1077 .base.cra_name = "ofb(des3_ede)", 1043 1078 .base.cra_driver_name = "atmel-ofb-tdes", 1044 - .base.cra_priority = ATMEL_TDES_PRIORITY, 1045 - .base.cra_flags = CRYPTO_ALG_ASYNC, 1046 1079 .base.cra_blocksize = DES_BLOCK_SIZE, 1047 - .base.cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1048 1080 .base.cra_alignmask = 0x7, 1049 - .base.cra_module = THIS_MODULE, 1050 1081 1051 - .init = atmel_tdes_init_tfm, 1052 1082 .min_keysize = DES3_EDE_KEY_SIZE, 1053 1083 .max_keysize = DES3_EDE_KEY_SIZE, 1054 1084 .setkey = atmel_tdes_setkey, ··· 1118 1158 int err, i, j; 1119 1159 1120 1160 for (i = 0; i < ARRAY_SIZE(tdes_algs); i++) { 1161 + atmel_tdes_skcipher_alg_init(&tdes_algs[i]); 1162 + 1121 1163 err = crypto_register_skcipher(&tdes_algs[i]); 1122 1164 if (err) 1123 1165 goto err_tdes_algs;