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dt-bindings: Add Oxford Semiconductor OXNAS pinctrl and gpio bindings
Add pinctrl and gpio DT bindings for Oxford Semiconductor OXNAS SoC Family.
This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
authored by
Neil Armstrong
and committed by
Linus Walleij
aeb99c85
611dac1e
+104
+47
Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
+47
Documentation/devicetree/bindings/gpio/gpio_oxnas.txt
···
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* Oxford Semiconductor OXNAS SoC GPIO Controller
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Please refer to gpio.txt for generic information regarding GPIO bindings.
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Required properties:
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- compatible: "oxsemi,ox810se-gpio"
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- reg: Base address and length for the device.
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- interrupts: The port interrupt shared by all pins.
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- gpio-controller: Marks the port as GPIO controller.
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- #gpio-cells: Two. The first cell is the pin number and
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the second cell is used to specify the gpio polarity as defined in
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defined in <dt-bindings/gpio/gpio.h>:
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0 = GPIO_ACTIVE_HIGH
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1 = GPIO_ACTIVE_LOW
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- interrupt-controller: Marks the device node as an interrupt controller.
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- #interrupt-cells: Two. The first cell is the GPIO number and second cell
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is used to specify the trigger type as defined in
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<dt-bindings/interrupt-controller/irq.h>:
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IRQ_TYPE_EDGE_RISING
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IRQ_TYPE_EDGE_FALLING
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IRQ_TYPE_EDGE_BOTH
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- gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the
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gpio base and count, should be in the format of numeric-gpio-range as
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specified in the gpio.txt file.
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Example:
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gpio0: gpio@0 {
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compatible = "oxsemi,ox810se-gpio";
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reg = <0x000000 0x100000>;
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interrupts = <21>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 32>;
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};
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keys {
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...
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button-esc {
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label = "ESC";
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linux,code = <1>;
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gpios = <&gpio0 12 0>;
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};
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};
+57
Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt
+57
Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt
···
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* Oxford Semiconductor OXNAS SoC Family Pin Controller
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Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
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../interrupt-controller/interrupts.txt for generic information regarding
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pin controller, GPIO, and interrupt bindings.
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OXNAS 'pin configuration node' is a node of a group of pins which can be
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used for a specific device or function. This node represents configurations of
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pins, optional function, and optional mux related configuration.
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Required properties for pin controller node:
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- compatible: "oxsemi,ox810se-pinctrl"
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- oxsemi,sys-ctrl: a phandle to the system controller syscon node
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Required properties for pin configuration sub-nodes:
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- pins: List of pins to which the configuration applies.
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Optional properties for pin configuration sub-nodes:
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----------------------------------------------------
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- function: Mux function for the specified pins.
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- bias-pull-up: Enable weak pull-up.
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Example:
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pinctrl: pinctrl {
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compatible = "oxsemi,ox810se-pinctrl";
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/* Regmap for sys registers */
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oxsemi,sys-ctrl = <&sys>;
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pinctrl_uart2: pinctrl_uart2 {
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uart2a {
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pins = "gpio31";
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function = "fct3";
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};
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uart2b {
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pins = "gpio32";
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function = "fct3";
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};
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};
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};
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uart2: serial@900000 {
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compatible = "ns16550a";
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reg = <0x900000 0x100000>;
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clocks = <&sysclk>;
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interrupts = <29>;
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reg-shift = <0>;
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fifo-size = <16>;
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reg-io-width = <1>;
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current-speed = <115200>;
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no-loopback-test;
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status = "disabled";
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resets = <&reset 22>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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};