tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'clk-next-hi6220' into clk-next
Conflicts:
drivers/clk/Kconfig
+681
-16
+1
drivers/clk/Kconfig
+1
drivers/clk/Kconfig
+1
-3
drivers/clk/Makefile
+1
-3
drivers/clk/Makefile
···
48
48
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
49
49
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
50
50
obj-$(CONFIG_ARCH_BERLIN) += berlin/
51
-
obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
52
-
obj-$(CONFIG_ARCH_HIP04) += hisilicon/
53
-
obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
51
+
obj-$(CONFIG_ARCH_HISI) += hisilicon/
54
52
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
55
53
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
56
54
ifeq ($(CONFIG_COMMON_CLK), y)
+6
drivers/clk/hisilicon/Kconfig
+6
drivers/clk/hisilicon/Kconfig
+2
-1
drivers/clk/hisilicon/Makefile
+2
-1
drivers/clk/hisilicon/Makefile
···
2
2
# Hisilicon Clock specific Makefile
3
3
#
4
4
5
-
obj-y += clk.o clkgate-separated.o
5
+
obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
6
6
7
7
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
8
8
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
9
9
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
10
+
obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
+284
drivers/clk/hisilicon/clk-hi6220.c
+284
drivers/clk/hisilicon/clk-hi6220.c
···
1
+
/*
2
+
* Hisilicon Hi6220 clock driver
3
+
*
4
+
* Copyright (c) 2015 Hisilicon Limited.
5
+
*
6
+
* Author: Bintian Wang <bintian.wang@huawei.com>
7
+
*
8
+
* This program is free software; you can redistribute it and/or modify
9
+
* it under the terms of the GNU General Public License version 2 as
10
+
* published by the Free Software Foundation.
11
+
*/
12
+
13
+
#include <linux/kernel.h>
14
+
#include <linux/clk-provider.h>
15
+
#include <linux/clkdev.h>
16
+
#include <linux/io.h>
17
+
#include <linux/of.h>
18
+
#include <linux/of_address.h>
19
+
#include <linux/of_device.h>
20
+
#include <linux/slab.h>
21
+
22
+
#include <dt-bindings/clock/hi6220-clock.h>
23
+
24
+
#include "clk.h"
25
+
26
+
27
+
/* clocks in AO (always on) controller */
28
+
static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
29
+
{ HI6220_REF32K, "ref32k", NULL, CLK_IS_ROOT, 32764, },
30
+
{ HI6220_CLK_TCXO, "clk_tcxo", NULL, CLK_IS_ROOT, 19200000, },
31
+
{ HI6220_MMC1_PAD, "mmc1_pad", NULL, CLK_IS_ROOT, 100000000, },
32
+
{ HI6220_MMC2_PAD, "mmc2_pad", NULL, CLK_IS_ROOT, 100000000, },
33
+
{ HI6220_MMC0_PAD, "mmc0_pad", NULL, CLK_IS_ROOT, 200000000, },
34
+
{ HI6220_PLL_BBP, "bbppll0", NULL, CLK_IS_ROOT, 245760000, },
35
+
{ HI6220_PLL_GPU, "gpupll", NULL, CLK_IS_ROOT, 1000000000,},
36
+
{ HI6220_PLL1_DDR, "ddrpll1", NULL, CLK_IS_ROOT, 1066000000,},
37
+
{ HI6220_PLL_SYS, "syspll", NULL, CLK_IS_ROOT, 1200000000,},
38
+
{ HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, CLK_IS_ROOT, 1200000000,},
39
+
{ HI6220_DDR_SRC, "ddr_sel_src", NULL, CLK_IS_ROOT, 1200000000,},
40
+
{ HI6220_PLL_MEDIA, "media_pll", NULL, CLK_IS_ROOT, 1440000000,},
41
+
{ HI6220_PLL_DDR, "ddrpll0", NULL, CLK_IS_ROOT, 1600000000,},
42
+
};
43
+
44
+
static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdata = {
45
+
{ HI6220_300M, "clk_300m", "syspll", 1, 4, 0, },
46
+
{ HI6220_150M, "clk_150m", "clk_300m", 1, 2, 0, },
47
+
{ HI6220_PICOPHY_SRC, "picophy_src", "clk_150m", 1, 4, 0, },
48
+
{ HI6220_MMC0_SRC_SEL, "mmc0srcsel", "mmc0_sel", 1, 8, 0, },
49
+
{ HI6220_MMC1_SRC_SEL, "mmc1srcsel", "mmc1_sel", 1, 8, 0, },
50
+
{ HI6220_MMC2_SRC_SEL, "mmc2srcsel", "mmc2_sel", 1, 8, 0, },
51
+
{ HI6220_VPU_CODEC, "vpucodec", "codec_jpeg_aclk", 1, 2, 0, },
52
+
{ HI6220_MMC0_SMP, "mmc0_sample", "mmc0_sel", 1, 8, 0, },
53
+
{ HI6220_MMC1_SMP, "mmc1_sample", "mmc1_sel", 1, 8, 0, },
54
+
{ HI6220_MMC2_SMP, "mmc2_sample", "mmc2_sel", 1, 8, 0, },
55
+
};
56
+
57
+
static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
58
+
{ HI6220_WDT0_PCLK, "wdt0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12, 0, },
59
+
{ HI6220_WDT1_PCLK, "wdt1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13, 0, },
60
+
{ HI6220_WDT2_PCLK, "wdt2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14, 0, },
61
+
{ HI6220_TIMER0_PCLK, "timer0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 15, 0, },
62
+
{ HI6220_TIMER1_PCLK, "timer1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 16, 0, },
63
+
{ HI6220_TIMER2_PCLK, "timer2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 17, 0, },
64
+
{ HI6220_TIMER3_PCLK, "timer3_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 18, 0, },
65
+
{ HI6220_TIMER4_PCLK, "timer4_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 19, 0, },
66
+
{ HI6220_TIMER5_PCLK, "timer5_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 20, 0, },
67
+
{ HI6220_TIMER6_PCLK, "timer6_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 21, 0, },
68
+
{ HI6220_TIMER7_PCLK, "timer7_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 22, 0, },
69
+
{ HI6220_TIMER8_PCLK, "timer8_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 23, 0, },
70
+
{ HI6220_UART0_PCLK, "uart0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 24, 0, },
71
+
};
72
+
73
+
static void __init hi6220_clk_ao_init(struct device_node *np)
74
+
{
75
+
struct hisi_clock_data *clk_data_ao;
76
+
77
+
clk_data_ao = hisi_clk_init(np, HI6220_AO_NR_CLKS);
78
+
if (!clk_data_ao)
79
+
return;
80
+
81
+
hisi_clk_register_fixed_rate(hi6220_fixed_rate_clks,
82
+
ARRAY_SIZE(hi6220_fixed_rate_clks), clk_data_ao);
83
+
84
+
hisi_clk_register_fixed_factor(hi6220_fixed_factor_clks,
85
+
ARRAY_SIZE(hi6220_fixed_factor_clks), clk_data_ao);
86
+
87
+
hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao,
88
+
ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao);
89
+
}
90
+
CLK_OF_DECLARE(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);
91
+
92
+
93
+
/* clocks in sysctrl */
94
+
static const char *mmc0_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
95
+
static const char *mmc0_mux1_p[] __initdata = { "mmc0_mux0", "pll_media_gate", };
96
+
static const char *mmc0_src_p[] __initdata = { "mmc0srcsel", "mmc0_div", };
97
+
static const char *mmc1_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
98
+
static const char *mmc1_mux1_p[] __initdata = { "mmc1_mux0", "pll_media_gate", };
99
+
static const char *mmc1_src_p[] __initdata = { "mmc1srcsel", "mmc1_div", };
100
+
static const char *mmc2_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
101
+
static const char *mmc2_mux1_p[] __initdata = { "mmc2_mux0", "pll_media_gate", };
102
+
static const char *mmc2_src_p[] __initdata = { "mmc2srcsel", "mmc2_div", };
103
+
static const char *mmc0_sample_in[] __initdata = { "mmc0_sample", "mmc0_pad", };
104
+
static const char *mmc1_sample_in[] __initdata = { "mmc1_sample", "mmc1_pad", };
105
+
static const char *mmc2_sample_in[] __initdata = { "mmc2_sample", "mmc2_pad", };
106
+
static const char *uart1_src[] __initdata = { "clk_tcxo", "clk_150m", };
107
+
static const char *uart2_src[] __initdata = { "clk_tcxo", "clk_150m", };
108
+
static const char *uart3_src[] __initdata = { "clk_tcxo", "clk_150m", };
109
+
static const char *uart4_src[] __initdata = { "clk_tcxo", "clk_150m", };
110
+
static const char *hifi_src[] __initdata = { "syspll", "pll_media_gate", };
111
+
112
+
static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = {
113
+
{ HI6220_MMC0_CLK, "mmc0_clk", "mmc0_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0, 0, },
114
+
{ HI6220_MMC0_CIUCLK, "mmc0_ciuclk", "mmc0_smp_in", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0, 0, },
115
+
{ HI6220_MMC1_CLK, "mmc1_clk", "mmc1_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 1, 0, },
116
+
{ HI6220_MMC1_CIUCLK, "mmc1_ciuclk", "mmc1_smp_in", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 1, 0, },
117
+
{ HI6220_MMC2_CLK, "mmc2_clk", "mmc2_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 2, 0, },
118
+
{ HI6220_MMC2_CIUCLK, "mmc2_ciuclk", "mmc2_smp_in", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 2, 0, },
119
+
{ HI6220_USBOTG_HCLK, "usbotg_hclk", "clk_bus", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 4, 0, },
120
+
{ HI6220_CLK_PICOPHY, "clk_picophy", "cs_dapb", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 5, 0, },
121
+
{ HI6220_HIFI, "hifi_clk", "hifi_div", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x210, 0, 0, },
122
+
{ HI6220_DACODEC_PCLK, "dacodec_pclk", "clk_bus", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x210, 5, 0, },
123
+
{ HI6220_EDMAC_ACLK, "edmac_aclk", "clk_bus", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x220, 2, 0, },
124
+
{ HI6220_CS_ATB, "cs_atb", "cs_atb_div", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 0, 0, },
125
+
{ HI6220_I2C0_CLK, "i2c0_clk", "clk_150m", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 1, 0, },
126
+
{ HI6220_I2C1_CLK, "i2c1_clk", "clk_150m", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 2, 0, },
127
+
{ HI6220_I2C2_CLK, "i2c2_clk", "clk_150m", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 3, 0, },
128
+
{ HI6220_I2C3_CLK, "i2c3_clk", "clk_150m", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 4, 0, },
129
+
{ HI6220_UART1_PCLK, "uart1_pclk", "uart1_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 5, 0, },
130
+
{ HI6220_UART2_PCLK, "uart2_pclk", "uart2_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 6, 0, },
131
+
{ HI6220_UART3_PCLK, "uart3_pclk", "uart3_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 7, 0, },
132
+
{ HI6220_UART4_PCLK, "uart4_pclk", "uart4_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 8, 0, },
133
+
{ HI6220_SPI_CLK, "spi_clk", "clk_150m", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 9, 0, },
134
+
{ HI6220_TSENSOR_CLK, "tsensor_clk", "clk_bus", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 12, 0, },
135
+
{ HI6220_MMU_CLK, "mmu_clk", "ddrc_axi1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x240, 11, 0, },
136
+
{ HI6220_HIFI_SEL, "hifi_sel", "hifi_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 0, 0, },
137
+
{ HI6220_MMC0_SYSPLL, "mmc0_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 1, 0, },
138
+
{ HI6220_MMC1_SYSPLL, "mmc1_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 2, 0, },
139
+
{ HI6220_MMC2_SYSPLL, "mmc2_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 3, 0, },
140
+
{ HI6220_MMC0_SEL, "mmc0_sel", "mmc0_mux1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 6, 0, },
141
+
{ HI6220_MMC1_SEL, "mmc1_sel", "mmc1_mux1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 7, 0, },
142
+
{ HI6220_BBPPLL_SEL, "bbppll_sel", "pll0_bbp_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 9, 0, },
143
+
{ HI6220_MEDIA_PLL_SRC, "media_pll_src", "pll_media_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 10, 0, },
144
+
{ HI6220_MMC2_SEL, "mmc2_sel", "mmc2_mux1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 11, 0, },
145
+
{ HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 12, 0, },
146
+
};
147
+
148
+
static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {
149
+
{ HI6220_MMC0_SRC, "mmc0_src", mmc0_src_p, ARRAY_SIZE(mmc0_src_p), CLK_SET_RATE_PARENT, 0x4, 0, 1, 0, },
150
+
{ HI6220_MMC0_SMP_IN, "mmc0_smp_in", mmc0_sample_in, ARRAY_SIZE(mmc0_sample_in), CLK_SET_RATE_PARENT, 0x4, 0, 1, 0, },
151
+
{ HI6220_MMC1_SRC, "mmc1_src", mmc1_src_p, ARRAY_SIZE(mmc1_src_p), CLK_SET_RATE_PARENT, 0x4, 2, 1, 0, },
152
+
{ HI6220_MMC1_SMP_IN, "mmc1_smp_in", mmc1_sample_in, ARRAY_SIZE(mmc1_sample_in), CLK_SET_RATE_PARENT, 0x4, 2, 1, 0, },
153
+
{ HI6220_MMC2_SRC, "mmc2_src", mmc2_src_p, ARRAY_SIZE(mmc2_src_p), CLK_SET_RATE_PARENT, 0x4, 4, 1, 0, },
154
+
{ HI6220_MMC2_SMP_IN, "mmc2_smp_in", mmc2_sample_in, ARRAY_SIZE(mmc2_sample_in), CLK_SET_RATE_PARENT, 0x4, 4, 1, 0, },
155
+
{ HI6220_HIFI_SRC, "hifi_src", hifi_src, ARRAY_SIZE(hifi_src), CLK_SET_RATE_PARENT, 0x400, 0, 1, CLK_MUX_HIWORD_MASK,},
156
+
{ HI6220_UART1_SRC, "uart1_src", uart1_src, ARRAY_SIZE(uart1_src), CLK_SET_RATE_PARENT, 0x400, 1, 1, CLK_MUX_HIWORD_MASK,},
157
+
{ HI6220_UART2_SRC, "uart2_src", uart2_src, ARRAY_SIZE(uart2_src), CLK_SET_RATE_PARENT, 0x400, 2, 1, CLK_MUX_HIWORD_MASK,},
158
+
{ HI6220_UART3_SRC, "uart3_src", uart3_src, ARRAY_SIZE(uart3_src), CLK_SET_RATE_PARENT, 0x400, 3, 1, CLK_MUX_HIWORD_MASK,},
159
+
{ HI6220_UART4_SRC, "uart4_src", uart4_src, ARRAY_SIZE(uart4_src), CLK_SET_RATE_PARENT, 0x400, 4, 1, CLK_MUX_HIWORD_MASK,},
160
+
{ HI6220_MMC0_MUX0, "mmc0_mux0", mmc0_mux0_p, ARRAY_SIZE(mmc0_mux0_p), CLK_SET_RATE_PARENT, 0x400, 5, 1, CLK_MUX_HIWORD_MASK,},
161
+
{ HI6220_MMC1_MUX0, "mmc1_mux0", mmc1_mux0_p, ARRAY_SIZE(mmc1_mux0_p), CLK_SET_RATE_PARENT, 0x400, 11, 1, CLK_MUX_HIWORD_MASK,},
162
+
{ HI6220_MMC2_MUX0, "mmc2_mux0", mmc2_mux0_p, ARRAY_SIZE(mmc2_mux0_p), CLK_SET_RATE_PARENT, 0x400, 12, 1, CLK_MUX_HIWORD_MASK,},
163
+
{ HI6220_MMC0_MUX1, "mmc0_mux1", mmc0_mux1_p, ARRAY_SIZE(mmc0_mux1_p), CLK_SET_RATE_PARENT, 0x400, 13, 1, CLK_MUX_HIWORD_MASK,},
164
+
{ HI6220_MMC1_MUX1, "mmc1_mux1", mmc1_mux1_p, ARRAY_SIZE(mmc1_mux1_p), CLK_SET_RATE_PARENT, 0x400, 14, 1, CLK_MUX_HIWORD_MASK,},
165
+
{ HI6220_MMC2_MUX1, "mmc2_mux1", mmc2_mux1_p, ARRAY_SIZE(mmc2_mux1_p), CLK_SET_RATE_PARENT, 0x400, 15, 1, CLK_MUX_HIWORD_MASK,},
166
+
};
167
+
168
+
static struct hi6220_divider_clock hi6220_div_clks_sys[] __initdata = {
169
+
{ HI6220_CLK_BUS, "clk_bus", "clk_300m", CLK_SET_RATE_PARENT, 0x490, 0, 4, 7, },
170
+
{ HI6220_MMC0_DIV, "mmc0_div", "mmc0_syspll", CLK_SET_RATE_PARENT, 0x494, 0, 6, 7, },
171
+
{ HI6220_MMC1_DIV, "mmc1_div", "mmc1_syspll", CLK_SET_RATE_PARENT, 0x498, 0, 6, 7, },
172
+
{ HI6220_MMC2_DIV, "mmc2_div", "mmc2_syspll", CLK_SET_RATE_PARENT, 0x49c, 0, 6, 7, },
173
+
{ HI6220_HIFI_DIV, "hifi_div", "hifi_sel", CLK_SET_RATE_PARENT, 0x4a0, 0, 4, 7, },
174
+
{ HI6220_BBPPLL0_DIV, "bbppll0_div", "bbppll_sel", CLK_SET_RATE_PARENT, 0x4a0, 8, 6, 15,},
175
+
{ HI6220_CS_DAPB, "cs_dapb", "picophy_src", CLK_SET_RATE_PARENT, 0x4a0, 24, 2, 31,},
176
+
{ HI6220_CS_ATB_DIV, "cs_atb_div", "cs_atb_syspll", CLK_SET_RATE_PARENT, 0x4a4, 0, 4, 7, },
177
+
};
178
+
179
+
static void __init hi6220_clk_sys_init(struct device_node *np)
180
+
{
181
+
struct hisi_clock_data *clk_data;
182
+
183
+
clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS);
184
+
if (!clk_data)
185
+
return;
186
+
187
+
hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys,
188
+
ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data);
189
+
190
+
hisi_clk_register_mux(hi6220_mux_clks_sys,
191
+
ARRAY_SIZE(hi6220_mux_clks_sys), clk_data);
192
+
193
+
hi6220_clk_register_divider(hi6220_div_clks_sys,
194
+
ARRAY_SIZE(hi6220_div_clks_sys), clk_data);
195
+
}
196
+
CLK_OF_DECLARE(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);
197
+
198
+
199
+
/* clocks in media controller */
200
+
static const char *clk_1000_1200_src[] __initdata = { "pll_gpu_gate", "media_syspll_src", };
201
+
static const char *clk_1440_1200_src[] __initdata = { "media_syspll_src", "media_pll_src", };
202
+
static const char *clk_1000_1440_src[] __initdata = { "pll_gpu_gate", "media_pll_src", };
203
+
204
+
static struct hisi_gate_clock hi6220_separated_gate_clks_media[] __initdata = {
205
+
{ HI6220_DSI_PCLK, "dsi_pclk", "vpucodec", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 0, 0, },
206
+
{ HI6220_G3D_PCLK, "g3d_pclk", "vpucodec", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 1, 0, },
207
+
{ HI6220_ACLK_CODEC_VPU, "aclk_codec_vpu", "ade_core_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 3, 0, },
208
+
{ HI6220_ISP_SCLK, "isp_sclk", "isp_sclk_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 5, 0, },
209
+
{ HI6220_ADE_CORE, "ade_core", "ade_core_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 6, 0, },
210
+
{ HI6220_MED_MMU, "media_mmu", "mmu_clk", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 8, 0, },
211
+
{ HI6220_CFG_CSI4PHY, "cfg_csi4phy", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 9, 0, },
212
+
{ HI6220_CFG_CSI2PHY, "cfg_csi2phy", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 10, 0, },
213
+
{ HI6220_ISP_SCLK_GATE, "isp_sclk_gate", "media_pll_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 11, 0, },
214
+
{ HI6220_ISP_SCLK_GATE1, "isp_sclk_gate1", "media_pll_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 12, 0, },
215
+
{ HI6220_ADE_CORE_GATE, "ade_core_gate", "media_pll_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 14, 0, },
216
+
{ HI6220_CODEC_VPU_GATE, "codec_vpu_gate", "clk_1000_1440", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 15, 0, },
217
+
{ HI6220_MED_SYSPLL, "media_syspll_src", "media_syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 17, 0, },
218
+
};
219
+
220
+
static struct hisi_mux_clock hi6220_mux_clks_media[] __initdata = {
221
+
{ HI6220_1440_1200, "clk_1440_1200", clk_1440_1200_src, ARRAY_SIZE(clk_1440_1200_src), CLK_SET_RATE_PARENT, 0x51c, 0, 1, 0, },
222
+
{ HI6220_1000_1200, "clk_1000_1200", clk_1000_1200_src, ARRAY_SIZE(clk_1000_1200_src), CLK_SET_RATE_PARENT, 0x51c, 1, 1, 0, },
223
+
{ HI6220_1000_1440, "clk_1000_1440", clk_1000_1440_src, ARRAY_SIZE(clk_1000_1440_src), CLK_SET_RATE_PARENT, 0x51c, 6, 1, 0, },
224
+
};
225
+
226
+
static struct hi6220_divider_clock hi6220_div_clks_media[] __initdata = {
227
+
{ HI6220_CODEC_JPEG, "codec_jpeg_aclk", "media_pll_src", CLK_SET_RATE_PARENT, 0xcbc, 0, 4, 23, },
228
+
{ HI6220_ISP_SCLK_SRC, "isp_sclk_src", "isp_sclk_gate", CLK_SET_RATE_PARENT, 0xcbc, 8, 4, 15, },
229
+
{ HI6220_ISP_SCLK1, "isp_sclk1", "isp_sclk_gate1", CLK_SET_RATE_PARENT, 0xcbc, 24, 4, 31, },
230
+
{ HI6220_ADE_CORE_SRC, "ade_core_src", "ade_core_gate", CLK_SET_RATE_PARENT, 0xcc0, 16, 3, 23, },
231
+
{ HI6220_ADE_PIX_SRC, "ade_pix_src", "clk_1440_1200", CLK_SET_RATE_PARENT, 0xcc0, 24, 6, 31, },
232
+
{ HI6220_G3D_CLK, "g3d_clk", "clk_1000_1200", CLK_SET_RATE_PARENT, 0xcc4, 8, 4, 15, },
233
+
{ HI6220_CODEC_VPU_SRC, "codec_vpu_src", "codec_vpu_gate", CLK_SET_RATE_PARENT, 0xcc4, 24, 6, 31, },
234
+
};
235
+
236
+
static void __init hi6220_clk_media_init(struct device_node *np)
237
+
{
238
+
struct hisi_clock_data *clk_data;
239
+
240
+
clk_data = hisi_clk_init(np, HI6220_MEDIA_NR_CLKS);
241
+
if (!clk_data)
242
+
return;
243
+
244
+
hisi_clk_register_gate_sep(hi6220_separated_gate_clks_media,
245
+
ARRAY_SIZE(hi6220_separated_gate_clks_media), clk_data);
246
+
247
+
hisi_clk_register_mux(hi6220_mux_clks_media,
248
+
ARRAY_SIZE(hi6220_mux_clks_media), clk_data);
249
+
250
+
hi6220_clk_register_divider(hi6220_div_clks_media,
251
+
ARRAY_SIZE(hi6220_div_clks_media), clk_data);
252
+
}
253
+
CLK_OF_DECLARE(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);
254
+
255
+
256
+
/* clocks in pmctrl */
257
+
static struct hisi_gate_clock hi6220_gate_clks_power[] __initdata = {
258
+
{ HI6220_PLL_GPU_GATE, "pll_gpu_gate", "gpupll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x8, 0, 0, },
259
+
{ HI6220_PLL1_DDR_GATE, "pll1_ddr_gate", "ddrpll1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x10, 0, 0, },
260
+
{ HI6220_PLL_DDR_GATE, "pll_ddr_gate", "ddrpll0", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x18, 0, 0, },
261
+
{ HI6220_PLL_MEDIA_GATE, "pll_media_gate", "media_pll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x38, 0, 0, },
262
+
{ HI6220_PLL0_BBP_GATE, "pll0_bbp_gate", "bbppll0", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x48, 0, 0, },
263
+
};
264
+
265
+
static struct hi6220_divider_clock hi6220_div_clks_power[] __initdata = {
266
+
{ HI6220_DDRC_SRC, "ddrc_src", "ddr_sel_src", CLK_SET_RATE_PARENT, 0x5a8, 0, 4, 0, },
267
+
{ HI6220_DDRC_AXI1, "ddrc_axi1", "ddrc_src", CLK_SET_RATE_PARENT, 0x5a8, 8, 2, 0, },
268
+
};
269
+
270
+
static void __init hi6220_clk_power_init(struct device_node *np)
271
+
{
272
+
struct hisi_clock_data *clk_data;
273
+
274
+
clk_data = hisi_clk_init(np, HI6220_POWER_NR_CLKS);
275
+
if (!clk_data)
276
+
return;
277
+
278
+
hisi_clk_register_gate(hi6220_gate_clks_power,
279
+
ARRAY_SIZE(hi6220_gate_clks_power), clk_data);
280
+
281
+
hi6220_clk_register_divider(hi6220_div_clks_power,
282
+
ARRAY_SIZE(hi6220_div_clks_power), clk_data);
283
+
}
284
+
CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init);
+29
drivers/clk/hisilicon/clk.c
+29
drivers/clk/hisilicon/clk.c
···
232
232
data->clk_data.clks[clks[i].id] = clk;
233
233
}
234
234
}
235
+
236
+
void __init hi6220_clk_register_divider(struct hi6220_divider_clock *clks,
237
+
int nums, struct hisi_clock_data *data)
238
+
{
239
+
struct clk *clk;
240
+
void __iomem *base = data->base;
241
+
int i;
242
+
243
+
for (i = 0; i < nums; i++) {
244
+
clk = hi6220_register_clkdiv(NULL, clks[i].name,
245
+
clks[i].parent_name,
246
+
clks[i].flags,
247
+
base + clks[i].offset,
248
+
clks[i].shift,
249
+
clks[i].width,
250
+
clks[i].mask_bit,
251
+
&hisi_clk_lock);
252
+
if (IS_ERR(clk)) {
253
+
pr_err("%s: failed to register clock %s\n",
254
+
__func__, clks[i].name);
255
+
continue;
256
+
}
257
+
258
+
if (clks[i].alias)
259
+
clk_register_clkdev(clk, clks[i].alias, NULL);
260
+
261
+
data->clk_data.clks[clks[i].id] = clk;
262
+
}
263
+
}
+29
-12
drivers/clk/hisilicon/clk.h
+29
-12
drivers/clk/hisilicon/clk.h
···
79
79
const char *alias;
80
80
};
81
81
82
+
struct hi6220_divider_clock {
83
+
unsigned int id;
84
+
const char *name;
85
+
const char *parent_name;
86
+
unsigned long flags;
87
+
unsigned long offset;
88
+
u8 shift;
89
+
u8 width;
90
+
u32 mask_bit;
91
+
const char *alias;
92
+
};
93
+
82
94
struct hisi_gate_clock {
83
95
unsigned int id;
84
96
const char *name;
···
106
94
const char *, unsigned long,
107
95
void __iomem *, u8,
108
96
u8, spinlock_t *);
97
+
struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
98
+
const char *parent_name, unsigned long flags, void __iomem *reg,
99
+
u8 shift, u8 width, u32 mask_bit, spinlock_t *lock);
109
100
110
-
struct hisi_clock_data __init *hisi_clk_init(struct device_node *, int);
111
-
void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *,
112
-
int, struct hisi_clock_data *);
113
-
void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,
114
-
int, struct hisi_clock_data *);
115
-
void __init hisi_clk_register_mux(struct hisi_mux_clock *, int,
116
-
struct hisi_clock_data *);
117
-
void __init hisi_clk_register_divider(struct hisi_divider_clock *,
101
+
struct hisi_clock_data *hisi_clk_init(struct device_node *, int);
102
+
void hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *,
118
103
int, struct hisi_clock_data *);
119
-
void __init hisi_clk_register_gate(struct hisi_gate_clock *,
120
-
int, struct hisi_clock_data *);
121
-
void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *,
122
-
int, struct hisi_clock_data *);
104
+
void hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,
105
+
int, struct hisi_clock_data *);
106
+
void hisi_clk_register_mux(struct hisi_mux_clock *, int,
107
+
struct hisi_clock_data *);
108
+
void hisi_clk_register_divider(struct hisi_divider_clock *,
109
+
int, struct hisi_clock_data *);
110
+
void hisi_clk_register_gate(struct hisi_gate_clock *,
111
+
int, struct hisi_clock_data *);
112
+
void hisi_clk_register_gate_sep(struct hisi_gate_clock *,
113
+
int, struct hisi_clock_data *);
114
+
void hi6220_clk_register_divider(struct hi6220_divider_clock *,
115
+
int, struct hisi_clock_data *);
123
116
#endif /* __HISI_CLK_H */
+156
drivers/clk/hisilicon/clkdivider-hi6220.c
+156
drivers/clk/hisilicon/clkdivider-hi6220.c
···
1
+
/*
2
+
* Hisilicon hi6220 SoC divider clock driver
3
+
*
4
+
* Copyright (c) 2015 Hisilicon Limited.
5
+
*
6
+
* Author: Bintian Wang <bintian.wang@huawei.com>
7
+
*
8
+
* This program is free software; you can redistribute it and/or modify
9
+
* it under the terms of the GNU General Public License version 2 as
10
+
* published by the Free Software Foundation.
11
+
*
12
+
*/
13
+
14
+
#include <linux/kernel.h>
15
+
#include <linux/clk-provider.h>
16
+
#include <linux/slab.h>
17
+
#include <linux/io.h>
18
+
#include <linux/err.h>
19
+
#include <linux/spinlock.h>
20
+
21
+
#define div_mask(width) ((1 << (width)) - 1)
22
+
23
+
/**
24
+
* struct hi6220_clk_divider - divider clock for hi6220
25
+
*
26
+
* @hw: handle between common and hardware-specific interfaces
27
+
* @reg: register containing divider
28
+
* @shift: shift to the divider bit field
29
+
* @width: width of the divider bit field
30
+
* @mask: mask for setting divider rate
31
+
* @table: the div table that the divider supports
32
+
* @lock: register lock
33
+
*/
34
+
struct hi6220_clk_divider {
35
+
struct clk_hw hw;
36
+
void __iomem *reg;
37
+
u8 shift;
38
+
u8 width;
39
+
u32 mask;
40
+
const struct clk_div_table *table;
41
+
spinlock_t *lock;
42
+
};
43
+
44
+
#define to_hi6220_clk_divider(_hw) \
45
+
container_of(_hw, struct hi6220_clk_divider, hw)
46
+
47
+
static unsigned long hi6220_clkdiv_recalc_rate(struct clk_hw *hw,
48
+
unsigned long parent_rate)
49
+
{
50
+
unsigned int val;
51
+
struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw);
52
+
53
+
val = readl_relaxed(dclk->reg) >> dclk->shift;
54
+
val &= div_mask(dclk->width);
55
+
56
+
return divider_recalc_rate(hw, parent_rate, val, dclk->table,
57
+
CLK_DIVIDER_ROUND_CLOSEST);
58
+
}
59
+
60
+
static long hi6220_clkdiv_round_rate(struct clk_hw *hw, unsigned long rate,
61
+
unsigned long *prate)
62
+
{
63
+
struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw);
64
+
65
+
return divider_round_rate(hw, rate, prate, dclk->table,
66
+
dclk->width, CLK_DIVIDER_ROUND_CLOSEST);
67
+
}
68
+
69
+
static int hi6220_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate,
70
+
unsigned long parent_rate)
71
+
{
72
+
int value;
73
+
unsigned long flags = 0;
74
+
u32 data;
75
+
struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw);
76
+
77
+
value = divider_get_val(rate, parent_rate, dclk->table,
78
+
dclk->width, CLK_DIVIDER_ROUND_CLOSEST);
79
+
80
+
if (dclk->lock)
81
+
spin_lock_irqsave(dclk->lock, flags);
82
+
83
+
data = readl_relaxed(dclk->reg);
84
+
data &= ~(div_mask(dclk->width) << dclk->shift);
85
+
data |= value << dclk->shift;
86
+
data |= dclk->mask;
87
+
88
+
writel_relaxed(data, dclk->reg);
89
+
90
+
if (dclk->lock)
91
+
spin_unlock_irqrestore(dclk->lock, flags);
92
+
93
+
return 0;
94
+
}
95
+
96
+
static const struct clk_ops hi6220_clkdiv_ops = {
97
+
.recalc_rate = hi6220_clkdiv_recalc_rate,
98
+
.round_rate = hi6220_clkdiv_round_rate,
99
+
.set_rate = hi6220_clkdiv_set_rate,
100
+
};
101
+
102
+
struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
103
+
const char *parent_name, unsigned long flags, void __iomem *reg,
104
+
u8 shift, u8 width, u32 mask_bit, spinlock_t *lock)
105
+
{
106
+
struct hi6220_clk_divider *div;
107
+
struct clk *clk;
108
+
struct clk_init_data init;
109
+
struct clk_div_table *table;
110
+
u32 max_div, min_div;
111
+
int i;
112
+
113
+
/* allocate the divider */
114
+
div = kzalloc(sizeof(*div), GFP_KERNEL);
115
+
if (!div)
116
+
return ERR_PTR(-ENOMEM);
117
+
118
+
/* Init the divider table */
119
+
max_div = div_mask(width) + 1;
120
+
min_div = 1;
121
+
122
+
table = kcalloc(max_div + 1, sizeof(*table), GFP_KERNEL);
123
+
if (!table) {
124
+
kfree(div);
125
+
return ERR_PTR(-ENOMEM);
126
+
}
127
+
128
+
for (i = 0; i < max_div; i++) {
129
+
table[i].div = min_div + i;
130
+
table[i].val = table[i].div - 1;
131
+
}
132
+
133
+
init.name = name;
134
+
init.ops = &hi6220_clkdiv_ops;
135
+
init.flags = flags;
136
+
init.parent_names = parent_name ? &parent_name : NULL;
137
+
init.num_parents = parent_name ? 1 : 0;
138
+
139
+
/* struct hi6220_clk_divider assignments */
140
+
div->reg = reg;
141
+
div->shift = shift;
142
+
div->width = width;
143
+
div->mask = mask_bit ? BIT(mask_bit) : 0;
144
+
div->lock = lock;
145
+
div->hw.init = &init;
146
+
div->table = table;
147
+
148
+
/* register the clock */
149
+
clk = clk_register(dev, &div->hw);
150
+
if (IS_ERR(clk)) {
151
+
kfree(table);
152
+
kfree(div);
153
+
}
154
+
155
+
return clk;
156
+
}
+173
include/dt-bindings/clock/hi6220-clock.h
+173
include/dt-bindings/clock/hi6220-clock.h
···
1
+
/*
2
+
* Copyright (c) 2015 Hisilicon Limited.
3
+
*
4
+
* Author: Bintian Wang <bintian.wang@huawei.com>
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
11
+
#ifndef __DT_BINDINGS_CLOCK_HI6220_H
12
+
#define __DT_BINDINGS_CLOCK_HI6220_H
13
+
14
+
/* clk in Hi6220 AO (always on) controller */
15
+
#define HI6220_NONE_CLOCK 0
16
+
17
+
/* fixed rate clocks */
18
+
#define HI6220_REF32K 1
19
+
#define HI6220_CLK_TCXO 2
20
+
#define HI6220_MMC1_PAD 3
21
+
#define HI6220_MMC2_PAD 4
22
+
#define HI6220_MMC0_PAD 5
23
+
#define HI6220_PLL_BBP 6
24
+
#define HI6220_PLL_GPU 7
25
+
#define HI6220_PLL1_DDR 8
26
+
#define HI6220_PLL_SYS 9
27
+
#define HI6220_PLL_SYS_MEDIA 10
28
+
#define HI6220_DDR_SRC 11
29
+
#define HI6220_PLL_MEDIA 12
30
+
#define HI6220_PLL_DDR 13
31
+
32
+
/* fixed factor clocks */
33
+
#define HI6220_300M 14
34
+
#define HI6220_150M 15
35
+
#define HI6220_PICOPHY_SRC 16
36
+
#define HI6220_MMC0_SRC_SEL 17
37
+
#define HI6220_MMC1_SRC_SEL 18
38
+
#define HI6220_MMC2_SRC_SEL 19
39
+
#define HI6220_VPU_CODEC 20
40
+
#define HI6220_MMC0_SMP 21
41
+
#define HI6220_MMC1_SMP 22
42
+
#define HI6220_MMC2_SMP 23
43
+
44
+
/* gate clocks */
45
+
#define HI6220_WDT0_PCLK 24
46
+
#define HI6220_WDT1_PCLK 25
47
+
#define HI6220_WDT2_PCLK 26
48
+
#define HI6220_TIMER0_PCLK 27
49
+
#define HI6220_TIMER1_PCLK 28
50
+
#define HI6220_TIMER2_PCLK 29
51
+
#define HI6220_TIMER3_PCLK 30
52
+
#define HI6220_TIMER4_PCLK 31
53
+
#define HI6220_TIMER5_PCLK 32
54
+
#define HI6220_TIMER6_PCLK 33
55
+
#define HI6220_TIMER7_PCLK 34
56
+
#define HI6220_TIMER8_PCLK 35
57
+
#define HI6220_UART0_PCLK 36
58
+
59
+
#define HI6220_AO_NR_CLKS 37
60
+
61
+
/* clk in Hi6220 systrl */
62
+
/* gate clock */
63
+
#define HI6220_MMC0_CLK 1
64
+
#define HI6220_MMC0_CIUCLK 2
65
+
#define HI6220_MMC1_CLK 3
66
+
#define HI6220_MMC1_CIUCLK 4
67
+
#define HI6220_MMC2_CLK 5
68
+
#define HI6220_MMC2_CIUCLK 6
69
+
#define HI6220_USBOTG_HCLK 7
70
+
#define HI6220_CLK_PICOPHY 8
71
+
#define HI6220_HIFI 9
72
+
#define HI6220_DACODEC_PCLK 10
73
+
#define HI6220_EDMAC_ACLK 11
74
+
#define HI6220_CS_ATB 12
75
+
#define HI6220_I2C0_CLK 13
76
+
#define HI6220_I2C1_CLK 14
77
+
#define HI6220_I2C2_CLK 15
78
+
#define HI6220_I2C3_CLK 16
79
+
#define HI6220_UART1_PCLK 17
80
+
#define HI6220_UART2_PCLK 18
81
+
#define HI6220_UART3_PCLK 19
82
+
#define HI6220_UART4_PCLK 20
83
+
#define HI6220_SPI_CLK 21
84
+
#define HI6220_TSENSOR_CLK 22
85
+
#define HI6220_MMU_CLK 23
86
+
#define HI6220_HIFI_SEL 24
87
+
#define HI6220_MMC0_SYSPLL 25
88
+
#define HI6220_MMC1_SYSPLL 26
89
+
#define HI6220_MMC2_SYSPLL 27
90
+
#define HI6220_MMC0_SEL 28
91
+
#define HI6220_MMC1_SEL 29
92
+
#define HI6220_BBPPLL_SEL 30
93
+
#define HI6220_MEDIA_PLL_SRC 31
94
+
#define HI6220_MMC2_SEL 32
95
+
#define HI6220_CS_ATB_SYSPLL 33
96
+
97
+
/* mux clocks */
98
+
#define HI6220_MMC0_SRC 34
99
+
#define HI6220_MMC0_SMP_IN 35
100
+
#define HI6220_MMC1_SRC 36
101
+
#define HI6220_MMC1_SMP_IN 37
102
+
#define HI6220_MMC2_SRC 38
103
+
#define HI6220_MMC2_SMP_IN 39
104
+
#define HI6220_HIFI_SRC 40
105
+
#define HI6220_UART1_SRC 41
106
+
#define HI6220_UART2_SRC 42
107
+
#define HI6220_UART3_SRC 43
108
+
#define HI6220_UART4_SRC 44
109
+
#define HI6220_MMC0_MUX0 45
110
+
#define HI6220_MMC1_MUX0 46
111
+
#define HI6220_MMC2_MUX0 47
112
+
#define HI6220_MMC0_MUX1 48
113
+
#define HI6220_MMC1_MUX1 49
114
+
#define HI6220_MMC2_MUX1 50
115
+
116
+
/* divider clocks */
117
+
#define HI6220_CLK_BUS 51
118
+
#define HI6220_MMC0_DIV 52
119
+
#define HI6220_MMC1_DIV 53
120
+
#define HI6220_MMC2_DIV 54
121
+
#define HI6220_HIFI_DIV 55
122
+
#define HI6220_BBPPLL0_DIV 56
123
+
#define HI6220_CS_DAPB 57
124
+
#define HI6220_CS_ATB_DIV 58
125
+
126
+
#define HI6220_SYS_NR_CLKS 59
127
+
128
+
/* clk in Hi6220 media controller */
129
+
/* gate clocks */
130
+
#define HI6220_DSI_PCLK 1
131
+
#define HI6220_G3D_PCLK 2
132
+
#define HI6220_ACLK_CODEC_VPU 3
133
+
#define HI6220_ISP_SCLK 4
134
+
#define HI6220_ADE_CORE 5
135
+
#define HI6220_MED_MMU 6
136
+
#define HI6220_CFG_CSI4PHY 7
137
+
#define HI6220_CFG_CSI2PHY 8
138
+
#define HI6220_ISP_SCLK_GATE 9
139
+
#define HI6220_ISP_SCLK_GATE1 10
140
+
#define HI6220_ADE_CORE_GATE 11
141
+
#define HI6220_CODEC_VPU_GATE 12
142
+
#define HI6220_MED_SYSPLL 13
143
+
144
+
/* mux clocks */
145
+
#define HI6220_1440_1200 14
146
+
#define HI6220_1000_1200 15
147
+
#define HI6220_1000_1440 16
148
+
149
+
/* divider clocks */
150
+
#define HI6220_CODEC_JPEG 17
151
+
#define HI6220_ISP_SCLK_SRC 18
152
+
#define HI6220_ISP_SCLK1 19
153
+
#define HI6220_ADE_CORE_SRC 20
154
+
#define HI6220_ADE_PIX_SRC 21
155
+
#define HI6220_G3D_CLK 22
156
+
#define HI6220_CODEC_VPU_SRC 23
157
+
158
+
#define HI6220_MEDIA_NR_CLKS 24
159
+
160
+
/* clk in Hi6220 power controller */
161
+
/* gate clocks */
162
+
#define HI6220_PLL_GPU_GATE 1
163
+
#define HI6220_PLL1_DDR_GATE 2
164
+
#define HI6220_PLL_DDR_GATE 3
165
+
#define HI6220_PLL_MEDIA_GATE 4
166
+
#define HI6220_PLL0_BBP_GATE 5
167
+
168
+
/* divider clocks */
169
+
#define HI6220_DDRC_SRC 6
170
+
#define HI6220_DDRC_AXI1 7
171
+
172
+
#define HI6220_POWER_NR_CLKS 8
173
+
#endif