tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (21 commits)
Blackfin: define HARDIRQ_BITS again for now
arch/blackfin: Add kmalloc NULL tests
Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions
Blackfin: work around anomaly 05000189
Blackfin: drop per-cpu loops_per_jiffy tracking
Blackfin: fix bugs in GPIO resume code
Blackfin: bf537-stamp: fix irq decl for AD7142
Blackfin: fix handling of IPEND in interrupt context save
Blackfin: drop duplicate runtime checking of anomaly 05000448
Blackfin: fix incomplete renaming of the bfin-twi-lcd driver
Blackfin: fix wrong CTS inversion
Blackfin: update handling of anomaly 364 (wrong rev id in BF527-0.1)
Blackfin: fix early_dma_memcpy() handling of busy channels
Blackfin: handle BF561 Core B memory regions better when SMP=n
Blackfin: fix miscompilation in lshrdi3
Blackfin: fix silent crash when no uClinux MTD filesystem exists
Blackfin: restore exception banner when dumping crash info
Blackfin: work around anomaly 05000281
Blackfin: update anomaly lists to match latest sheets/usage
Blackfin: drop dead flash_probe call
...

Linus Torvalds ae42b9e1 6cdbf734

+143 -113
unified split
+4 -3
arch/blackfin/include/asm/context.S
··· 223 223 [--sp] = RETN; 224 224 [--sp] = RETE; 225 225 [--sp] = SEQSTAT; 226 - #ifdef CONFIG_KGDB 227 - r1.l = lo(IPEND); 228 - r1.h = hi(IPEND); 226 + #ifdef CONFIG_DEBUG_KERNEL 227 + p1.l = lo(IPEND); 228 + p1.h = hi(IPEND); 229 + r1 = [p1]; 229 230 [--sp] = r1; 230 231 #else 231 232 [--sp] = r0; /* Skip IPEND as well. */
-1
arch/blackfin/include/asm/cpu.h
··· 32 32 struct task_struct *idle; 33 33 unsigned int imemctl; 34 34 unsigned int dmemctl; 35 - unsigned long loops_per_jiffy; 36 35 unsigned long dcache_invld_count; 37 36 unsigned long icache_invld_count; 38 37 };
+3
arch/blackfin/include/asm/hardirq.h
··· 6 6 extern void ack_bad_irq(unsigned int irq); 7 7 #define ack_bad_irq ack_bad_irq 8 8 9 + /* Define until common code gets sane defaults */ 10 + #define HARDIRQ_BITS 9 11 + 9 12 #include <asm-generic/hardirq.h> 10 13 11 14 #endif
+7 -14
arch/blackfin/include/asm/processor.h
··· 105 105 /* Always use CHIPID, to work around ANOMALY_05000234 */ 106 106 uint32_t revid = (bfin_read_CHIPID() & CHIPID_VERSION) >> 28; 107 107 108 - #ifdef CONFIG_BF52x 109 - /* ANOMALY_05000357 108 + #ifdef _BOOTROM_GET_DXE_ADDRESS_TWI 109 + /* 110 + * ANOMALY_05000364 110 111 * Incorrect Revision Number in DSPID Register 111 112 */ 112 - if (revid == 0) 113 - switch (bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI)) { 114 - case 0x0010: 115 - revid = 0; 116 - break; 117 - case 0x2796: 118 - revid = 1; 119 - break; 120 - default: 121 - revid = 0xFFFF; 122 - break; 123 - } 113 + if (ANOMALY_05000364 && 114 + bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI) == 0x2796) 115 + revid = 1; 124 116 #endif 117 + 125 118 return revid; 126 119 } 127 120
+19 -20
arch/blackfin/kernel/bfin_dma_5xx.c
··· 253 253 BUG_ON(src % 4); 254 254 BUG_ON(size % 4); 255 255 256 + src_ch = 0; 257 + /* Find an avalible memDMA channel */ 258 + while (1) { 259 + if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) { 260 + dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR; 261 + src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR; 262 + } else { 263 + dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR; 264 + src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR; 265 + } 266 + 267 + if (!bfin_read16(&src_ch->cfg)) 268 + break; 269 + else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) { 270 + bfin_write16(&src_ch->cfg, 0); 271 + break; 272 + } 273 + } 274 + 256 275 /* Force a sync in case a previous config reset on this channel 257 276 * occurred. This is needed so subsequent writes to DMA registers 258 277 * are not spuriously lost/corrupted. 259 278 */ 260 279 __builtin_bfin_ssync(); 261 - 262 - src_ch = 0; 263 - /* Find an avalible memDMA channel */ 264 - while (1) { 265 - if (!src_ch || src_ch == (struct dma_register *)MDMA_S1_NEXT_DESC_PTR) { 266 - dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR; 267 - src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR; 268 - } else { 269 - dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR; 270 - src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR; 271 - } 272 - 273 - if (!bfin_read16(&src_ch->cfg)) { 274 - break; 275 - } else { 276 - if (bfin_read16(&src_ch->irq_status) & DMA_DONE) 277 - bfin_write16(&src_ch->cfg, 0); 278 - } 279 - 280 - } 281 280 282 281 /* Destination */ 283 282 bfin_write32(&dst_ch->start_addr, dst);
+2 -4
arch/blackfin/kernel/bfin_gpio.c
··· 686 686 *port_fer[bank] = gpio_bank_saved[bank].fer; 687 687 #endif 688 688 gpio_array[bank]->inen = gpio_bank_saved[bank].inen; 689 + gpio_array[bank]->data_set = gpio_bank_saved[bank].data 690 + & gpio_bank_saved[bank].dir; 689 691 gpio_array[bank]->dir = gpio_bank_saved[bank].dir; 690 692 gpio_array[bank]->polar = gpio_bank_saved[bank].polar; 691 693 gpio_array[bank]->edge = gpio_bank_saved[bank].edge; 692 694 gpio_array[bank]->both = gpio_bank_saved[bank].both; 693 - 694 - gpio_array[bank]->data_set = gpio_bank_saved[bank].data 695 - | gpio_bank_saved[bank].dir; 696 - 697 695 gpio_array[bank]->maska = gpio_bank_saved[bank].maska; 698 696 } 699 697 AWA_DUMMY_READ(maska);
+17 -6
arch/blackfin/kernel/cplb-nompu/cplbinit.c
··· 72 72 } 73 73 74 74 /* Cover L1 memory. One 4M area for code and data each is enough. */ 75 - if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { 76 - d_tbl[i_d].addr = L1_DATA_A_START; 77 - d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; 75 + if (cpu == 0) { 76 + if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { 77 + d_tbl[i_d].addr = L1_DATA_A_START; 78 + d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; 79 + } 80 + i_tbl[i_i].addr = L1_CODE_START; 81 + i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; 78 82 } 79 - i_tbl[i_i].addr = L1_CODE_START; 80 - i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; 81 - 83 + #ifdef CONFIG_SMP 84 + else { 85 + if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { 86 + d_tbl[i_d].addr = COREB_L1_DATA_A_START; 87 + d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; 88 + } 89 + i_tbl[i_i].addr = COREB_L1_CODE_START; 90 + i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; 91 + } 92 + #endif 82 93 first_switched_dcplb = i_d; 83 94 first_switched_icplb = i_i; 84 95
+7 -7
arch/blackfin/kernel/process.c
··· 361 361 int in_mem_const(unsigned long addr, unsigned long size, 362 362 unsigned long const_addr, unsigned long const_size) 363 363 { 364 - return in_mem_const_off(addr, 0, size, const_addr, const_size); 364 + return in_mem_const_off(addr, size, 0, const_addr, const_size); 365 365 } 366 366 #define IN_ASYNC(bnum, bctlnum) \ 367 367 ({ \ ··· 390 390 if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH)) 391 391 return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; 392 392 #ifdef COREB_L1_CODE_START 393 - if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) 393 + if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH)) 394 394 return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA; 395 395 if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) 396 396 return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT; 397 - if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) 397 + if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH)) 398 398 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; 399 - if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) 399 + if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH)) 400 400 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; 401 401 #endif 402 402 if (in_mem_const(addr, size, L2_START, L2_LENGTH)) ··· 472 472 if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH)) 473 473 return 1; 474 474 #ifdef COREB_L1_CODE_START 475 - if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) 475 + if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH)) 476 476 return 1; 477 477 if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) 478 478 return 1; 479 - if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) 479 + if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH)) 480 480 return 1; 481 - if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) 481 + if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH)) 482 482 return 1; 483 483 #endif 484 484 if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
+18 -24
arch/blackfin/kernel/setup.c
··· 168 168 struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu); 169 169 170 170 cpudata->idle = current; 171 - cpudata->loops_per_jiffy = loops_per_jiffy; 172 171 cpudata->imemctl = bfin_read_IMEM_CONTROL(); 173 172 cpudata->dmemctl = bfin_read_DMEM_CONTROL(); 174 173 } ··· 567 568 # endif /* ANOMALY_05000263 */ 568 569 # endif /* CONFIG_ROMFS_FS */ 569 570 570 - memory_end -= mtd_size; 571 + /* Since the default MTD_UCLINUX has no magic number, we just blindly 572 + * read 8 past the end of the kernel's image, and look at it. 573 + * When no image is attached, mtd_size is set to a random number 574 + * Do some basic sanity checks before operating on things 575 + */ 576 + if (mtd_size == 0 || memory_end <= mtd_size) { 577 + pr_emerg("Could not find valid ram mtd attached.\n"); 578 + } else { 579 + memory_end -= mtd_size; 571 580 572 - if (mtd_size == 0) { 573 - console_init(); 574 - panic("Don't boot kernel without rootfs attached."); 581 + /* Relocate MTD image to the top of memory after the uncached memory area */ 582 + uclinux_ram_map.phys = memory_mtd_start = memory_end; 583 + uclinux_ram_map.size = mtd_size; 584 + pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n", 585 + _end, mtd_size, (void *)memory_mtd_start); 586 + dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); 575 587 } 576 - 577 - /* Relocate MTD image to the top of memory after the uncached memory area */ 578 - uclinux_ram_map.phys = memory_mtd_start = memory_end; 579 - uclinux_ram_map.size = mtd_size; 580 - dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); 581 588 #endif /* CONFIG_MTD_UCLINUX */ 582 589 583 590 #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) ··· 873 868 else 874 869 printk(KERN_CONT "and Disabled\n"); 875 870 876 - #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH) 877 - /* we need to initialize the Flashrom device here since we might 878 - * do things with flash early on in the boot 879 - */ 880 - flash_probe(); 881 - #endif 882 - 883 871 printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF); 884 872 885 873 /* Newer parts mirror SWRST bits in SYSCR */ ··· 935 937 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n", 936 938 CPU, bfin_revid()); 937 939 } 938 - 939 - /* We can't run on BF548-0.1 due to ANOMALY 05000448 */ 940 - if (bfin_cpuid() == 0x27de && bfin_revid() == 1) 941 - panic("You can't run on this processor due to 05000448"); 942 940 943 941 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); 944 942 ··· 1158 1164 sclk/1000000, sclk%1000000); 1159 1165 seq_printf(m, "bogomips\t: %lu.%02lu\n" 1160 1166 "Calibration\t: %lu loops\n", 1161 - (cpudata->loops_per_jiffy * HZ) / 500000, 1162 - ((cpudata->loops_per_jiffy * HZ) / 5000) % 100, 1163 - (cpudata->loops_per_jiffy * HZ)); 1167 + (loops_per_jiffy * HZ) / 500000, 1168 + ((loops_per_jiffy * HZ) / 5000) % 100, 1169 + (loops_per_jiffy * HZ)); 1164 1170 1165 1171 /* Check Cache configutation */ 1166 1172 switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
+6 -3
arch/blackfin/kernel/traps.c
··· 570 570 if (kernel_mode_regs(fp) || (current && !current->mm)) { 571 571 console_verbose(); 572 572 oops_in_progress = 1; 573 - if (strerror) 574 - verbose_printk(strerror); 575 573 } 576 574 577 575 if (sig != SIGTRAP) { 576 + if (strerror) 577 + verbose_printk(strerror); 578 + 578 579 dump_bfin_process(fp); 579 580 dump_bfin_mem(fp); 580 581 show_regs(fp); ··· 620 619 force_sig_info(sig, &info, current); 621 620 } 622 621 623 - if (ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8)) 622 + if ((ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8)) || 623 + (ANOMALY_05000281 && trapnr == VEC_HWERR) || 624 + (ANOMALY_05000189 && (trapnr == VEC_CPLB_I_VL || trapnr == VEC_CPLB_VL))) 624 625 fp->pc = SAFE_USER_INSTRUCTION; 625 626 626 627 traps_done:
+1 -15
arch/blackfin/lib/lshrdi3.c
··· 27 27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 28 28 */ 29 29 30 - #define BITS_PER_UNIT 8 31 - 32 - typedef int SItype __attribute__ ((mode(SI))); 33 - typedef unsigned int USItype __attribute__ ((mode(SI))); 34 - typedef int DItype __attribute__ ((mode(DI))); 35 - typedef int word_type __attribute__ ((mode(__word__))); 36 - 37 - struct DIstruct { 38 - SItype high, low; 39 - }; 40 - 41 - typedef union { 42 - struct DIstruct s; 43 - DItype ll; 44 - } DIunion; 30 + #include "gcclib.h" 45 31 46 32 #ifdef CONFIG_ARITHMETIC_OPS_L1 47 33 DItype __lshrdi3(DItype u, word_type b)__attribute__((l1_text));
+1 -1
arch/blackfin/mach-bf518/boards/ezbrd.c
··· 534 534 #endif 535 535 536 536 static struct i2c_board_info __initdata bfin_i2c_board_info[] = { 537 - #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) 537 + #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) 538 538 { 539 539 I2C_BOARD_INFO("pcf8574_lcd", 0x22), 540 540 },
+2
arch/blackfin/mach-bf518/include/mach/anomaly.h
··· 82 82 #define ANOMALY_05000179 (0) 83 83 #define ANOMALY_05000182 (0) 84 84 #define ANOMALY_05000183 (0) 85 + #define ANOMALY_05000189 (0) 85 86 #define ANOMALY_05000198 (0) 86 87 #define ANOMALY_05000202 (0) 87 88 #define ANOMALY_05000215 (0) ··· 118 117 #define ANOMALY_05000357 (0) 119 118 #define ANOMALY_05000362 (1) 120 119 #define ANOMALY_05000363 (0) 120 + #define ANOMALY_05000364 (0) 121 121 #define ANOMALY_05000371 (0) 122 122 #define ANOMALY_05000380 (0) 123 123 #define ANOMALY_05000386 (0)
+1 -1
arch/blackfin/mach-bf527/boards/cm_bf527.c
··· 793 793 #endif 794 794 795 795 static struct i2c_board_info __initdata bfin_i2c_board_info[] = { 796 - #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) 796 + #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) 797 797 { 798 798 I2C_BOARD_INFO("pcf8574_lcd", 0x22), 799 799 .type = "pcf8574_lcd",
+1 -1
arch/blackfin/mach-bf527/boards/ezbrd.c
··· 591 591 #endif 592 592 593 593 static struct i2c_board_info __initdata bfin_i2c_board_info[] = { 594 - #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) 594 + #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) 595 595 { 596 596 I2C_BOARD_INFO("pcf8574_lcd", 0x22), 597 597 },
+1 -1
arch/blackfin/mach-bf527/boards/ezkit.c
··· 858 858 #endif 859 859 860 860 static struct i2c_board_info __initdata bfin_i2c_board_info[] = { 861 - #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) 861 + #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) 862 862 { 863 863 I2C_BOARD_INFO("pcf8574_lcd", 0x22), 864 864 },
+3 -1
arch/blackfin/mach-bf527/include/mach/anomaly.h
··· 176 176 #define ANOMALY_05000443 (1) 177 177 /* The WURESET Bit in the SYSCR Register is not Functional */ 178 178 #define ANOMALY_05000445 (1) 179 + /* USB DMA Short Packet Data Corruption */ 180 + #define ANOMALY_05000450 (1) 179 181 /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ 180 182 #define ANOMALY_05000451 (1) 181 183 /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ ··· 203 201 #define ANOMALY_05000179 (0) 204 202 #define ANOMALY_05000182 (0) 205 203 #define ANOMALY_05000183 (0) 204 + #define ANOMALY_05000189 (0) 206 205 #define ANOMALY_05000198 (0) 207 206 #define ANOMALY_05000202 (0) 208 207 #define ANOMALY_05000215 (0) ··· 241 238 #define ANOMALY_05000412 (0) 242 239 #define ANOMALY_05000447 (0) 243 240 #define ANOMALY_05000448 (0) 244 - #define ANOMALY_05000450 (0) 245 241 246 242 #endif
+1 -1
arch/blackfin/mach-bf533/boards/stamp.c
··· 453 453 .irq = 39, 454 454 }, 455 455 #endif 456 - #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) 456 + #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) 457 457 { 458 458 I2C_BOARD_INFO("pcf8574_lcd", 0x22), 459 459 },
+1
arch/blackfin/mach-bf533/include/mach/anomaly.h
··· 335 335 #define ANOMALY_05000323 (0) 336 336 #define ANOMALY_05000353 (1) 337 337 #define ANOMALY_05000362 (1) 338 + #define ANOMALY_05000364 (0) 338 339 #define ANOMALY_05000380 (0) 339 340 #define ANOMALY_05000386 (1) 340 341 #define ANOMALY_05000389 (0)
+2 -2
arch/blackfin/mach-bf537/boards/stamp.c
··· 1313 1313 #if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE) 1314 1314 { 1315 1315 I2C_BOARD_INFO("ad7142_joystick", 0x2C), 1316 - .irq = IRQ_PF5, 1316 + .irq = IRQ_PG5, 1317 1317 }, 1318 1318 #endif 1319 - #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) 1319 + #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) 1320 1320 { 1321 1321 I2C_BOARD_INFO("pcf8574_lcd", 0x22), 1322 1322 },
+2
arch/blackfin/mach-bf537/include/mach/anomaly.h
··· 167 167 #define ANOMALY_05000179 (0) 168 168 #define ANOMALY_05000182 (0) 169 169 #define ANOMALY_05000183 (0) 170 + #define ANOMALY_05000189 (0) 170 171 #define ANOMALY_05000198 (0) 171 172 #define ANOMALY_05000202 (0) 172 173 #define ANOMALY_05000215 (0) ··· 187 186 #define ANOMALY_05000353 (1) 188 187 #define ANOMALY_05000362 (1) 189 188 #define ANOMALY_05000363 (0) 189 + #define ANOMALY_05000364 (0) 190 190 #define ANOMALY_05000380 (0) 191 191 #define ANOMALY_05000386 (1) 192 192 #define ANOMALY_05000389 (0)
+2
arch/blackfin/mach-bf538/include/mach/anomaly.h
··· 137 137 #define ANOMALY_05000158 (0) 138 138 #define ANOMALY_05000171 (0) 139 139 #define ANOMALY_05000182 (0) 140 + #define ANOMALY_05000189 (0) 140 141 #define ANOMALY_05000198 (0) 141 142 #define ANOMALY_05000202 (0) 142 143 #define ANOMALY_05000215 (0) ··· 161 160 #define ANOMALY_05000353 (1) 162 161 #define ANOMALY_05000362 (1) 163 162 #define ANOMALY_05000363 (0) 163 + #define ANOMALY_05000364 (0) 164 164 #define ANOMALY_05000380 (0) 165 165 #define ANOMALY_05000386 (1) 166 166 #define ANOMALY_05000389 (0)
+1 -1
arch/blackfin/mach-bf548/boards/ezkit.c
··· 864 864 865 865 #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ 866 866 static struct i2c_board_info __initdata bfin_i2c_board_info1[] = { 867 - #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) 867 + #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) 868 868 { 869 869 I2C_BOARD_INFO("pcf8574_lcd", 0x22), 870 870 },
+2
arch/blackfin/mach-bf548/include/mach/anomaly.h
··· 195 195 #define ANOMALY_05000179 (0) 196 196 #define ANOMALY_05000182 (0) 197 197 #define ANOMALY_05000183 (0) 198 + #define ANOMALY_05000189 (0) 198 199 #define ANOMALY_05000198 (0) 199 200 #define ANOMALY_05000202 (0) 200 201 #define ANOMALY_05000215 (0) ··· 227 226 #define ANOMALY_05000323 (0) 228 227 #define ANOMALY_05000362 (1) 229 228 #define ANOMALY_05000363 (0) 229 + #define ANOMALY_05000364 (0) 230 230 #define ANOMALY_05000380 (0) 231 231 #define ANOMALY_05000400 (0) 232 232 #define ANOMALY_05000412 (0)
+1
arch/blackfin/mach-bf561/include/mach/anomaly.h
··· 288 288 #define ANOMALY_05000273 (0) 289 289 #define ANOMALY_05000311 (0) 290 290 #define ANOMALY_05000353 (1) 291 + #define ANOMALY_05000364 (0) 291 292 #define ANOMALY_05000380 (0) 292 293 #define ANOMALY_05000386 (1) 293 294 #define ANOMALY_05000389 (0)
+22 -1
arch/blackfin/mach-bf561/include/mach/mem_map.h
··· 37 37 38 38 /* Memory Map for ADSP-BF561 processors */ 39 39 40 - #ifdef CONFIG_BF561 41 40 #define COREA_L1_CODE_START 0xFFA00000 42 41 #define COREA_L1_DATA_A_START 0xFF800000 43 42 #define COREA_L1_DATA_B_START 0xFF900000 ··· 73 74 #define BFIN_DCACHESIZE (0*1024) 74 75 #define BFIN_DSUPBANKS 0 75 76 #endif /*CONFIG_BFIN_DCACHE*/ 77 + 78 + /* 79 + * If we are in SMP mode, then the cache settings of Core B will match 80 + * the settings of Core A. If we aren't, then we assume Core B is not 81 + * using any cache. This allows the rest of the kernel to work with 82 + * the core in either mode as we are only loading user code into it and 83 + * it is the user's problem to make sure they aren't doing something 84 + * stupid there. 85 + * 86 + * Note that we treat the L1 code region as a contiguous blob to make 87 + * the rest of the kernel simpler. Easier to check one region than a 88 + * bunch of small ones. Again, possible misbehavior here is the fault 89 + * of the user -- don't try to use memory that doesn't exist. 90 + */ 91 + #ifdef CONFIG_SMP 92 + # define COREB_L1_CODE_LENGTH L1_CODE_LENGTH 93 + # define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH 94 + # define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH 95 + #else 96 + # define COREB_L1_CODE_LENGTH 0x14000 97 + # define COREB_L1_DATA_A_LENGTH 0x8000 98 + # define COREB_L1_DATA_B_LENGTH 0x8000 76 99 #endif 77 100 78 101 /* Level 2 Memory */
+7 -5
arch/blackfin/mach-common/entry.S
··· 218 218 /* Single stepping only a single instruction, so clear the trace 219 219 * bit here. */ 220 220 r7 = syscfg; 221 - bitclr (r7, 0); 221 + bitclr (r7, SYSCFG_SSSTEP_P); 222 222 syscfg = R7; 223 223 jump _ex_trap_c; 224 224 ··· 251 251 if !cc jump _bfin_return_from_exception; 252 252 253 253 r7 = syscfg; 254 - bitclr (r7, 0); 254 + bitclr (r7, SYSCFG_SSSTEP_P); /* Turn off single step */ 255 255 syscfg = R7; 256 256 257 257 /* Fall through to _bfin_return_from_exception. */ ··· 342 342 r6 = retx; 343 343 [p5 + PDA_RETX] = r6; 344 344 #endif 345 + /* Save the state of single stepping */ 345 346 r6 = SYSCFG; 346 347 [p5 + PDA_SYSCFG] = r6; 347 - BITCLR(r6, 0); 348 + /* Clear it while we handle the exception in IRQ5 mode */ 349 + BITCLR(r6, SYSCFG_SSSTEP_P); 348 350 SYSCFG = r6; 349 351 350 352 /* Disable all interrupts, but make sure level 5 is enabled so ··· 369 367 * exception. This is a unrecoverable event, so crash. 370 368 * Note: this cannot be ENTRY() as we jump here with "if cc jump" ... 371 369 */ 372 - _double_fault: 370 + ENTRY(_double_fault) 373 371 /* Turn caches & protection off, to ensure we don't get any more 374 372 * double exceptions 375 373 */ ··· 874 872 raise 15; /* raise evt15 to do signal or reschedule */ 875 873 4: 876 874 r0 = syscfg; 877 - bitclr(r0, 0); 875 + bitclr(r0, SYSCFG_SSSTEP_P); /* Turn off single step */ 878 876 syscfg = r0; 879 877 5: 880 878 rts;
+9 -1
arch/blackfin/mach-common/smp.c
··· 211 211 return 0; 212 212 213 213 msg = kmalloc(sizeof(*msg), GFP_ATOMIC); 214 + if (!msg) 215 + return -ENOMEM; 214 216 INIT_LIST_HEAD(&msg->list); 215 217 msg->call_struct.func = func; 216 218 msg->call_struct.info = info; ··· 254 252 cpu_set(cpu, callmap); 255 253 256 254 msg = kmalloc(sizeof(*msg), GFP_ATOMIC); 255 + if (!msg) 256 + return -ENOMEM; 257 257 INIT_LIST_HEAD(&msg->list); 258 258 msg->call_struct.func = func; 259 259 msg->call_struct.info = info; ··· 291 287 return; 292 288 293 289 msg = kmalloc(sizeof(*msg), GFP_ATOMIC); 290 + if (!msg) 291 + return; 294 292 memset(msg, 0, sizeof(msg)); 295 293 INIT_LIST_HEAD(&msg->list); 296 294 msg->type = BFIN_IPI_RESCHEDULE; ··· 320 314 return; 321 315 322 316 msg = kmalloc(sizeof(*msg), GFP_ATOMIC); 317 + if (!msg) 318 + return; 323 319 memset(msg, 0, sizeof(msg)); 324 320 INIT_LIST_HEAD(&msg->list); 325 321 msg->type = BFIN_IPI_CPU_STOP; ··· 458 450 unsigned int cpu; 459 451 460 452 for_each_online_cpu(cpu) 461 - bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy; 453 + bogosum += loops_per_jiffy; 462 454 463 455 printk(KERN_INFO "SMP: Total of %d processors activated " 464 456 "(%lu.%02lu BogoMIPS).\n",