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kernel
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linux
[POWERPC] Import spu disassembly code into xmon
This patch imports and munges the spu disassembly code from binutils.
All files originated from version 1.1 in binutils cvs.
* spu.h, spu-insns.h and spu-opc.c are unchanged except for pathnames.
* spu-dis.c has been edited heavily:
* use printf instead of info->fprintf_func and similar.
* pass the instruction in rather than reading it.
* we have no equivalent to symbol_at_address_func, so we just assume
there is never a symbol at the address given.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
authored by
Michael Ellerman
and committed by
Paul Mackerras
ae06e374
4c4c8723
+829
+249
arch/powerpc/xmon/spu-dis.c
+249
arch/powerpc/xmon/spu-dis.c
···
1
+
/* Disassemble SPU instructions
2
+
3
+
Copyright 2006 Free Software Foundation, Inc.
4
+
5
+
This file is part of GDB, GAS, and the GNU binutils.
6
+
7
+
This program is free software; you can redistribute it and/or modify
8
+
it under the terms of the GNU General Public License as published by
9
+
the Free Software Foundation; either version 2 of the License, or
10
+
(at your option) any later version.
11
+
12
+
This program is distributed in the hope that it will be useful,
13
+
but WITHOUT ANY WARRANTY; without even the implied warranty of
14
+
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15
+
GNU General Public License for more details.
16
+
17
+
You should have received a copy of the GNU General Public License along
18
+
with this program; if not, write to the Free Software Foundation, Inc.,
19
+
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
20
+
21
+
#include <linux/string.h>
22
+
#include "nonstdio.h"
23
+
#include "ansidecl.h"
24
+
#include "spu.h"
25
+
26
+
extern void print_address (unsigned long memaddr);
27
+
28
+
/* This file provides a disassembler function which uses
29
+
the disassembler interface defined in dis-asm.h. */
30
+
31
+
extern const struct spu_opcode spu_opcodes[];
32
+
extern const int spu_num_opcodes;
33
+
34
+
#define SPU_DISASM_TBL_SIZE (1 << 11)
35
+
static const struct spu_opcode *spu_disassemble_table[SPU_DISASM_TBL_SIZE];
36
+
37
+
static void
38
+
init_spu_disassemble (void)
39
+
{
40
+
int i;
41
+
42
+
/* If two instructions have the same opcode then we prefer the first
43
+
* one. In most cases it is just an alternate mnemonic. */
44
+
for (i = 0; i < spu_num_opcodes; i++)
45
+
{
46
+
int o = spu_opcodes[i].opcode;
47
+
if (o >= SPU_DISASM_TBL_SIZE)
48
+
continue; /* abort (); */
49
+
if (spu_disassemble_table[o] == 0)
50
+
spu_disassemble_table[o] = &spu_opcodes[i];
51
+
}
52
+
}
53
+
54
+
/* Determine the instruction from the 10 least significant bits. */
55
+
static const struct spu_opcode *
56
+
get_index_for_opcode (unsigned int insn)
57
+
{
58
+
const struct spu_opcode *index;
59
+
unsigned int opcode = insn >> (32-11);
60
+
61
+
/* Init the table. This assumes that element 0/opcode 0 (currently
62
+
* NOP) is always used */
63
+
if (spu_disassemble_table[0] == 0)
64
+
init_spu_disassemble ();
65
+
66
+
if ((index = spu_disassemble_table[opcode & 0x780]) != 0
67
+
&& index->insn_type == RRR)
68
+
return index;
69
+
70
+
if ((index = spu_disassemble_table[opcode & 0x7f0]) != 0
71
+
&& (index->insn_type == RI18 || index->insn_type == LBT))
72
+
return index;
73
+
74
+
if ((index = spu_disassemble_table[opcode & 0x7f8]) != 0
75
+
&& index->insn_type == RI10)
76
+
return index;
77
+
78
+
if ((index = spu_disassemble_table[opcode & 0x7fc]) != 0
79
+
&& (index->insn_type == RI16))
80
+
return index;
81
+
82
+
if ((index = spu_disassemble_table[opcode & 0x7fe]) != 0
83
+
&& (index->insn_type == RI8))
84
+
return index;
85
+
86
+
if ((index = spu_disassemble_table[opcode & 0x7ff]) != 0)
87
+
return index;
88
+
89
+
return 0;
90
+
}
91
+
92
+
/* Print a Spu instruction. */
93
+
94
+
int
95
+
print_insn_spu (unsigned long insn, unsigned long memaddr)
96
+
{
97
+
int value;
98
+
int hex_value;
99
+
const struct spu_opcode *index;
100
+
enum spu_insns tag;
101
+
102
+
index = get_index_for_opcode (insn);
103
+
104
+
if (index == 0)
105
+
{
106
+
printf(".long 0x%x", insn);
107
+
}
108
+
else
109
+
{
110
+
int i;
111
+
int paren = 0;
112
+
tag = (enum spu_insns)(index - spu_opcodes);
113
+
printf("%s", index->mnemonic);
114
+
if (tag == M_BI || tag == M_BISL || tag == M_IRET || tag == M_BISLED
115
+
|| tag == M_BIHNZ || tag == M_BIHZ || tag == M_BINZ || tag == M_BIZ
116
+
|| tag == M_SYNC || tag == M_HBR)
117
+
{
118
+
int fb = (insn >> (32-18)) & 0x7f;
119
+
if (fb & 0x40)
120
+
printf(tag == M_SYNC ? "c" : "p");
121
+
if (fb & 0x20)
122
+
printf("d");
123
+
if (fb & 0x10)
124
+
printf("e");
125
+
}
126
+
if (index->arg[0] != 0)
127
+
printf("\t");
128
+
hex_value = 0;
129
+
for (i = 1; i <= index->arg[0]; i++)
130
+
{
131
+
int arg = index->arg[i];
132
+
if (arg != A_P && !paren && i > 1)
133
+
printf(",");
134
+
135
+
switch (arg)
136
+
{
137
+
case A_T:
138
+
printf("$%d",
139
+
DECODE_INSN_RT (insn));
140
+
break;
141
+
case A_A:
142
+
printf("$%d",
143
+
DECODE_INSN_RA (insn));
144
+
break;
145
+
case A_B:
146
+
printf("$%d",
147
+
DECODE_INSN_RB (insn));
148
+
break;
149
+
case A_C:
150
+
printf("$%d",
151
+
DECODE_INSN_RC (insn));
152
+
break;
153
+
case A_S:
154
+
printf("$sp%d",
155
+
DECODE_INSN_RA (insn));
156
+
break;
157
+
case A_H:
158
+
printf("$ch%d",
159
+
DECODE_INSN_RA (insn));
160
+
break;
161
+
case A_P:
162
+
paren++;
163
+
printf("(");
164
+
break;
165
+
case A_U7A:
166
+
printf("%d",
167
+
173 - DECODE_INSN_U8 (insn));
168
+
break;
169
+
case A_U7B:
170
+
printf("%d",
171
+
155 - DECODE_INSN_U8 (insn));
172
+
break;
173
+
case A_S3:
174
+
case A_S6:
175
+
case A_S7:
176
+
case A_S7N:
177
+
case A_U3:
178
+
case A_U5:
179
+
case A_U6:
180
+
case A_U7:
181
+
hex_value = DECODE_INSN_I7 (insn);
182
+
printf("%d", hex_value);
183
+
break;
184
+
case A_S11:
185
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print_address(memaddr + DECODE_INSN_I9a (insn) * 4);
186
+
break;
187
+
case A_S11I:
188
+
print_address(memaddr + DECODE_INSN_I9b (insn) * 4);
189
+
break;
190
+
case A_S10:
191
+
case A_S10B:
192
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hex_value = DECODE_INSN_I10 (insn);
193
+
printf("%d", hex_value);
194
+
break;
195
+
case A_S14:
196
+
hex_value = DECODE_INSN_I10 (insn) * 16;
197
+
printf("%d", hex_value);
198
+
break;
199
+
case A_S16:
200
+
hex_value = DECODE_INSN_I16 (insn);
201
+
printf("%d", hex_value);
202
+
break;
203
+
case A_X16:
204
+
hex_value = DECODE_INSN_U16 (insn);
205
+
printf("%u", hex_value);
206
+
break;
207
+
case A_R18:
208
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value = DECODE_INSN_I16 (insn) * 4;
209
+
if (value == 0)
210
+
printf("%d", value);
211
+
else
212
+
{
213
+
hex_value = memaddr + value;
214
+
print_address(hex_value & 0x3ffff);
215
+
}
216
+
break;
217
+
case A_S18:
218
+
value = DECODE_INSN_U16 (insn) * 4;
219
+
if (value == 0)
220
+
printf("%d", value);
221
+
else
222
+
print_address(value);
223
+
break;
224
+
case A_U18:
225
+
value = DECODE_INSN_U18 (insn);
226
+
if (value == 0 || 1)
227
+
{
228
+
hex_value = value;
229
+
printf("%u", value);
230
+
}
231
+
else
232
+
print_address(value);
233
+
break;
234
+
case A_U14:
235
+
hex_value = DECODE_INSN_U14 (insn);
236
+
printf("%u", hex_value);
237
+
break;
238
+
}
239
+
if (arg != A_P && paren)
240
+
{
241
+
printf(")");
242
+
paren--;
243
+
}
244
+
}
245
+
if (hex_value > 16)
246
+
printf("\t# %x", hex_value);
247
+
}
248
+
return 4;
249
+
}
+410
arch/powerpc/xmon/spu-insns.h
+410
arch/powerpc/xmon/spu-insns.h
···
1
+
/* SPU ELF support for BFD.
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+
3
+
Copyright 2006 Free Software Foundation, Inc.
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+
5
+
This file is part of BFD, the Binary File Descriptor library.
6
+
7
+
This program is free software; you can redistribute it and/or modify
8
+
it under the terms of the GNU General Public License as published by
9
+
the Free Software Foundation; either version 2 of the License, or
10
+
(at your option) any later version.
11
+
12
+
This program is distributed in the hope that it will be useful,
13
+
but WITHOUT ANY WARRANTY; without even the implied warranty of
14
+
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15
+
GNU General Public License for more details.
16
+
17
+
You should have received a copy of the GNU General Public License
18
+
along with this program; if not, write to the Free Software Foundation,
19
+
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
20
+
21
+
/* SPU Opcode Table
22
+
23
+
-=-=-= FORMAT =-=-=-
24
+
25
+
+----+-------+-------+-------+-------+ +------------+-------+-------+-------+
26
+
RRR | op | RC | RB | RA | RT | RI7 | op | I7 | RA | RT |
27
+
+----+-------+-------+-------+-------+ +------------+-------+-------+-------+
28
+
0 3 1 1 2 3 0 1 1 2 3
29
+
0 7 4 1 0 7 4 1
30
+
31
+
+-----------+--------+-------+-------+ +---------+----------+-------+-------+
32
+
RI8 | op | I8 | RA | RT | RI10 | op | I10 | RA | RT |
33
+
+-----------+--------+-------+-------+ +---------+----------+-------+-------+
34
+
0 9 1 2 3 0 7 1 2 3
35
+
7 4 1 7 4 1
36
+
37
+
+----------+-----------------+-------+ +--------+-------------------+-------+
38
+
RI16 | op | I16 | RT | RI18 | op | I18 | RT |
39
+
+----------+-----------------+-------+ +--------+-------------------+-------+
40
+
0 8 2 3 0 6 2 3
41
+
4 1 4 1
42
+
43
+
+------------+-------+-------+-------+ +-------+--+-----------------+-------+
44
+
RR | op | RB | RA | RT | LBT | op |RO| I16 | RO |
45
+
+------------+-------+-------+-------+ +-------+--+-----------------+-------+
46
+
0 1 1 2 3 0 6 8 2 3
47
+
0 7 4 1 4 1
48
+
49
+
+------------+----+--+-------+-------+
50
+
LBTI | op | // |RO| RA | RO |
51
+
+------------+----+--+-------+-------+
52
+
0 1 1 1 2 3
53
+
0 5 7 4 1
54
+
55
+
-=-=-= OPCODE =-=-=-
56
+
57
+
OPCODE field specifies the most significant 11bit of the instruction. Some formats don't have 11bits for opcode field, and in this
58
+
case, bit field other than op are defined as 0s. For example, opcode of fma instruction which is RRR format is defined as 0x700,
59
+
since 0x700 -> 11'b11100000000, this means opcode is 4'b1110, and other 7bits are defined as 7'b0000000.
60
+
61
+
-=-=-= ASM_FORMAT =-=-=-
62
+
63
+
RRR category RI7 category
64
+
ASM_RRR mnemonic RC, RA, RB, RT ASM_RI4 mnemonic RT, RA, I4
65
+
ASM_RI7 mnemonic RT, RA, I7
66
+
67
+
RI8 category RI10 category
68
+
ASM_RUI8 mnemonic RT, RA, UI8 ASM_AI10 mnemonic RA, I10
69
+
ASM_RI10 mnemonic RT, RA, R10
70
+
ASM_RI10IDX mnemonic RT, I10(RA)
71
+
72
+
RI16 category RI18 category
73
+
ASM_I16W mnemonic I16W ASM_RI18 mnemonic RT, I18
74
+
ASM_RI16 mnemonic RT, I16
75
+
ASM_RI16W mnemonic RT, I16W
76
+
77
+
RR category LBT category
78
+
ASM_MFSPR mnemonic RT, SA ASM_LBT mnemonic brinst, brtarg
79
+
ASM_MTSPR mnemonic SA, RT
80
+
ASM_NOOP mnemonic LBTI category
81
+
ASM_RA mnemonic RA ASM_LBTI mnemonic brinst, RA
82
+
ASM_RAB mnemonic RA, RB
83
+
ASM_RDCH mnemonic RT, CA
84
+
ASM_RR mnemonic RT, RA, RB
85
+
ASM_RT mnemonic RT
86
+
ASM_RTA mnemonic RT, RA
87
+
ASM_WRCH mnemonic CA, RT
88
+
89
+
Note that RRR instructions have the names for RC and RT reversed from
90
+
what's in the ISA, in order to put RT in the same position it appears
91
+
for other formats.
92
+
93
+
-=-=-= DEPENDENCY =-=-=-
94
+
95
+
DEPENDENCY filed consists of 5 digits. This represents which register is used as source and which register is used as target.
96
+
The first(most significant) digit is always 0. Then it is followd by RC, RB, RA and RT digits.
97
+
If the digit is 0, this means the corresponding register is not used in the instruction.
98
+
If the digit is 1, this means the corresponding register is used as a source in the instruction.
99
+
If the digit is 2, this means the corresponding register is used as a target in the instruction.
100
+
If the digit is 3, this means the corresponding register is used as both source and target in the instruction.
101
+
For example, fms instruction has 00113 as the DEPENDENCY field. This means RC is not used in this operation, RB and RA are
102
+
used as sources and RT is the target.
103
+
104
+
-=-=-= PIPE =-=-=-
105
+
106
+
This field shows which execution pipe is used for the instruction
107
+
108
+
pipe0 execution pipelines:
109
+
FP6 SP floating pipeline
110
+
FP7 integer operations executed in SP floating pipeline
111
+
FPD DP floating pipeline
112
+
FX2 FXU pipeline
113
+
FX3 Rotate/Shift pipeline
114
+
FXB Byte pipeline
115
+
NOP No pipeline
116
+
117
+
pipe1 execution pipelines:
118
+
BR Branch pipeline
119
+
LNOP No pipeline
120
+
LS Load/Store pipeline
121
+
SHUF Shuffle pipeline
122
+
SPR SPR/CH pipeline
123
+
124
+
*/
125
+
126
+
#define _A0() {0}
127
+
#define _A1(a) {1,a}
128
+
#define _A2(a,b) {2,a,b}
129
+
#define _A3(a,b,c) {3,a,b,c}
130
+
#define _A4(a,b,c,d) {4,a,b,c,d}
131
+
132
+
/* TAG FORMAT OPCODE MNEMONIC ASM_FORMAT DEPENDENCY PIPE COMMENT */
133
+
/* 0[RC][RB][RA][RT] */
134
+
/* 1:src, 2:target */
135
+
136
+
APUOP(M_BR, RI16, 0x190, "br", _A1(A_R18), 00000, BR) /* BRel IP<-IP+I16 */
137
+
APUOP(M_BRSL, RI16, 0x198, "brsl", _A2(A_T,A_R18), 00002, BR) /* BRelSetLink RT,IP<-IP,IP+I16 */
138
+
APUOP(M_BRA, RI16, 0x180, "bra", _A1(A_S18), 00000, BR) /* BRAbs IP<-I16 */
139
+
APUOP(M_BRASL, RI16, 0x188, "brasl", _A2(A_T,A_S18), 00002, BR) /* BRAbsSetLink RT,IP<-IP,I16 */
140
+
APUOP(M_FSMBI, RI16, 0x194, "fsmbi", _A2(A_T,A_X16), 00002, SHUF) /* FormSelMask%I RT<-fsm(I16) */
141
+
APUOP(M_LQA, RI16, 0x184, "lqa", _A2(A_T,A_S18), 00002, LS) /* LoadQAbs RT<-M[I16] */
142
+
APUOP(M_LQR, RI16, 0x19C, "lqr", _A2(A_T,A_R18), 00002, LS) /* LoadQRel RT<-M[IP+I16] */
143
+
APUOP(M_STOP, RR, 0x000, "stop", _A0(), 00000, BR) /* STOP stop */
144
+
APUOP(M_STOP2, RR, 0x000, "stop", _A1(A_U14), 00000, BR) /* STOP stop */
145
+
APUOP(M_STOPD, RR, 0x140, "stopd", _A3(A_T,A_A,A_B), 00111, BR) /* STOPD stop (with register dependencies) */
146
+
APUOP(M_LNOP, RR, 0x001, "lnop", _A0(), 00000, LNOP) /* LNOP no_operation */
147
+
APUOP(M_SYNC, RR, 0x002, "sync", _A0(), 00000, BR) /* SYNC flush_pipe */
148
+
APUOP(M_DSYNC, RR, 0x003, "dsync", _A0(), 00000, BR) /* DSYNC flush_store_queue */
149
+
APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */
150
+
APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */
151
+
APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */
152
+
APUOP(M_HBRA, LBT, 0x080, "hbra", _A2(A_S11,A_S18), 00000, LS) /* HBRA BTB[B9]<-M[I16] */
153
+
APUOP(M_HBRR, LBT, 0x090, "hbrr", _A2(A_S11,A_R18), 00000, LS) /* HBRR BTB[B9]<-M[IP+I16] */
154
+
APUOP(M_BRZ, RI16, 0x100, "brz", _A2(A_T,A_R18), 00001, BR) /* BRZ IP<-IP+I16_if(RT) */
155
+
APUOP(M_BRNZ, RI16, 0x108, "brnz", _A2(A_T,A_R18), 00001, BR) /* BRNZ IP<-IP+I16_if(RT) */
156
+
APUOP(M_BRHZ, RI16, 0x110, "brhz", _A2(A_T,A_R18), 00001, BR) /* BRHZ IP<-IP+I16_if(RT) */
157
+
APUOP(M_BRHNZ, RI16, 0x118, "brhnz", _A2(A_T,A_R18), 00001, BR) /* BRHNZ IP<-IP+I16_if(RT) */
158
+
APUOP(M_STQA, RI16, 0x104, "stqa", _A2(A_T,A_S18), 00001, LS) /* SToreQAbs M[I16]<-RT */
159
+
APUOP(M_STQR, RI16, 0x11C, "stqr", _A2(A_T,A_R18), 00001, LS) /* SToreQRel M[IP+I16]<-RT */
160
+
APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */
161
+
APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */
162
+
APUOP(M_LQD, RI10, 0x1a0, "lqd", _A4(A_T,A_S14,A_P,A_A), 00012, LS) /* LoadQDisp RT<-M[Ra+I10] */
163
+
APUOP(M_BI, RR, 0x1a8, "bi", _A1(A_A), 00010, BR) /* BI IP<-RA */
164
+
APUOP(M_BISL, RR, 0x1a9, "bisl", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */
165
+
APUOP(M_IRET, RR, 0x1aa, "iret", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */
166
+
APUOP(M_IRET2, RR, 0x1aa, "iret", _A0(), 00010, BR) /* IRET IP<-SRR0 */
167
+
APUOP(M_BISLED, RR, 0x1ab, "bisled", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */
168
+
APUOP(M_HBR, LBTI, 0x1ac, "hbr", _A2(A_S11I,A_A), 00010, LS) /* HBR BTB[B9]<-M[Ra] */
169
+
APUOP(M_FREST, RR, 0x1b8, "frest", _A2(A_T,A_A), 00012, SHUF) /* FREST RT<-recip(RA) */
170
+
APUOP(M_FRSQEST, RR, 0x1b9, "frsqest", _A2(A_T,A_A), 00012, SHUF) /* FRSQEST RT<-rsqrt(RA) */
171
+
APUOP(M_FSM, RR, 0x1b4, "fsm", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */
172
+
APUOP(M_FSMH, RR, 0x1b5, "fsmh", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */
173
+
APUOP(M_FSMB, RR, 0x1b6, "fsmb", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */
174
+
APUOP(M_GB, RR, 0x1b0, "gb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */
175
+
APUOP(M_GBH, RR, 0x1b1, "gbh", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */
176
+
APUOP(M_GBB, RR, 0x1b2, "gbb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */
177
+
APUOP(M_CBD, RI7, 0x1f4, "cbd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
178
+
APUOP(M_CHD, RI7, 0x1f5, "chd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
179
+
APUOP(M_CWD, RI7, 0x1f6, "cwd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
180
+
APUOP(M_CDD, RI7, 0x1f7, "cdd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
181
+
APUOP(M_ROTQBII, RI7, 0x1f8, "rotqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* ROTQBII RT<-RA<<<I7 */
182
+
APUOP(M_ROTQBYI, RI7, 0x1fc, "rotqbyi", _A3(A_T,A_A,A_S7N), 00012, SHUF) /* ROTQBYI RT<-RA<<<(I7*8) */
183
+
APUOP(M_ROTQMBII, RI7, 0x1f9, "rotqmbii", _A3(A_T,A_A,A_S3), 00012, SHUF) /* ROTQMBII RT<-RA<<I7 */
184
+
APUOP(M_ROTQMBYI, RI7, 0x1fd, "rotqmbyi", _A3(A_T,A_A,A_S6), 00012, SHUF) /* ROTQMBYI RT<-RA<<I7 */
185
+
APUOP(M_SHLQBII, RI7, 0x1fb, "shlqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* SHLQBII RT<-RA<<I7 */
186
+
APUOP(M_SHLQBYI, RI7, 0x1ff, "shlqbyi", _A3(A_T,A_A,A_U5), 00012, SHUF) /* SHLQBYI RT<-RA<<I7 */
187
+
APUOP(M_STQD, RI10, 0x120, "stqd", _A4(A_T,A_S14,A_P,A_A), 00011, LS) /* SToreQDisp M[Ra+I10]<-RT */
188
+
APUOP(M_BIHNZ, RR, 0x12b, "bihnz", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
189
+
APUOP(M_BIHZ, RR, 0x12a, "bihz", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
190
+
APUOP(M_BINZ, RR, 0x129, "binz", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
191
+
APUOP(M_BIZ, RR, 0x128, "biz", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
192
+
APUOP(M_CBX, RR, 0x1d4, "cbx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
193
+
APUOP(M_CHX, RR, 0x1d5, "chx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
194
+
APUOP(M_CWX, RR, 0x1d6, "cwx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
195
+
APUOP(M_CDX, RR, 0x1d7, "cdx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
196
+
APUOP(M_LQX, RR, 0x1c4, "lqx", _A3(A_T,A_A,A_B), 00112, LS) /* LoadQindeX RT<-M[Ra+Rb] */
197
+
APUOP(M_ROTQBI, RR, 0x1d8, "rotqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBI RT<-RA<<<Rb */
198
+
APUOP(M_ROTQMBI, RR, 0x1d9, "rotqmbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBI RT<-RA<<Rb */
199
+
APUOP(M_SHLQBI, RR, 0x1db, "shlqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBI RT<-RA<<Rb */
200
+
APUOP(M_ROTQBY, RR, 0x1dc, "rotqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBY RT<-RA<<<(Rb*8) */
201
+
APUOP(M_ROTQMBY, RR, 0x1dd, "rotqmby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBY RT<-RA<<Rb */
202
+
APUOP(M_SHLQBY, RR, 0x1df, "shlqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBY RT<-RA<<Rb */
203
+
APUOP(M_ROTQBYBI, RR, 0x1cc, "rotqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBYBI RT<-RA<<Rb */
204
+
APUOP(M_ROTQMBYBI, RR, 0x1cd, "rotqmbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBYBI RT<-RA<<Rb */
205
+
APUOP(M_SHLQBYBI, RR, 0x1cf, "shlqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBYBI RT<-RA<<Rb */
206
+
APUOP(M_STQX, RR, 0x144, "stqx", _A3(A_T,A_A,A_B), 00111, LS) /* SToreQindeX M[Ra+Rb]<-RT */
207
+
APUOP(M_SHUFB, RRR, 0x580, "shufb", _A4(A_C,A_A,A_B,A_T), 02111, SHUF) /* SHUFfleBytes RC<-f(RA,RB,RT) */
208
+
APUOP(M_IL, RI16, 0x204, "il", _A2(A_T,A_S16), 00002, FX2) /* ImmLoad RT<-sxt(I16) */
209
+
APUOP(M_ILH, RI16, 0x20c, "ilh", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadH RT<-I16 */
210
+
APUOP(M_ILHU, RI16, 0x208, "ilhu", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadHUpper RT<-I16<<16 */
211
+
APUOP(M_ILA, RI18, 0x210, "ila", _A2(A_T,A_U18), 00002, FX2) /* ImmLoadAddr RT<-zxt(I18) */
212
+
APUOP(M_NOP, RR, 0x201, "nop", _A1(A_T), 00000, NOP) /* XNOP no_operation */
213
+
APUOP(M_NOP2, RR, 0x201, "nop", _A0(), 00000, NOP) /* XNOP no_operation */
214
+
APUOP(M_IOHL, RI16, 0x304, "iohl", _A2(A_T,A_X16), 00003, FX2) /* AddImmeXt RT<-RT+sxt(I16) */
215
+
APUOP(M_ANDBI, RI10, 0x0b0, "andbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* AND%I RT<-RA&I10 */
216
+
APUOP(M_ANDHI, RI10, 0x0a8, "andhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */
217
+
APUOP(M_ANDI, RI10, 0x0a0, "andi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */
218
+
APUOP(M_ORBI, RI10, 0x030, "orbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* OR%I RT<-RA|I10 */
219
+
APUOP(M_ORHI, RI10, 0x028, "orhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */
220
+
APUOP(M_ORI, RI10, 0x020, "ori", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */
221
+
APUOP(M_ORX, RR, 0x1f0, "orx", _A2(A_T,A_A), 00012, BR) /* ORX RT<-RA.w0|RA.w1|RA.w2|RA.w3 */
222
+
APUOP(M_XORBI, RI10, 0x230, "xorbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* XOR%I RT<-RA^I10 */
223
+
APUOP(M_XORHI, RI10, 0x228, "xorhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */
224
+
APUOP(M_XORI, RI10, 0x220, "xori", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */
225
+
APUOP(M_AHI, RI10, 0x0e8, "ahi", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */
226
+
APUOP(M_AI, RI10, 0x0e0, "ai", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */
227
+
APUOP(M_SFHI, RI10, 0x068, "sfhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */
228
+
APUOP(M_SFI, RI10, 0x060, "sfi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */
229
+
APUOP(M_CGTBI, RI10, 0x270, "cgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CGT%I RT<-(RA>I10) */
230
+
APUOP(M_CGTHI, RI10, 0x268, "cgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */
231
+
APUOP(M_CGTI, RI10, 0x260, "cgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */
232
+
APUOP(M_CLGTBI, RI10, 0x2f0, "clgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CLGT%I RT<-(RA>I10) */
233
+
APUOP(M_CLGTHI, RI10, 0x2e8, "clgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */
234
+
APUOP(M_CLGTI, RI10, 0x2e0, "clgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */
235
+
APUOP(M_CEQBI, RI10, 0x3f0, "ceqbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CEQ%I RT<-(RA=I10) */
236
+
APUOP(M_CEQHI, RI10, 0x3e8, "ceqhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */
237
+
APUOP(M_CEQI, RI10, 0x3e0, "ceqi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */
238
+
APUOP(M_HGTI, RI10, 0x278, "hgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */
239
+
APUOP(M_HGTI2, RI10, 0x278, "hgti", _A2(A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */
240
+
APUOP(M_HLGTI, RI10, 0x2f8, "hlgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */
241
+
APUOP(M_HLGTI2, RI10, 0x2f8, "hlgti", _A2(A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */
242
+
APUOP(M_HEQI, RI10, 0x3f8, "heqi", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */
243
+
APUOP(M_HEQI2, RI10, 0x3f8, "heqi", _A2(A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */
244
+
APUOP(M_MPYI, RI10, 0x3a0, "mpyi", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYI RT<-RA*I10 */
245
+
APUOP(M_MPYUI, RI10, 0x3a8, "mpyui", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYUI RT<-RA*I10 */
246
+
APUOP(M_CFLTS, RI8, 0x3b0, "cflts", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTS RT<-int(RA,I8) */
247
+
APUOP(M_CFLTU, RI8, 0x3b2, "cfltu", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTU RT<-int(RA,I8) */
248
+
APUOP(M_CSFLT, RI8, 0x3b4, "csflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CSFLT RT<-flt(RA,I8) */
249
+
APUOP(M_CUFLT, RI8, 0x3b6, "cuflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CUFLT RT<-flt(RA,I8) */
250
+
APUOP(M_FESD, RR, 0x3b8, "fesd", _A2(A_T,A_A), 00012, FPD) /* FESD RT<-double(RA) */
251
+
APUOP(M_FRDS, RR, 0x3b9, "frds", _A2(A_T,A_A), 00012, FPD) /* FRDS RT<-single(RA) */
252
+
APUOP(M_FSCRRD, RR, 0x398, "fscrrd", _A1(A_T), 00002, FPD) /* FSCRRD RT<-FP_status */
253
+
APUOP(M_FSCRWR, RR, 0x3ba, "fscrwr", _A2(A_T,A_A), 00010, FP7) /* FSCRWR FP_status<-RA */
254
+
APUOP(M_FSCRWR2, RR, 0x3ba, "fscrwr", _A1(A_A), 00010, FP7) /* FSCRWR FP_status<-RA */
255
+
APUOP(M_CLZ, RR, 0x2a5, "clz", _A2(A_T,A_A), 00012, FX2) /* CLZ RT<-clz(RA) */
256
+
APUOP(M_CNTB, RR, 0x2b4, "cntb", _A2(A_T,A_A), 00012, FXB) /* CNT RT<-pop(RA) */
257
+
APUOP(M_XSBH, RR, 0x2b6, "xsbh", _A2(A_T,A_A), 00012, FX2) /* eXtSignBtoH RT<-sign_ext(RA) */
258
+
APUOP(M_XSHW, RR, 0x2ae, "xshw", _A2(A_T,A_A), 00012, FX2) /* eXtSignHtoW RT<-sign_ext(RA) */
259
+
APUOP(M_XSWD, RR, 0x2a6, "xswd", _A2(A_T,A_A), 00012, FX2) /* eXtSignWtoD RT<-sign_ext(RA) */
260
+
APUOP(M_ROTI, RI7, 0x078, "roti", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */
261
+
APUOP(M_ROTMI, RI7, 0x079, "rotmi", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROT%MI RT<-RA<<I7 */
262
+
APUOP(M_ROTMAI, RI7, 0x07a, "rotmai", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */
263
+
APUOP(M_SHLI, RI7, 0x07b, "shli", _A3(A_T,A_A,A_U6), 00012, FX3) /* SHL%I RT<-RA<<I7 */
264
+
APUOP(M_ROTHI, RI7, 0x07c, "rothi", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */
265
+
APUOP(M_ROTHMI, RI7, 0x07d, "rothmi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROT%MI RT<-RA<<I7 */
266
+
APUOP(M_ROTMAHI, RI7, 0x07e, "rotmahi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */
267
+
APUOP(M_SHLHI, RI7, 0x07f, "shlhi", _A3(A_T,A_A,A_U5), 00012, FX3) /* SHL%I RT<-RA<<I7 */
268
+
APUOP(M_A, RR, 0x0c0, "a", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */
269
+
APUOP(M_AH, RR, 0x0c8, "ah", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */
270
+
APUOP(M_SF, RR, 0x040, "sf", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */
271
+
APUOP(M_SFH, RR, 0x048, "sfh", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */
272
+
APUOP(M_CGT, RR, 0x240, "cgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */
273
+
APUOP(M_CGTB, RR, 0x250, "cgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */
274
+
APUOP(M_CGTH, RR, 0x248, "cgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */
275
+
APUOP(M_CLGT, RR, 0x2c0, "clgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */
276
+
APUOP(M_CLGTB, RR, 0x2d0, "clgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */
277
+
APUOP(M_CLGTH, RR, 0x2c8, "clgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */
278
+
APUOP(M_CEQ, RR, 0x3c0, "ceq", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */
279
+
APUOP(M_CEQB, RR, 0x3d0, "ceqb", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */
280
+
APUOP(M_CEQH, RR, 0x3c8, "ceqh", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */
281
+
APUOP(M_HGT, RR, 0x258, "hgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */
282
+
APUOP(M_HGT2, RR, 0x258, "hgt", _A2(A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */
283
+
APUOP(M_HLGT, RR, 0x2d8, "hlgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */
284
+
APUOP(M_HLGT2, RR, 0x2d8, "hlgt", _A2(A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */
285
+
APUOP(M_HEQ, RR, 0x3d8, "heq", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */
286
+
APUOP(M_HEQ2, RR, 0x3d8, "heq", _A2(A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */
287
+
APUOP(M_FCEQ, RR, 0x3c2, "fceq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCEQ RT<-(RA=RB) */
288
+
APUOP(M_FCMEQ, RR, 0x3ca, "fcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMEQ RT<-(|RA|=|RB|) */
289
+
APUOP(M_FCGT, RR, 0x2c2, "fcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCGT RT<-(RA<RB) */
290
+
APUOP(M_FCMGT, RR, 0x2ca, "fcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMGT RT<-(|RA|<|RB|) */
291
+
APUOP(M_AND, RR, 0x0c1, "and", _A3(A_T,A_A,A_B), 00112, FX2) /* AND RT<-RA&RB */
292
+
APUOP(M_NAND, RR, 0x0c9, "nand", _A3(A_T,A_A,A_B), 00112, FX2) /* NAND RT<-!(RA&RB) */
293
+
APUOP(M_OR, RR, 0x041, "or", _A3(A_T,A_A,A_B), 00112, FX2) /* OR RT<-RA|RB */
294
+
APUOP(M_NOR, RR, 0x049, "nor", _A3(A_T,A_A,A_B), 00112, FX2) /* NOR RT<-!(RA&RB) */
295
+
APUOP(M_XOR, RR, 0x241, "xor", _A3(A_T,A_A,A_B), 00112, FX2) /* XOR RT<-RA^RB */
296
+
APUOP(M_EQV, RR, 0x249, "eqv", _A3(A_T,A_A,A_B), 00112, FX2) /* EQuiValent RT<-!(RA^RB) */
297
+
APUOP(M_ANDC, RR, 0x2c1, "andc", _A3(A_T,A_A,A_B), 00112, FX2) /* ANDComplement RT<-RA&!RB */
298
+
APUOP(M_ORC, RR, 0x2c9, "orc", _A3(A_T,A_A,A_B), 00112, FX2) /* ORComplement RT<-RA|!RB */
299
+
APUOP(M_ABSDB, RR, 0x053, "absdb", _A3(A_T,A_A,A_B), 00112, FXB) /* ABSoluteDiff RT<-|RA-RB| */
300
+
APUOP(M_AVGB, RR, 0x0d3, "avgb", _A3(A_T,A_A,A_B), 00112, FXB) /* AVG% RT<-(RA+RB+1)/2 */
301
+
APUOP(M_SUMB, RR, 0x253, "sumb", _A3(A_T,A_A,A_B), 00112, FXB) /* SUM% RT<-f(RA,RB) */
302
+
APUOP(M_DFA, RR, 0x2cc, "dfa", _A3(A_T,A_A,A_B), 00112, FPD) /* DFAdd RT<-RA+RB */
303
+
APUOP(M_DFM, RR, 0x2ce, "dfm", _A3(A_T,A_A,A_B), 00112, FPD) /* DFMul RT<-RA*RB */
304
+
APUOP(M_DFS, RR, 0x2cd, "dfs", _A3(A_T,A_A,A_B), 00112, FPD) /* DFSub RT<-RA-RB */
305
+
APUOP(M_FA, RR, 0x2c4, "fa", _A3(A_T,A_A,A_B), 00112, FP6) /* FAdd RT<-RA+RB */
306
+
APUOP(M_FM, RR, 0x2c6, "fm", _A3(A_T,A_A,A_B), 00112, FP6) /* FMul RT<-RA*RB */
307
+
APUOP(M_FS, RR, 0x2c5, "fs", _A3(A_T,A_A,A_B), 00112, FP6) /* FSub RT<-RA-RB */
308
+
APUOP(M_MPY, RR, 0x3c4, "mpy", _A3(A_T,A_A,A_B), 00112, FP7) /* MPY RT<-RA*RB */
309
+
APUOP(M_MPYH, RR, 0x3c5, "mpyh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYH RT<-(RAh*RB)<<16 */
310
+
APUOP(M_MPYHH, RR, 0x3c6, "mpyhh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHH RT<-RAh*RBh */
311
+
APUOP(M_MPYHHU, RR, 0x3ce, "mpyhhu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHHU RT<-RAh*RBh */
312
+
APUOP(M_MPYS, RR, 0x3c7, "mpys", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYS RT<-(RA*RB)>>16 */
313
+
APUOP(M_MPYU, RR, 0x3cc, "mpyu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYU RT<-RA*RB */
314
+
APUOP(M_FI, RR, 0x3d4, "fi", _A3(A_T,A_A,A_B), 00112, FP7) /* FInterpolate RT<-f(RA,RB) */
315
+
APUOP(M_ROT, RR, 0x058, "rot", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */
316
+
APUOP(M_ROTM, RR, 0x059, "rotm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */
317
+
APUOP(M_ROTMA, RR, 0x05a, "rotma", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */
318
+
APUOP(M_SHL, RR, 0x05b, "shl", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */
319
+
APUOP(M_ROTH, RR, 0x05c, "roth", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */
320
+
APUOP(M_ROTHM, RR, 0x05d, "rothm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */
321
+
APUOP(M_ROTMAH, RR, 0x05e, "rotmah", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */
322
+
APUOP(M_SHLH, RR, 0x05f, "shlh", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */
323
+
APUOP(M_MPYHHA, RR, 0x346, "mpyhha", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHA RT<-RAh*RBh+RT */
324
+
APUOP(M_MPYHHAU, RR, 0x34e, "mpyhhau", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHAU RT<-RAh*RBh+RT */
325
+
APUOP(M_DFMA, RR, 0x35c, "dfma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMAdd RT<-RT+RA*RB */
326
+
APUOP(M_DFMS, RR, 0x35d, "dfms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMSub RT<-RA*RB-RT */
327
+
APUOP(M_DFNMS, RR, 0x35e, "dfnms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMSub RT<-RT-RA*RB */
328
+
APUOP(M_DFNMA, RR, 0x35f, "dfnma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMAdd RT<-(-RT)-RA*RB */
329
+
APUOP(M_FMA, RRR, 0x700, "fma", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMAdd RC<-RT+RA*RB */
330
+
APUOP(M_FMS, RRR, 0x780, "fms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMSub RC<-RA*RB-RT */
331
+
APUOP(M_FNMS, RRR, 0x680, "fnms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FNMSub RC<-RT-RA*RB */
332
+
APUOP(M_MPYA, RRR, 0x600, "mpya", _A4(A_C,A_A,A_B,A_T), 02111, FP7) /* MPYA RC<-RA*RB+RT */
333
+
APUOP(M_SELB, RRR, 0x400, "selb", _A4(A_C,A_A,A_B,A_T), 02111, FX2) /* SELectBits RC<-RA&RT|RB&!RT */
334
+
/* for system function call, this uses op-code of mtspr */
335
+
APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Call */
336
+
/*
337
+
pseudo instruction:
338
+
system call
339
+
value of I9 operation
340
+
0 halt
341
+
1 rt[0] = open(MEM[ra[0]], ra[1])
342
+
2 rt[0] = close(ra[0])
343
+
3 rt[0] = read(ra[0], MEM[ra[1]], ra[2])
344
+
4 rt[0] = write(ra[0], MEM[ra[1]], ra[2])
345
+
5 printf(MEM[ra[0]], ra[1], ra[2], ra[3])
346
+
42 rt[0] = clock()
347
+
52 rt[0] = lseek(ra0, ra1, ra2)
348
+
349
+
*/
350
+
351
+
352
+
/* new multiprecision add/sub */
353
+
APUOP(M_ADDX, RR, 0x340, "addx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */
354
+
APUOP(M_CG, RR, 0x0c2, "cg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */
355
+
APUOP(M_CGX, RR, 0x342, "cgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */
356
+
APUOP(M_SFX, RR, 0x341, "sfx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */
357
+
APUOP(M_BG, RR, 0x042, "bg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */
358
+
APUOP(M_BGX, RR, 0x343, "bgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */
359
+
360
+
/*
361
+
362
+
The following ops are a subset of above except with feature bits set.
363
+
Feature bits are bits 11-17 of the instruction:
364
+
365
+
11 - C & P feature bit
366
+
12 - disable interrupts
367
+
13 - enable interrupts
368
+
369
+
*/
370
+
APUOPFB(M_BID, RR, 0x1a8, 0x20, "bid", _A1(A_A), 00010, BR) /* BI IP<-RA */
371
+
APUOPFB(M_BIE, RR, 0x1a8, 0x10, "bie", _A1(A_A), 00010, BR) /* BI IP<-RA */
372
+
APUOPFB(M_BISLD, RR, 0x1a9, 0x20, "bisld", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */
373
+
APUOPFB(M_BISLE, RR, 0x1a9, 0x10, "bisle", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */
374
+
APUOPFB(M_IRETD, RR, 0x1aa, 0x20, "iretd", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */
375
+
APUOPFB(M_IRETD2, RR, 0x1aa, 0x20, "iretd", _A0(), 00010, BR) /* IRET IP<-SRR0 */
376
+
APUOPFB(M_IRETE, RR, 0x1aa, 0x10, "irete", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */
377
+
APUOPFB(M_IRETE2, RR, 0x1aa, 0x10, "irete", _A0(), 00010, BR) /* IRET IP<-SRR0 */
378
+
APUOPFB(M_BISLEDD, RR, 0x1ab, 0x20, "bisledd", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */
379
+
APUOPFB(M_BISLEDE, RR, 0x1ab, 0x10, "bislede", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */
380
+
APUOPFB(M_BIHNZD, RR, 0x12b, 0x20, "bihnzd", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
381
+
APUOPFB(M_BIHNZE, RR, 0x12b, 0x10, "bihnze", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
382
+
APUOPFB(M_BIHZD, RR, 0x12a, 0x20, "bihzd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
383
+
APUOPFB(M_BIHZE, RR, 0x12a, 0x10, "bihze", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
384
+
APUOPFB(M_BINZD, RR, 0x129, 0x20, "binzd", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
385
+
APUOPFB(M_BINZE, RR, 0x129, 0x10, "binze", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
386
+
APUOPFB(M_BIZD, RR, 0x128, 0x20, "bizd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
387
+
APUOPFB(M_BIZE, RR, 0x128, 0x10, "bize", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
388
+
APUOPFB(M_SYNCC, RR, 0x002, 0x40, "syncc", _A0(), 00000, BR) /* SYNCC flush_pipe */
389
+
APUOPFB(M_HBRP, LBTI, 0x1ac, 0x40, "hbrp", _A0(), 00010, LS) /* HBR BTB[B9]<-M[Ra] */
390
+
391
+
/* Synonyms required by the AS manual. */
392
+
APUOP(M_LR, RI10, 0x020, "lr", _A2(A_T,A_A), 00012, FX2) /* OR%I RT<-RA|I10 */
393
+
APUOP(M_BIHT, RR, 0x12b, "biht", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
394
+
APUOP(M_BIHF, RR, 0x12a, "bihf", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
395
+
APUOP(M_BIT, RR, 0x129, "bit", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
396
+
APUOP(M_BIF, RR, 0x128, "bif", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
397
+
APUOPFB(M_BIHTD, RR, 0x12b, 0x20, "bihtd", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */
398
+
APUOPFB(M_BIHTE, RR, 0x12b, 0x10, "bihte", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */
399
+
APUOPFB(M_BIHFD, RR, 0x12a, 0x20, "bihfd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
400
+
APUOPFB(M_BIHFE, RR, 0x12a, 0x10, "bihfe", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
401
+
APUOPFB(M_BITD, RR, 0x129, 0x20, "bitd", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */
402
+
APUOPFB(M_BITE, RR, 0x129, 0x10, "bite", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */
403
+
APUOPFB(M_BIFD, RR, 0x128, 0x20, "bifd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
404
+
APUOPFB(M_BIFE, RR, 0x128, 0x10, "bife", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
405
+
406
+
#undef _A0
407
+
#undef _A1
408
+
#undef _A2
409
+
#undef _A3
410
+
#undef _A4
+44
arch/powerpc/xmon/spu-opc.c
+44
arch/powerpc/xmon/spu-opc.c
···
1
+
/* SPU opcode list
2
+
3
+
Copyright 2006 Free Software Foundation, Inc.
4
+
5
+
This file is part of GDB, GAS, and the GNU binutils.
6
+
7
+
This program is free software; you can redistribute it and/or modify
8
+
it under the terms of the GNU General Public License as published by
9
+
the Free Software Foundation; either version 2 of the License, or
10
+
(at your option) any later version.
11
+
12
+
This program is distributed in the hope that it will be useful,
13
+
but WITHOUT ANY WARRANTY; without even the implied warranty of
14
+
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15
+
GNU General Public License for more details.
16
+
17
+
You should have received a copy of the GNU General Public License along
18
+
with this program; if not, write to the Free Software Foundation, Inc.,
19
+
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
20
+
21
+
#include "spu.h"
22
+
23
+
/* This file holds the Spu opcode table */
24
+
25
+
26
+
/*
27
+
Example contents of spu-insn.h
28
+
id_tag mode mode type opcode mnemonic asmtype dependency FPU L/S? branch? instruction
29
+
QUAD WORD (0,RC,RB,RA,RT) latency
30
+
APUOP(M_LQD, 1, 0, RI9, 0x1f8, "lqd", ASM_RI9IDX, 00012, FXU, 1, 0) Load Quadword d-form
31
+
*/
32
+
33
+
const struct spu_opcode spu_opcodes[] = {
34
+
#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
35
+
{ MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
36
+
#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
37
+
{ MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
38
+
#include "spu-insns.h"
39
+
#undef APUOP
40
+
#undef APUOPFB
41
+
};
42
+
43
+
const int spu_num_opcodes =
44
+
sizeof (spu_opcodes) / sizeof (spu_opcodes[0]);
+126
arch/powerpc/xmon/spu.h
+126
arch/powerpc/xmon/spu.h
···
1
+
/* SPU ELF support for BFD.
2
+
3
+
Copyright 2006 Free Software Foundation, Inc.
4
+
5
+
This file is part of GDB, GAS, and the GNU binutils.
6
+
7
+
This program is free software; you can redistribute it and/or modify
8
+
it under the terms of the GNU General Public License as published by
9
+
the Free Software Foundation; either version 2 of the License, or
10
+
(at your option) any later version.
11
+
12
+
This program is distributed in the hope that it will be useful,
13
+
but WITHOUT ANY WARRANTY; without even the implied warranty of
14
+
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15
+
GNU General Public License for more details.
16
+
17
+
You should have received a copy of the GNU General Public License
18
+
along with this program; if not, write to the Free Software Foundation,
19
+
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
20
+
21
+
22
+
/* These two enums are from rel_apu/common/spu_asm_format.h */
23
+
/* definition of instruction format */
24
+
typedef enum {
25
+
RRR,
26
+
RI18,
27
+
RI16,
28
+
RI10,
29
+
RI8,
30
+
RI7,
31
+
RR,
32
+
LBT,
33
+
LBTI,
34
+
IDATA,
35
+
UNKNOWN_IFORMAT
36
+
} spu_iformat;
37
+
38
+
/* These values describe assembly instruction arguments. They indicate
39
+
* how to encode, range checking and which relocation to use. */
40
+
typedef enum {
41
+
A_T, /* register at pos 0 */
42
+
A_A, /* register at pos 7 */
43
+
A_B, /* register at pos 14 */
44
+
A_C, /* register at pos 21 */
45
+
A_S, /* special purpose register at pos 7 */
46
+
A_H, /* channel register at pos 7 */
47
+
A_P, /* parenthesis, this has to separate regs from immediates */
48
+
A_S3,
49
+
A_S6,
50
+
A_S7N,
51
+
A_S7,
52
+
A_U7A,
53
+
A_U7B,
54
+
A_S10B,
55
+
A_S10,
56
+
A_S11,
57
+
A_S11I,
58
+
A_S14,
59
+
A_S16,
60
+
A_S18,
61
+
A_R18,
62
+
A_U3,
63
+
A_U5,
64
+
A_U6,
65
+
A_U7,
66
+
A_U14,
67
+
A_X16,
68
+
A_U18,
69
+
A_MAX
70
+
} spu_aformat;
71
+
72
+
enum spu_insns {
73
+
#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
74
+
TAG,
75
+
#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
76
+
TAG,
77
+
#include "spu-insns.h"
78
+
#undef APUOP
79
+
#undef APUOPFB
80
+
M_SPU_MAX
81
+
};
82
+
83
+
struct spu_opcode
84
+
{
85
+
spu_iformat insn_type;
86
+
unsigned int opcode;
87
+
char *mnemonic;
88
+
int arg[5];
89
+
};
90
+
91
+
#define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size))
92
+
#define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1))
93
+
94
+
#define DECODE_INSN_RT(insn) (insn & 0x7f)
95
+
#define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f)
96
+
#define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f)
97
+
#define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f)
98
+
99
+
#define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14)
100
+
#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14)
101
+
102
+
/* For branching, immediate loads, hbr and lqa/stqa. */
103
+
#define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7)
104
+
#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7)
105
+
106
+
/* for stop */
107
+
#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0)
108
+
109
+
/* For ila */
110
+
#define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7)
111
+
#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7)
112
+
113
+
/* For rotate and shift and generate control mask */
114
+
#define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14)
115
+
#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14)
116
+
117
+
/* For float <-> int conversion */
118
+
#define DECODE_INSN_I8(insn) SIGNED_EXTRACT(insn,8,14)
119
+
#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14)
120
+
121
+
/* For hbr */
122
+
#define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
123
+
#define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
124
+
#define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
125
+
#define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
126
+