tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amd/pp: Remove cgs_query_system_info

Get gpu info through adev directly in powerplay

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rex Zhu and committed by
Alex Deucher ada6770e 6848d73e

+72 -286
-59
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
··· 835 835 return amdgpu_sriov_vf(adev); 836 836 } 837 837 838 - static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device, 839 - struct cgs_system_info *sys_info) 840 - { 841 - CGS_FUNC_ADEV; 842 - 843 - if (NULL == sys_info) 844 - return -ENODEV; 845 - 846 - if (sizeof(struct cgs_system_info) != sys_info->size) 847 - return -ENODEV; 848 - 849 - switch (sys_info->info_id) { 850 - case CGS_SYSTEM_INFO_ADAPTER_BDF_ID: 851 - sys_info->value = adev->pdev->devfn | (adev->pdev->bus->number << 8); 852 - break; 853 - case CGS_SYSTEM_INFO_PCIE_GEN_INFO: 854 - sys_info->value = adev->pm.pcie_gen_mask; 855 - break; 856 - case CGS_SYSTEM_INFO_PCIE_MLW: 857 - sys_info->value = adev->pm.pcie_mlw_mask; 858 - break; 859 - case CGS_SYSTEM_INFO_PCIE_DEV: 860 - sys_info->value = adev->pdev->device; 861 - break; 862 - case CGS_SYSTEM_INFO_PCIE_REV: 863 - sys_info->value = adev->pdev->revision; 864 - break; 865 - case CGS_SYSTEM_INFO_CG_FLAGS: 866 - sys_info->value = adev->cg_flags; 867 - break; 868 - case CGS_SYSTEM_INFO_PG_FLAGS: 869 - sys_info->value = adev->pg_flags; 870 - break; 871 - case CGS_SYSTEM_INFO_GFX_CU_INFO: 872 - sys_info->value = adev->gfx.cu_info.number; 873 - break; 874 - case CGS_SYSTEM_INFO_GFX_SE_INFO: 875 - sys_info->value = adev->gfx.config.max_shader_engines; 876 - break; 877 - case CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID: 878 - sys_info->value = adev->pdev->subsystem_device; 879 - break; 880 - case CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID: 881 - sys_info->value = adev->pdev->subsystem_vendor; 882 - break; 883 - case CGS_SYSTEM_INFO_PCIE_BUS_DEVFN: 884 - sys_info->value = adev->pdev->devfn; 885 - break; 886 - case CGS_SYSTEM_INFO_VRAM_WIDTH: 887 - sys_info->value = adev->gmc.vram_width; 888 - break; 889 - default: 890 - return -ENODEV; 891 - } 892 - 893 - return 0; 894 - } 895 - 896 838 static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, 897 839 struct cgs_display_info *info) 898 840 { ··· 938 996 .set_clockgating_state = amdgpu_cgs_set_clockgating_state, 939 997 .get_active_displays_info = amdgpu_cgs_get_active_displays_info, 940 998 .notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled, 941 - .query_system_info = amdgpu_cgs_query_system_info, 942 999 .is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled, 943 1000 .enter_safe_mode = amdgpu_cgs_enter_safe_mode, 944 1001 .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
-34
drivers/gpu/drm/amd/include/cgs_common.h
··· 88 88 CGS_UCODE_ID_MAXIMUM, 89 89 }; 90 90 91 - enum cgs_system_info_id { 92 - CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1, 93 - CGS_SYSTEM_INFO_PCIE_GEN_INFO, 94 - CGS_SYSTEM_INFO_PCIE_MLW, 95 - CGS_SYSTEM_INFO_PCIE_DEV, 96 - CGS_SYSTEM_INFO_PCIE_REV, 97 - CGS_SYSTEM_INFO_CG_FLAGS, 98 - CGS_SYSTEM_INFO_PG_FLAGS, 99 - CGS_SYSTEM_INFO_GFX_CU_INFO, 100 - CGS_SYSTEM_INFO_GFX_SE_INFO, 101 - CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID, 102 - CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID, 103 - CGS_SYSTEM_INFO_PCIE_BUS_DEVFN, 104 - CGS_SYSTEM_INFO_VRAM_WIDTH, 105 - CGS_SYSTEM_INFO_ID_MAXIMUM, 106 - }; 107 - 108 - struct cgs_system_info { 109 - uint64_t size; 110 - enum cgs_system_info_id info_id; 111 - union { 112 - void *ptr; 113 - uint64_t value; 114 - }; 115 - uint64_t padding[13]; 116 - }; 117 - 118 91 /* 119 92 * enum cgs_resource_type - GPU resource type 120 93 */ ··· 348 375 349 376 typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled); 350 377 351 - typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device, 352 - struct cgs_system_info *sys_info); 353 - 354 378 typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device); 355 379 356 380 typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en); ··· 386 416 cgs_get_active_displays_info get_active_displays_info; 387 417 /* notify dpm enabled */ 388 418 cgs_notify_dpm_enabled notify_dpm_enabled; 389 - /* get system info */ 390 - cgs_query_system_info query_system_info; 391 419 cgs_is_virtualization_enabled_t is_virtualization_enabled; 392 420 cgs_enter_safe_mode enter_safe_mode; 393 421 cgs_lock_grbm_idx lock_grbm_idx; ··· 451 483 #define cgs_get_active_displays_info(dev, info) \ 452 484 CGS_CALL(get_active_displays_info, dev, info) 453 485 454 - #define cgs_query_system_info(dev, sys_info) \ 455 - CGS_CALL(query_system_info, dev, sys_info) 456 486 #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \ 457 487 resource_base) \ 458 488 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
+9 -13
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
··· 173 173 static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) 174 174 { 175 175 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); 176 - struct cgs_system_info sys_info = {0}; 177 - int result; 176 + struct amdgpu_device *adev = hwmgr->adev; 178 177 179 178 cz_hwmgr->gfx_ramp_step = 256*25/100; 180 179 cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */ ··· 233 234 PHM_PlatformCaps_UVDPowerGating); 234 235 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 235 236 PHM_PlatformCaps_VCEPowerGating); 236 - sys_info.size = sizeof(struct cgs_system_info); 237 - sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS; 238 - result = cgs_query_system_info(hwmgr->device, &sys_info); 239 - if (!result) { 240 - if (sys_info.value & AMD_PG_SUPPORT_UVD) 241 - phm_cap_set(hwmgr->platform_descriptor.platformCaps, 242 - PHM_PlatformCaps_UVDPowerGating); 243 - if (sys_info.value & AMD_PG_SUPPORT_VCE) 244 - phm_cap_set(hwmgr->platform_descriptor.platformCaps, 245 - PHM_PlatformCaps_VCEPowerGating); 246 - } 237 + 238 + if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 239 + phm_cap_set(hwmgr->platform_descriptor.platformCaps, 240 + PHM_PlatformCaps_UVDPowerGating); 241 + if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 242 + phm_cap_set(hwmgr->platform_descriptor.platformCaps, 243 + PHM_PlatformCaps_VCEPowerGating); 244 + 247 245 248 246 return 0; 249 247 }
+15 -39
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
··· 64 64 return (uint16_t) ((6200 - (vid * 25)) / VOLTAGE_SCALE); 65 65 } 66 66 67 - static int phm_get_pci_bus_devfn(struct pp_hwmgr *hwmgr, 68 - struct cgs_system_info *sys_info) 69 - { 70 - sys_info->size = sizeof(struct cgs_system_info); 71 - sys_info->info_id = CGS_SYSTEM_INFO_PCIE_BUS_DEVFN; 72 - 73 - return cgs_query_system_info(hwmgr->device, sys_info); 74 - } 75 - 76 67 static int phm_thermal_l2h_irq(void *private_data, 77 68 unsigned src_id, const uint32_t *iv_entry) 78 69 { 79 70 struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data; 80 - struct cgs_system_info sys_info = {0}; 81 - int result; 71 + struct amdgpu_device *adev = hwmgr->adev; 82 72 83 - result = phm_get_pci_bus_devfn(hwmgr, &sys_info); 84 - if (result) 85 - return -EINVAL; 86 - 87 - pr_warn("GPU over temperature range detected on PCIe %lld:%lld.%lld!\n", 88 - PCI_BUS_NUM(sys_info.value), 89 - PCI_SLOT(sys_info.value), 90 - PCI_FUNC(sys_info.value)); 73 + pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n", 74 + PCI_BUS_NUM(adev->pdev->devfn), 75 + PCI_SLOT(adev->pdev->devfn), 76 + PCI_FUNC(adev->pdev->devfn)); 91 77 return 0; 92 78 } 93 79 ··· 81 95 unsigned src_id, const uint32_t *iv_entry) 82 96 { 83 97 struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data; 84 - struct cgs_system_info sys_info = {0}; 85 - int result; 98 + struct amdgpu_device *adev = hwmgr->adev; 86 99 87 - result = phm_get_pci_bus_devfn(hwmgr, &sys_info); 88 - if (result) 89 - return -EINVAL; 90 - 91 - pr_warn("GPU under temperature range detected on PCIe %lld:%lld.%lld!\n", 92 - PCI_BUS_NUM(sys_info.value), 93 - PCI_SLOT(sys_info.value), 94 - PCI_FUNC(sys_info.value)); 100 + pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n", 101 + PCI_BUS_NUM(adev->pdev->devfn), 102 + PCI_SLOT(adev->pdev->devfn), 103 + PCI_FUNC(adev->pdev->devfn)); 95 104 return 0; 96 105 } 97 106 ··· 94 113 unsigned src_id, const uint32_t *iv_entry) 95 114 { 96 115 struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data; 97 - struct cgs_system_info sys_info = {0}; 98 - int result; 116 + struct amdgpu_device *adev = hwmgr->adev; 99 117 100 - result = phm_get_pci_bus_devfn(hwmgr, &sys_info); 101 - if (result) 102 - return -EINVAL; 103 - 104 - pr_warn("GPU Critical Temperature Fault detected on PCIe %lld:%lld.%lld!\n", 105 - PCI_BUS_NUM(sys_info.value), 106 - PCI_SLOT(sys_info.value), 107 - PCI_FUNC(sys_info.value)); 118 + pr_warn("GPU Critical Temperature Fault detected on PCIe %d:%d.%d!\n", 119 + PCI_BUS_NUM(adev->pdev->devfn), 120 + PCI_SLOT(adev->pdev->devfn), 121 + PCI_FUNC(adev->pdev->devfn)); 108 122 return 0; 109 123 } 110 124
+3 -14
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
··· 472 472 */ 473 473 int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable) 474 474 { 475 - struct cgs_system_info sys_info = {0}; 476 - uint32_t active_cus; 477 - int result; 478 - 479 - sys_info.size = sizeof(struct cgs_system_info); 480 - sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO; 481 - 482 - result = cgs_query_system_info(hwmgr->device, &sys_info); 483 - 484 - if (result) 485 - return -EINVAL; 486 - 487 - active_cus = sys_info.value; 475 + struct amdgpu_device *adev = hwmgr->adev; 488 476 489 477 if (enable) 490 478 return smum_send_msg_to_smc_with_parameter(hwmgr, 491 - PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus); 479 + PPSMC_MSG_GFX_CU_PG_ENABLE, 480 + adev->gfx.cu_info.number); 492 481 else 493 482 return smum_send_msg_to_smc(hwmgr, 494 483 PPSMC_MSG_GFX_CU_PG_DISABLE);
+15 -42
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
··· 1468 1468 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1469 1469 struct phm_ppt_v1_information *table_info = 1470 1470 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1471 - struct cgs_system_info sys_info = {0}; 1472 - int result; 1471 + struct amdgpu_device *adev = hwmgr->adev; 1473 1472 1474 1473 data->dll_default_on = false; 1475 1474 data->mclk_dpm0_activity_target = 0xa; ··· 1589 1590 data->pcie_lane_power_saving.max = 0; 1590 1591 data->pcie_lane_power_saving.min = 16; 1591 1592 1592 - sys_info.size = sizeof(struct cgs_system_info); 1593 - sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS; 1594 - result = cgs_query_system_info(hwmgr->device, &sys_info); 1595 - if (!result) { 1596 - if (sys_info.value & AMD_PG_SUPPORT_UVD) 1597 - phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1598 - PHM_PlatformCaps_UVDPowerGating); 1599 - if (sys_info.value & AMD_PG_SUPPORT_VCE) 1600 - phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1601 - PHM_PlatformCaps_VCEPowerGating); 1602 - } 1593 + 1594 + if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 1595 + phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1596 + PHM_PlatformCaps_UVDPowerGating); 1597 + if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 1598 + phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1599 + PHM_PlatformCaps_VCEPowerGating); 1603 1600 } 1604 1601 1605 1602 /** ··· 2030 2035 struct phm_ppt_v1_voltage_lookup_table *lookup_table; 2031 2036 uint32_t i; 2032 2037 uint32_t hw_revision, sub_vendor_id, sub_sys_id; 2033 - struct cgs_system_info sys_info = {0}; 2038 + struct amdgpu_device *adev = hwmgr->adev; 2034 2039 2035 2040 if (table_info != NULL) { 2036 2041 dep_mclk_table = table_info->vdd_dep_on_mclk; ··· 2038 2043 } else 2039 2044 return 0; 2040 2045 2041 - sys_info.size = sizeof(struct cgs_system_info); 2042 - 2043 - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV; 2044 - cgs_query_system_info(hwmgr->device, &sys_info); 2045 - hw_revision = (uint32_t)sys_info.value; 2046 - 2047 - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID; 2048 - cgs_query_system_info(hwmgr->device, &sys_info); 2049 - sub_sys_id = (uint32_t)sys_info.value; 2050 - 2051 - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID; 2052 - cgs_query_system_info(hwmgr->device, &sys_info); 2053 - sub_vendor_id = (uint32_t)sys_info.value; 2046 + hw_revision = adev->pdev->revision; 2047 + sub_sys_id = adev->pdev->subsystem_device; 2048 + sub_vendor_id = adev->pdev->subsystem_vendor; 2054 2049 2055 2050 if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 && 2056 2051 ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) || ··· 2483 2498 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr); 2484 2499 2485 2500 if (0 == result) { 2486 - struct cgs_system_info sys_info = {0}; 2501 + struct amdgpu_device *adev = hwmgr->adev; 2487 2502 2488 2503 data->is_tlu_enabled = false; 2489 2504 ··· 2492 2507 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 2493 2508 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 2494 2509 2495 - sys_info.size = sizeof(struct cgs_system_info); 2496 - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO; 2497 - result = cgs_query_system_info(hwmgr->device, &sys_info); 2498 - if (result) 2499 - data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK; 2500 - else 2501 - data->pcie_gen_cap = (uint32_t)sys_info.value; 2510 + data->pcie_gen_cap = adev->pm.pcie_gen_mask; 2502 2511 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 2503 2512 data->pcie_spc_cap = 20; 2504 - sys_info.size = sizeof(struct cgs_system_info); 2505 - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW; 2506 - result = cgs_query_system_info(hwmgr->device, &sys_info); 2507 - if (result) 2508 - data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK; 2509 - else 2510 - data->pcie_lane_cap = (uint32_t)sys_info.value; 2513 + data->pcie_lane_cap = adev->pm.pcie_mlw_mask; 2511 2514 2512 2515 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 2513 2516 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
+2 -7
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
··· 731 731 int result; 732 732 uint32_t num_se = 0; 733 733 uint32_t count, value, value2; 734 - struct cgs_system_info sys_info = {0}; 734 + struct amdgpu_device *adev = hwmgr->adev; 735 735 736 - sys_info.size = sizeof(struct cgs_system_info); 737 - sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO; 738 - result = cgs_query_system_info(hwmgr->device, &sys_info); 739 - 740 - if (result == 0) 741 - num_se = sys_info.value; 736 + num_se = adev->gfx.config.max_shader_engines; 742 737 743 738 if (PP_CAP(PHM_PlatformCaps_SQRamping) || 744 739 PP_CAP(PHM_PlatformCaps_DBRamping) ||
+5 -13
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
··· 190 190 (struct vega10_hwmgr *)(hwmgr->backend); 191 191 struct phm_ppt_v2_information *table_info = 192 192 (struct phm_ppt_v2_information *)hwmgr->pptable; 193 - struct cgs_system_info sys_info = {0}; 194 - int result; 193 + struct amdgpu_device *adev = hwmgr->adev; 195 194 196 195 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 197 196 PHM_PlatformCaps_SclkDeepSleep); ··· 205 206 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 206 207 PHM_PlatformCaps_EnableSMU7ThermalManagement); 207 208 208 - sys_info.size = sizeof(struct cgs_system_info); 209 - sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS; 210 - result = cgs_query_system_info(hwmgr->device, &sys_info); 211 - 212 - if (!result && (sys_info.value & AMD_PG_SUPPORT_UVD)) 209 + if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 213 210 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 214 211 PHM_PlatformCaps_UVDPowerGating); 215 212 216 - if (!result && (sys_info.value & AMD_PG_SUPPORT_VCE)) 213 + if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 217 214 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 218 215 PHM_PlatformCaps_VCEPowerGating); 219 216 ··· 745 750 struct vega10_hwmgr *data; 746 751 uint32_t config_telemetry = 0; 747 752 struct pp_atomfwctrl_voltage_table vol_table; 748 - struct cgs_system_info sys_info = {0}; 753 + struct amdgpu_device *adev = hwmgr->adev; 749 754 uint32_t reg; 750 755 751 756 data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL); ··· 838 843 hwmgr->platform_descriptor.clockStep.engineClock = 500; 839 844 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 840 845 841 - sys_info.size = sizeof(struct cgs_system_info); 842 - sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO; 843 - result = cgs_query_system_info(hwmgr->device, &sys_info); 844 - data->total_active_cus = sys_info.value; 846 + data->total_active_cus = adev->gfx.cu_info.number; 845 847 /* Setup default Overdrive Fan control settings */ 846 848 data->odn_fan_table.target_fan_speed = 847 849 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
+8 -20
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
··· 933 933 { 934 934 int result; 935 935 uint32_t num_se = 0, count, data; 936 - struct cgs_system_info sys_info = {0}; 936 + struct amdgpu_device *adev = hwmgr->adev; 937 937 uint32_t reg; 938 938 939 - sys_info.size = sizeof(struct cgs_system_info); 940 - sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO; 941 - if (cgs_query_system_info(hwmgr->device, &sys_info) == 0) 942 - num_se = sys_info.value; 939 + num_se = adev->gfx.config.max_shader_engines; 943 940 944 941 cgs_enter_safe_mode(hwmgr->device, true); 945 942 ··· 984 987 { 985 988 int result; 986 989 uint32_t num_se = 0, count, data; 987 - struct cgs_system_info sys_info = {0}; 990 + struct amdgpu_device *adev = hwmgr->adev; 988 991 uint32_t reg; 989 992 990 - sys_info.size = sizeof(struct cgs_system_info); 991 - sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO; 992 - if (cgs_query_system_info(hwmgr->device, &sys_info) == 0) 993 - num_se = sys_info.value; 993 + num_se = adev->gfx.config.max_shader_engines; 994 994 995 995 cgs_enter_safe_mode(hwmgr->device, true); 996 996 ··· 1046 1052 { 1047 1053 int result; 1048 1054 uint32_t num_se = 0, count, data; 1049 - struct cgs_system_info sys_info = {0}; 1055 + struct amdgpu_device *adev = hwmgr->adev; 1050 1056 uint32_t reg; 1051 1057 1052 - sys_info.size = sizeof(struct cgs_system_info); 1053 - sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO; 1054 - if (cgs_query_system_info(hwmgr->device, &sys_info) == 0) 1055 - num_se = sys_info.value; 1058 + num_se = adev->gfx.config.max_shader_engines; 1056 1059 1057 1060 cgs_enter_safe_mode(hwmgr->device, true); 1058 1061 ··· 1094 1103 int result; 1095 1104 uint32_t num_se = 0; 1096 1105 uint32_t count, data; 1097 - struct cgs_system_info sys_info = {0}; 1106 + struct amdgpu_device *adev = hwmgr->adev; 1098 1107 uint32_t reg; 1099 1108 1100 - sys_info.size = sizeof(struct cgs_system_info); 1101 - sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO; 1102 - if (cgs_query_system_info(hwmgr->device, &sys_info) == 0) 1103 - num_se = sys_info.value; 1109 + num_se = adev->gfx.config.max_shader_engines; 1104 1110 1105 1111 cgs_enter_safe_mode(hwmgr->device, true); 1106 1112
+3 -10
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
··· 688 688 uint8_t num_entries; 689 689 struct phm_ppt_v1_clock_voltage_dependency_table 690 690 *clk_table; 691 - struct cgs_system_info sys_info = {0}; 692 691 uint32_t dev_id; 693 692 uint32_t rev_id; 693 + struct amdgpu_device *adev = hwmgr->adev; 694 694 695 695 PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0), 696 696 "Invalid PowerPlay Table!", return -1); ··· 701 701 * This DPM level was added to support 3DPM monitors @ 4K120Hz 702 702 * 703 703 */ 704 - sys_info.size = sizeof(struct cgs_system_info); 705 - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV; 706 - cgs_query_system_info(hwmgr->device, &sys_info); 707 - dev_id = (uint32_t)sys_info.value; 708 - 709 - sys_info.size = sizeof(struct cgs_system_info); 710 - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV; 711 - cgs_query_system_info(hwmgr->device, &sys_info); 712 - rev_id = (uint32_t)sys_info.value; 704 + dev_id = adev->pdev->device; 705 + rev_id = adev->pdev->revision; 713 706 714 707 if (dev_id == 0x6863 && rev_id == 0 && 715 708 clk_dep_table->entries[clk_dep_table->ucNumEntries - 1].ulClk < 90000)
+4 -10
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
··· 236 236 static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) 237 237 { 238 238 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); 239 - struct cgs_system_info sys_info = {0}; 239 + struct amdgpu_device *adev = hwmgr->adev; 240 240 uint32_t dev_id; 241 241 242 - sys_info.size = sizeof(struct cgs_system_info); 243 - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV; 244 - cgs_query_system_info(hwmgr->device, &sys_info); 245 - dev_id = (uint32_t)sys_info.value; 242 + dev_id = adev->pdev->device; 246 243 247 244 switch (dev_id) { 248 245 case 0x67BA: ··· 1306 1309 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); 1307 1310 struct smu7_dpm_table *dpm_table = &data->dpm_table; 1308 1311 int result; 1309 - struct cgs_system_info sys_info = {0}; 1312 + struct amdgpu_device *adev = hwmgr->adev; 1310 1313 uint32_t dev_id; 1311 1314 1312 1315 uint32_t level_array_address = smu_data->dpm_table_start + offsetof(SMU7_Discrete_DpmTable, MemoryLevel); ··· 1327 1330 1328 1331 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; 1329 1332 1330 - sys_info.size = sizeof(struct cgs_system_info); 1331 - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV; 1332 - cgs_query_system_info(hwmgr->device, &sys_info); 1333 - dev_id = (uint32_t)sys_info.value; 1333 + dev_id = adev->pdev->device; 1334 1334 1335 1335 if ((dpm_table->mclk_table.count >= 2) 1336 1336 && ((dev_id == 0x67B0) || (dev_id == 0x67B1))) {
+2 -5
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
··· 281 281 static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) 282 282 { 283 283 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); 284 - struct cgs_system_info sys_info = {0}; 284 + struct amdgpu_device *adev = hwmgr->adev; 285 285 uint32_t dev_id; 286 286 287 - sys_info.size = sizeof(struct cgs_system_info); 288 - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV; 289 - cgs_query_system_info(hwmgr->device, &sys_info); 290 - dev_id = (uint32_t)sys_info.value; 287 + dev_id = adev->pdev->device; 291 288 292 289 switch (dev_id) { 293 290 case DEVICE_ID_VI_ICELAND_M_6900:
+3 -10
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
··· 1623 1623 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = 1624 1624 table_info->vdd_dep_on_sclk; 1625 1625 uint32_t hw_revision, dev_id; 1626 - struct cgs_system_info sys_info = {0}; 1626 + struct amdgpu_device *adev = hwmgr->adev; 1627 1627 1628 1628 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount; 1629 1629 1630 - sys_info.size = sizeof(struct cgs_system_info); 1631 - 1632 - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV; 1633 - cgs_query_system_info(hwmgr->device, &sys_info); 1634 - hw_revision = (uint32_t)sys_info.value; 1635 - 1636 - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV; 1637 - cgs_query_system_info(hwmgr->device, &sys_info); 1638 - dev_id = (uint32_t)sys_info.value; 1630 + hw_revision = adev->pdev->revision; 1631 + dev_id = adev->pdev->device; 1639 1632 1640 1633 /* Read SMU_Eefuse to read and calculate RO and determine 1641 1634 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
+3 -10
drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
··· 349 349 static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr) 350 350 { 351 351 uint32_t smc_driver_if_version; 352 - struct cgs_system_info sys_info = {0}; 352 + struct amdgpu_device *adev = hwmgr->adev; 353 353 uint32_t dev_id; 354 354 uint32_t rev_id; 355 355 ··· 359 359 return -EINVAL); 360 360 vega10_read_arg_from_smc(hwmgr, &smc_driver_if_version); 361 361 362 - sys_info.size = sizeof(struct cgs_system_info); 363 - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV; 364 - cgs_query_system_info(hwmgr->device, &sys_info); 365 - dev_id = (uint32_t)sys_info.value; 366 - 367 - sys_info.size = sizeof(struct cgs_system_info); 368 - sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV; 369 - cgs_query_system_info(hwmgr->device, &sys_info); 370 - rev_id = (uint32_t)sys_info.value; 362 + dev_id = adev->pdev->device; 363 + rev_id = adev->pdev->revision; 371 364 372 365 if (!((dev_id == 0x687f) && 373 366 ((rev_id == 0xc0) ||