[PCI] Do not enable CRS Software Visibility by default

It appears that some PCI-E bridges do the wrong thing in the presense of
CRS Software Visibility and MMCONFIG. In particular, it looks like an
ATI bridge (device ID 7936) will return 0001 in the vendor ID field of
any bridged devices indefinitely.

Not enabling CRS SV avoids the problem, and as we currently do not
really make good use of the feature anyway (we just time out rather than
do any threaded discovery as suggested by the CRS specs), we're better
off just not enabling it.

This should fix a slew of problem reports with random devices (generally
graphics adapters or fairly high-performance networking cards, since it
only affected PCI-E) not getting properly recognized on these AMD systems.

If we really want to use CRS-SV, we may end up eventually needing a
whitelist of systems where this should be enabled, along with some kind
of "pcibios_enable_crs()" query to call the system-specific code.

Suggested-by: Loic Prylli <loic@myri.com>
Tested-by: Kai Ruhnau <kai@tragetaschen.dyndns.org>
Cc: Matthew Wilcox <matthew@wil.cx>
Cc: Greg Kroah-Hartman <greg@kroah.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

-18
-18
drivers/pci/probe.c
··· 455 455 return child; 456 456 } 457 457 458 - static void pci_enable_crs(struct pci_dev *dev) 459 - { 460 - u16 cap, rpctl; 461 - int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP); 462 - if (!rpcap) 463 - return; 464 - 465 - pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap); 466 - if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT) 467 - return; 468 - 469 - pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl); 470 - rpctl |= PCI_EXP_RTCTL_CRSSVE; 471 - pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl); 472 - } 473 - 474 458 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) 475 459 { 476 460 struct pci_bus *parent = child->parent; ··· 500 516 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 501 517 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 502 518 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 503 - 504 - pci_enable_crs(dev); 505 519 506 520 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) { 507 521 unsigned int cmax, busnr;