tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: move reset debug disable handling

Move everything to the supported resets masks rather than
having an explicit misc checks for this.

Reviewed-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex Deucher ad0a48e5 b5e333e6

+32 -22
+3 -5
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
··· 130 130 } 131 131 132 132 /* attempt a per ring reset */ 133 - if (unlikely(adev->debug_disable_gpu_ring_reset)) { 134 - dev_err(adev->dev, "Ring reset disabled by debug mask\n"); 135 - } else if (amdgpu_gpu_recovery && 136 - amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_PER_QUEUE) && 137 - ring->funcs->reset) { 133 + if (amdgpu_gpu_recovery && 134 + amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_PER_QUEUE) && 135 + ring->funcs->reset) { 138 136 dev_err(adev->dev, "Starting %s ring reset\n", 139 137 s_job->sched->name); 140 138 r = amdgpu_ring_reset(ring, job->vmid, job->hw_fence);
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
··· 468 468 ktime_t deadline; 469 469 bool ret; 470 470 471 - if (unlikely(ring->adev->debug_disable_soft_recovery)) 472 - return false; 473 - 474 471 deadline = ktime_add_us(ktime_get(), 10000); 475 472 476 473 if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
+2 -1
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
··· 4956 4956 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 4957 4957 adev->gfx.compute_supported_reset = 4958 4958 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 4959 - if (!amdgpu_sriov_vf(adev)) { 4959 + if (!amdgpu_sriov_vf(adev) && 4960 + !adev->debug_disable_gpu_ring_reset) { 4960 4961 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 4961 4962 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 4962 4963 }
+4 -2
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 1821 1821 case IP_VERSION(11, 0, 3): 1822 1822 if ((adev->gfx.me_fw_version >= 2280) && 1823 1823 (adev->gfx.mec_fw_version >= 2410) && 1824 - !amdgpu_sriov_vf(adev)) { 1824 + !amdgpu_sriov_vf(adev) && 1825 + !adev->debug_disable_gpu_ring_reset) { 1825 1826 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1826 1827 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1827 1828 } 1828 1829 break; 1829 1830 default: 1830 - if (!amdgpu_sriov_vf(adev)) { 1831 + if (!amdgpu_sriov_vf(adev) && 1832 + !adev->debug_disable_gpu_ring_reset) { 1831 1833 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1832 1834 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1833 1835 }
+2 -1
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
··· 1548 1548 case IP_VERSION(12, 0, 1): 1549 1549 if ((adev->gfx.me_fw_version >= 2660) && 1550 1550 (adev->gfx.mec_fw_version >= 2920) && 1551 - !amdgpu_sriov_vf(adev)) { 1551 + !amdgpu_sriov_vf(adev) && 1552 + !adev->debug_disable_gpu_ring_reset) { 1552 1553 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1553 1554 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1554 1555 }
+1 -1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 2409 2409 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 2410 2410 adev->gfx.compute_supported_reset = 2411 2411 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 2412 - if (!amdgpu_sriov_vf(adev)) 2412 + if (!amdgpu_sriov_vf(adev) && !adev->debug_disable_gpu_ring_reset) 2413 2413 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2414 2414 2415 2415 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, 0);
+4 -2
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
··· 1149 1149 case IP_VERSION(9, 4, 3): 1150 1150 case IP_VERSION(9, 4, 4): 1151 1151 if ((adev->gfx.mec_fw_version >= 155) && 1152 - !amdgpu_sriov_vf(adev)) { 1152 + !amdgpu_sriov_vf(adev) && 1153 + !adev->debug_disable_gpu_ring_reset) { 1153 1154 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1154 1155 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1155 1156 } 1156 1157 break; 1157 1158 case IP_VERSION(9, 5, 0): 1158 1159 if ((adev->gfx.mec_fw_version >= 21) && 1159 - !amdgpu_sriov_vf(adev)) { 1160 + !amdgpu_sriov_vf(adev) && 1161 + !adev->debug_disable_gpu_ring_reset) { 1160 1162 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1161 1163 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1162 1164 }
+6 -2
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
··· 2361 2361 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2362 2362 case IP_VERSION(9, 4, 3): 2363 2363 case IP_VERSION(9, 4, 4): 2364 - if ((adev->gfx.mec_fw_version >= 0xb0) && amdgpu_dpm_reset_sdma_is_supported(adev)) 2364 + if ((adev->gfx.mec_fw_version >= 0xb0) && 2365 + amdgpu_dpm_reset_sdma_is_supported(adev) && 2366 + !adev->debug_disable_gpu_ring_reset) 2365 2367 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2366 2368 break; 2367 2369 case IP_VERSION(9, 5, 0): 2368 - if ((adev->gfx.mec_fw_version >= 0xf) && amdgpu_dpm_reset_sdma_is_supported(adev)) 2370 + if ((adev->gfx.mec_fw_version >= 0xf) && 2371 + amdgpu_dpm_reset_sdma_is_supported(adev) && 2372 + !adev->debug_disable_gpu_ring_reset) 2369 2373 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2370 2374 break; 2371 2375 default:
+2 -1
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
··· 1429 1429 case IP_VERSION(5, 0, 2): 1430 1430 case IP_VERSION(5, 0, 5): 1431 1431 if ((adev->sdma.instance[0].fw_version >= 35) && 1432 - !amdgpu_sriov_vf(adev)) 1432 + !amdgpu_sriov_vf(adev) && 1433 + !adev->debug_disable_gpu_ring_reset) 1433 1434 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1434 1435 break; 1435 1436 default:
+4 -2
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
··· 1348 1348 case IP_VERSION(5, 2, 3): 1349 1349 case IP_VERSION(5, 2, 4): 1350 1350 if ((adev->sdma.instance[0].fw_version >= 76) && 1351 - !amdgpu_sriov_vf(adev)) 1351 + !amdgpu_sriov_vf(adev) && 1352 + !adev->debug_disable_gpu_ring_reset) 1352 1353 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1353 1354 break; 1354 1355 case IP_VERSION(5, 2, 5): 1355 1356 if ((adev->sdma.instance[0].fw_version >= 34) && 1356 - !amdgpu_sriov_vf(adev)) 1357 + !amdgpu_sriov_vf(adev) && 1358 + !adev->debug_disable_gpu_ring_reset) 1357 1359 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1358 1360 break; 1359 1361 default:
+2 -1
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
··· 1356 1356 case IP_VERSION(6, 0, 2): 1357 1357 case IP_VERSION(6, 0, 3): 1358 1358 if ((adev->sdma.instance[0].fw_version >= 21) && 1359 - !amdgpu_sriov_vf(adev)) 1359 + !amdgpu_sriov_vf(adev) && 1360 + !adev->debug_disable_gpu_ring_reset) 1360 1361 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1361 1362 break; 1362 1363 default:
+2 -1
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
··· 1337 1337 1338 1338 adev->sdma.supported_reset = 1339 1339 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1340 - if (!amdgpu_sriov_vf(adev)) 1340 + if (!amdgpu_sriov_vf(adev) && 1341 + !adev->debug_disable_gpu_ring_reset) 1341 1342 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1342 1343 1343 1344 r = amdgpu_sdma_sysfs_reset_mask_init(adev);