drm/amdgpu: Add ras module files into amdgpu

Add ras module files into amdgpu.

Signed-off-by: YiPeng Chai <[e-mail]>
Reviewed-by: Tao Zhou <[e-mail]>
Reviewed-by: Hawking Zhang <[e-mail]>
Signed-off-by: Alex Deucher <[e-mail]>

drivers/gpu/drm/amd/amdgpu/Makefile

···
 	-I$(FULL_AMD_DISPLAY_PATH)/modules/inc \
 	-I$(FULL_AMD_DISPLAY_PATH)/dc \
 	-I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \
-	-I$(FULL_AMD_PATH)/amdkfd
+	-I$(FULL_AMD_PATH)/amdkfd \
+	-I$(FULL_AMD_PATH)/ras/ras_mgr
 
 # Locally disable W=1 warnings enabled in drm subsystem Makefile
 subdir-ccflags-y += -Wno-override-init
···
 	isp_v4_1_0.o \
 	isp_v4_1_1.o
 endif
+
+AMD_GPU_RAS_PATH := ../ras
+AMD_GPU_RAS_FULL_PATH := $(FULL_AMD_PATH)/ras
+include $(AMD_GPU_RAS_FULL_PATH)/Makefile
+amdgpu-y += $(AMD_GPU_RAS_FILES)
 
 obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

···
 };
 
 struct amdgpu_ras {
+	void *ras_mgr;
 	/* ras infrastructure */
 	/* for ras itself. */
 	uint32_t features;

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c

···
 	if (!dev_handle || (dev_handle == RAS_CMD_DEV_HANDLE_MAGIC))
 		return NULL;
 
-	ras_core = (struct ras_core_context *)(dev_handle ^ RAS_CMD_DEV_HANDLE_MAGIC);
+	ras_core = (struct ras_core_context *)(uintptr_t)(dev_handle ^ RAS_CMD_DEV_HANDLE_MAGIC);
 
 	if (ras_cmd_get_dev_handle(ras_core) == dev_handle)
 		return ras_core;

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c

···
 	return (struct amdgpu_ras_mgr *)adev->psp.ras_context.ras->ras_mgr;
 }
 
-static const struct amd_ip_funcs ras_v1_0_ip_funcs = {
+static const struct amd_ip_funcs __maybe_unused ras_v1_0_ip_funcs = {
 	.name = "ras_v1_0",
 	.sw_init = amdgpu_ras_mgr_sw_init,
 	.sw_fini = amdgpu_ras_mgr_sw_fini,

drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h

···
 #include <linux/stdarg.h>
 #include <linux/printk.h>
 #include <linux/dev_printk.h>
+#include <linux/mempool.h>
 #include "amdgpu.h"
 
 #define RAS_DEV_ERR(device, fmt, ...)                                               \

drivers/gpu/drm/amd/ras/rascore/ras_aca.c

···
 	struct aca_bank_ecc bank_ecc;
 	struct ras_log_batch_tag *batch_tag = NULL;
 	u32 count = 0;
-	int ret;
+	int ret = 0;
 	int i;
 
 	mutex_lock(&ras_core->ras_aca.bank_op_lock);

drivers/gpu/drm/amd/ras/rascore/ras_cmd.c

···
 {
 	INIT_LIST_HEAD(&ras_core->ras_cmd.head);
 	ras_core->ras_cmd.ras_core = ras_core;
-	ras_core->ras_cmd.dev_handle = (uint64_t)ras_core ^ RAS_CMD_DEV_HANDLE_MAGIC;
+	ras_core->ras_cmd.dev_handle = (uintptr_t)ras_core ^ RAS_CMD_DEV_HANDLE_MAGIC;
 	return 0;
 }
 
···
 	if (!req->buf_size || !req->buf_ptr || !req->cper_num)
 		return RAS_CMD__ERROR_INVALID_INPUT_DATA;
 
-	if (!access_ok((void *)req->buf_ptr, req->buf_size)) {
-		RAS_DEV_ERR(ras_core->dev, "Invalid cper buffer memory!\n");
-		return RAS_CMD__ERROR_INVALID_INPUT_DATA;
-	}
-
 	buffer = kzalloc(req->buf_size, GFP_KERNEL);
 	if (!buffer)
 		return RAS_CMD__ERROR_GENERIC;
···
 	}
 
 	if ((ret && (ret != -ENOMEM)) ||
-		copy_to_user((void *)req->buf_ptr, buffer, offset)) {
+		copy_to_user(u64_to_user_ptr(req->buf_ptr), buffer, offset)) {
 		kfree(buffer);
 		return RAS_CMD__ERROR_GENERIC;
 	}

drivers/gpu/drm/amd/ras/rascore/ras_core.c

···
 	int seconds_per_minute = 60;
 	int days, remaining_seconds;
 
-	days = timestamp / seconds_per_day;
-	remaining_seconds = timestamp % seconds_per_day;
+	days = div64_u64_rem(timestamp, seconds_per_day, (uint64_t *)&remaining_seconds);
 
 	/* utc_timestamp follows the Unix epoch */
 	year = 1970;

drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c

···
 {
 	struct ras_log_ring *log_ring = &ras_core->ras_log_ring;
 	unsigned long flags = 0;
-	int ret;
+	int ret = 0;
 
 	if (batch_tag && (batch_tag->sub_seqno >= MAX_RECORD_PER_BATCH)) {
 		RAS_DEV_ERR(ras_core->dev,
···
 {
 	struct ras_log_ring *log_ring = &ras_core->ras_log_ring;
 	struct ras_log_batch_tag *batch_tag;
-	unsigned long flags;
+	unsigned long flags = 0;
 
 	batch_tag = kzalloc(sizeof(*batch_tag), GFP_KERNEL);
 	if (!batch_tag)

drivers/gpu/drm/amd/ras/rascore/ras_mp1.c

···
 }
 
 int ras_mp1_dump_bank(struct ras_core_context *ras_core,
-		enum ras_err_type type, u32 idx, u32 reg_idx, u64 *val)
+		u32 type, u32 idx, u32 reg_idx, u64 *val)
 {
 	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
 

drivers/gpu/drm/amd/ras/rascore/ras_psp.c

···
 
 	ras_ring_wptr_dw = psp->ip_func->psp_ras_ring_wptr_get(ras_core);
 
-	return (ras_ring_wptr_dw << 2) / sizeof(struct psp_gfx_rb_frame);
+	return div64_u64((ras_ring_wptr_dw << 2), sizeof(struct psp_gfx_rb_frame));
 }
 
 static int __set_ring_frame_slot(struct ras_core_context *ras_core,
···
 		return -ENOMEM;
 
 	max_frame_slot =
-		ring_mem->mem_size / sizeof(struct psp_gfx_rb_frame);
+		div64_u64(ring_mem->mem_size, sizeof(struct psp_gfx_rb_frame));
 
 	rb_frame =
 		(struct psp_gfx_rb_frame *)ring_mem->mem_cpu_addr;