···6666 if (delay < pci_pm_d3_delay)6767 delay = pci_pm_d3_delay;68686969- msleep(delay);6969+ if (delay)7070+ msleep(delay);7071}71727273#ifdef CONFIG_PCI_DOMAINS···828827 * because have already delayed for the bridge.829828 */830829 if (dev->runtime_d3cold) {831831- msleep(dev->d3cold_delay);830830+ if (dev->d3cold_delay)831831+ msleep(dev->d3cold_delay);832832 /*833833 * When powering on a bridge from D3cold, the834834 * whole hierarchy may be powered on into···17841782 }17851783 }17861784 if (!list_empty(&pci_pme_list))17871787- schedule_delayed_work(&pci_pme_work,17881788- msecs_to_jiffies(PME_TIMEOUT));17851785+ queue_delayed_work(system_freezable_wq, &pci_pme_work,17861786+ msecs_to_jiffies(PME_TIMEOUT));17891787 mutex_unlock(&pci_pme_list_mutex);17901788}17911789···18501848 mutex_lock(&pci_pme_list_mutex);18511849 list_add(&pme_dev->list, &pci_pme_list);18521850 if (list_is_singular(&pci_pme_list))18531853- schedule_delayed_work(&pci_pme_work,18541854- msecs_to_jiffies(PME_TIMEOUT));18511851+ queue_delayed_work(system_freezable_wq,18521852+ &pci_pme_work,18531853+ msecs_to_jiffies(PME_TIMEOUT));18551854 mutex_unlock(&pci_pme_list_mutex);18561855 } else {18571856 mutex_lock(&pci_pme_list_mutex);