tjh.dev
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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
selftests: bpf: add tests for shifts by zero
There are currently no tests for ALU64 shift operations when the shift
amount is 0. This adds 6 new tests to make sure they are equivalent
to a no-op. The x32 JIT had such bugs that could have been caught by
these tests.
Cc: Xi Wang <xi.wang@gmail.com>
Signed-off-by: Luke Nelson <luke.r.nels@gmail.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
authored by
Luke Nelson
and committed by
Daniel Borkmann
ac8786c7
6fa632e7
+85
+85
tools/testing/selftests/bpf/verifier/basic_instr.c
+85
tools/testing/selftests/bpf/verifier/basic_instr.c
···
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.result = ACCEPT,
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},
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{
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+
"lsh64 by 0 imm",
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+
.insns = {
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+
BPF_LD_IMM64(BPF_REG_0, 1),
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+
BPF_LD_IMM64(BPF_REG_1, 1),
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+
BPF_ALU64_IMM(BPF_LSH, BPF_REG_1, 0),
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+
BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 1, 1),
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+
BPF_MOV64_IMM(BPF_REG_0, 2),
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+
BPF_EXIT_INSN(),
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+
},
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+
.result = ACCEPT,
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+
.retval = 1,
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+
},
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+
{
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+
"rsh64 by 0 imm",
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+
.insns = {
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+
BPF_LD_IMM64(BPF_REG_0, 1),
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+
BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
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+
BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
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+
BPF_ALU64_IMM(BPF_RSH, BPF_REG_1, 0),
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+
BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
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+
BPF_MOV64_IMM(BPF_REG_0, 2),
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+
BPF_EXIT_INSN(),
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+
},
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+
.result = ACCEPT,
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+
.retval = 1,
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+
},
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+
{
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+
"arsh64 by 0 imm",
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+
.insns = {
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+
BPF_LD_IMM64(BPF_REG_0, 1),
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+
BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
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+
BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
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+
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_1, 0),
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+
BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
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+
BPF_MOV64_IMM(BPF_REG_0, 2),
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+
BPF_EXIT_INSN(),
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+
},
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+
.result = ACCEPT,
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+
.retval = 1,
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+
},
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+
{
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+
"lsh64 by 0 reg",
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+
.insns = {
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+
BPF_LD_IMM64(BPF_REG_0, 1),
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+
BPF_LD_IMM64(BPF_REG_1, 1),
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+
BPF_LD_IMM64(BPF_REG_2, 0),
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+
BPF_ALU64_REG(BPF_LSH, BPF_REG_1, BPF_REG_2),
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+
BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 1, 1),
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+
BPF_MOV64_IMM(BPF_REG_0, 2),
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+
BPF_EXIT_INSN(),
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+
},
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+
.result = ACCEPT,
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+
.retval = 1,
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+
},
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+
{
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+
"rsh64 by 0 reg",
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+
.insns = {
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+
BPF_LD_IMM64(BPF_REG_0, 1),
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+
BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
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+
BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
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+
BPF_LD_IMM64(BPF_REG_3, 0),
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+
BPF_ALU64_REG(BPF_RSH, BPF_REG_1, BPF_REG_3),
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+
BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
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+
BPF_MOV64_IMM(BPF_REG_0, 2),
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+
BPF_EXIT_INSN(),
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+
},
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+
.result = ACCEPT,
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+
.retval = 1,
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+
},
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+
{
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+
"arsh64 by 0 reg",
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+
.insns = {
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+
BPF_LD_IMM64(BPF_REG_0, 1),
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+
BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
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+
BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
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+
BPF_LD_IMM64(BPF_REG_3, 0),
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+
BPF_ALU64_REG(BPF_ARSH, BPF_REG_1, BPF_REG_3),
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+
BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
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+
BPF_MOV64_IMM(BPF_REG_0, 2),
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+
BPF_EXIT_INSN(),
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+
},
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+
.result = ACCEPT,
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+
.retval = 1,
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+
},
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+
{
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"invalid 64-bit BPF_END",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_0, 0),