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drm/i915/dsc: Adding the new registers for DSC
Adding new DSC register which are introducted MTL onwards
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230309062855.393087-4-suraj.kandpal@intel.com
authored by
Suraj Kandpal
and committed by
Uma Shankar
ac754358
5011f291
+28
+28
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+28
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
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_ICL_PIPE_DSS_CTL2_PB, \
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_ICL_PIPE_DSS_CTL2_PC)
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/* MTL Display Stream Compression registers */
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#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB 0x782B4
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#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB 0x783B4
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#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC 0x784B4
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#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC 0x785B4
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#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
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_MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
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_MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
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#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
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_MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
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_MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
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#define DSC_SL_BPG_OFFSET(offset) ((offset) << 27)
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#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB 0x782B8
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#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB 0x783B8
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#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC 0x784B8
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#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC 0x785B8
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#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
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_MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
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_MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
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#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
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_MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
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_MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
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#define DSC_NSL_BPG_OFFSET(offset) ((offset) << 16)
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#define DSC_SL_OFFSET_ADJ(offset) ((offset) << 0)
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/* Icelake Display Stream Compression Registers */
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#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
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#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
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#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
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_ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
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_ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
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#define DSC_NATIVE_422_ENABLE BIT(23)
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#define DSC_NATIVE_420_ENABLE BIT(22)
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#define DSC_ALT_ICH_SEL (1 << 20)
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#define DSC_VBR_ENABLE (1 << 19)
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#define DSC_422_ENABLE (1 << 18)