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scsi: docs: convert hptiop.txt to ReST

Link: https://lore.kernel.org/r/d189a339bb360b7b397914ee3ddeb75d9a7fd788.1583136624.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

authored by

Mauro Carvalho Chehab and committed by
Martin K. Petersen ac69461b 1392de9d

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+38 -7
Documentation/scsi/hptiop.txt Documentation/scsi/hptiop.rst
··· 1 - HIGHPOINT ROCKETRAID 3xxx/4xxx ADAPTER DRIVER (hptiop) 1 + .. SPDX-License-Identifier: GPL-2.0 2 + .. include:: <isonum.txt> 3 + 4 + ====================================================== 5 + Highpoint RocketRAID 3xxx/4xxx Adapter Driver (hptiop) 6 + ====================================================== 2 7 3 8 Controller Register Map 4 - ------------------------- 9 + ----------------------- 5 10 6 - For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2: 11 + For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2 7 12 13 + ============== ================================== 8 14 BAR0 offset Register 15 + ============== ================================== 9 16 0x11C5C Link Interface IRQ Set 10 17 0x11C60 Link Interface IRQ Clear 18 + ============== ================================== 11 19 20 + ============== ================================== 12 21 BAR2 offset Register 22 + ============== ================================== 13 23 0x10 Inbound Message Register 0 14 24 0x14 Inbound Message Register 1 15 25 0x18 Outbound Message Register 0 ··· 31 21 0x34 Outbound Interrupt Mask Register 32 22 0x40 Inbound Queue Port 33 23 0x44 Outbound Queue Port 24 + ============== ================================== 34 25 35 26 For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0: 36 27 28 + ============== ================================== 37 29 BAR0 offset Register 30 + ============== ================================== 38 31 0x10 Inbound Message Register 0 39 32 0x14 Inbound Message Register 1 40 33 0x18 Outbound Message Register 0 ··· 49 36 0x34 Outbound Interrupt Mask Register 50 37 0x40 Inbound Queue Port 51 38 0x44 Outbound Queue Port 39 + ============== ================================== 52 40 53 41 For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1: 54 42 43 + ============== ================================== 55 44 BAR0 offset Register 45 + ============== ================================== 56 46 0x20400 Inbound Doorbell Register 57 47 0x20404 Inbound Interrupt Mask Register 58 48 0x20408 Outbound Doorbell Register 59 49 0x2040C Outbound Interrupt Mask Register 50 + ============== ================================== 60 51 52 + ============== ================================== 61 53 BAR1 offset Register 54 + ============== ================================== 62 55 0x0 Inbound Queue Head Pointer 63 56 0x4 Inbound Queue Tail Pointer 64 57 0x8 Outbound Queue Head Pointer ··· 72 53 0x10 Inbound Message Register 73 54 0x14 Outbound Message Register 74 55 0x40-0x1040 Inbound Queue 75 - 0x1040-0x2040 Outbound Queue 56 + 0x1040-0x2040 Outbound Queue 57 + ============== ================================== 76 58 77 59 For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1: 78 60 61 + ============== ================================== 79 62 BAR0 offset Register 63 + ============== ================================== 80 64 0x0 IOP configuration information. 65 + ============== ================================== 81 66 67 + ============== =================================================== 82 68 BAR1 offset Register 69 + ============== =================================================== 83 70 0x4000 Inbound List Base Address Low 84 71 0x4004 Inbound List Base Address High 85 72 0x4018 Inbound List Write Pointer ··· 101 76 0x10420 CPU to PCIe Function 0 Message A 102 77 0x10480 CPU to PCIe Function 0 Doorbell 103 78 0x10484 CPU to PCIe Function 0 Doorbell Enable 79 + ============== =================================================== 104 80 105 81 106 82 I/O Request Workflow of Not Marvell Frey 107 - ------------------------------------------ 83 + ---------------------------------------- 108 84 109 85 All queued requests are handled via inbound/outbound queue port. 110 86 A request packet can be allocated in either IOP or host memory. ··· 150 124 151 125 152 126 I/O Request Workflow of Marvell Frey 153 - -------------------------------------- 127 + ------------------------------------ 154 128 155 129 All queued requests are handled via inbound/outbound list. 156 130 ··· 193 167 194 168 The driver exposes following sysfs attributes: 195 169 170 + ================== === ======================== 196 171 NAME R/W Description 172 + ================== === ======================== 197 173 driver-version R driver version string 198 174 firmware-version R firmware version string 175 + ================== === ======================== 199 176 200 177 201 178 ----------------------------------------------------------------------------- 202 - Copyright (C) 2006-2012 HighPoint Technologies, Inc. All Rights Reserved. 179 + 180 + Copyright |copy| 2006-2012 HighPoint Technologies, Inc. All Rights Reserved. 203 181 204 182 This file is distributed in the hope that it will be useful, 205 183 but WITHOUT ANY WARRANTY; without even the implied warranty of ··· 211 181 GNU General Public License for more details. 212 182 213 183 linux@highpoint-tech.com 184 + 214 185 http://www.highpoint-tech.com
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Documentation/scsi/index.rst
··· 22 22 FlashPoint 23 23 g_NCR5380 24 24 hpsa 25 + hptiop 25 26 26 27 scsi_transport_srp/figures
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MAINTAINERS
··· 7505 7505 M: HighPoint Linux Team <linux@highpoint-tech.com> 7506 7506 W: http://www.highpoint-tech.com 7507 7507 S: Supported 7508 - F: Documentation/scsi/hptiop.txt 7508 + F: Documentation/scsi/hptiop.rst 7509 7509 F: drivers/scsi/hptiop.c 7510 7510 7511 7511 HIPPI