Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

staging: winbond: remove driver

The driver hasn't been cleaned up and nobody is working to do so, so
remove it.

Signed-off-by: Kristina Martšenko <kristina.martsenko@gmail.com>
Cc: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Kristina Martšenko and committed by
Greg Kroah-Hartman
ac4ddad6 c0cd6e5b

-8758
-5
MAINTAINERS
··· 8631 8631 S: Odd Fixes 8632 8632 F: drivers/staging/vt665?/ 8633 8633 8634 - STAGING - WINBOND IS89C35 WLAN USB DRIVER 8635 - M: Pavel Machek <pavel@ucw.cz> 8636 - S: Odd Fixes 8637 - F: drivers/staging/winbond/ 8638 - 8639 8634 STAGING - XGI Z7,Z9,Z11 PCI DISPLAY DRIVER 8640 8635 M: Arnaud Patard <arnaud.patard@rtp-net.org> 8641 8636 S: Odd Fixes
-2
drivers/staging/Kconfig
··· 30 30 31 31 source "drivers/staging/usbip/Kconfig" 32 32 33 - source "drivers/staging/winbond/Kconfig" 34 - 35 33 source "drivers/staging/wlan-ng/Kconfig" 36 34 37 35 source "drivers/staging/comedi/Kconfig"
-1
drivers/staging/Makefile
··· 7 7 obj-$(CONFIG_ET131X) += et131x/ 8 8 obj-$(CONFIG_SLICOSS) += slicoss/ 9 9 obj-$(CONFIG_USBIP_CORE) += usbip/ 10 - obj-$(CONFIG_W35UND) += winbond/ 11 10 obj-$(CONFIG_PRISM2_USB) += wlan-ng/ 12 11 obj-$(CONFIG_COMEDI) += comedi/ 13 12 obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon/
-11
drivers/staging/winbond/Kconfig
··· 1 - config W35UND 2 - tristate "IS89C35 WLAN USB driver" 3 - depends on MAC80211 && WLAN && USB 4 - default n 5 - ---help--- 6 - This is highly experimental driver for Winbond WIFI card. 7 - 8 - Hardware is present in some Kohjinsha subnotebooks, and in some 9 - stand-alone USB modules. Chipset name seems to be w89c35d. 10 - 11 - Check <http://code.google.com/p/winbondport/> for new version.
-15
drivers/staging/winbond/Makefile
··· 1 - w35und-y := \ 2 - mds.o \ 3 - mto.o \ 4 - phy_calibration.o \ 5 - reg.o \ 6 - wb35reg.o \ 7 - wb35rx.o \ 8 - wb35tx.o \ 9 - wbusb.o \ 10 - 11 - 12 - obj-$(CONFIG_W35UND) += w35und.o 13 - 14 - 15 -
-12
drivers/staging/winbond/TODO
··· 1 - TODO: 2 - - sparse cleanups 3 - - checkpatch cleanups 4 - - kerneldoc cleanups 5 - - fix severeCamelCaseInfestation 6 - - remove unused ioctls 7 - - use cfg80211 for regulatory stuff 8 - - fix 4k stack problems 9 - - fix locking problems (it's done using atomics...) 10 - 11 - Please send patches to Greg Kroah-Hartman <greg@kroah.com> and 12 - Pavel Machek <pavel@ucw.cz>
-61
drivers/staging/winbond/core.h
··· 1 - #ifndef __WINBOND_CORE_H 2 - #define __WINBOND_CORE_H 3 - 4 - #include <linux/wireless.h> 5 - #include <linux/types.h> 6 - #include <linux/delay.h> 7 - 8 - #include "wbhal.h" 9 - #include "mto.h" 10 - 11 - #include "mac_structures.h" 12 - #include "mds_s.h" 13 - 14 - #define MAX_NUM_TX_MMPDU 2 15 - #define MAX_MMPDU_SIZE 1512 16 - #define MAX_NUM_RX_MMPDU 6 17 - 18 - struct mlme_frame { 19 - s8 *pMMPDU; 20 - u16 len; 21 - u8 data_type; 22 - u8 is_in_used; 23 - 24 - u8 TxMMPDU[MAX_NUM_TX_MMPDU][MAX_MMPDU_SIZE]; 25 - u8 TxMMPDUInUse[(MAX_NUM_TX_MMPDU + 3) & ~0x03]; 26 - 27 - u16 wNumTxMMPDU; 28 - u16 wNumTxMMPDUDiscarded; 29 - 30 - u8 RxMMPDU[MAX_NUM_RX_MMPDU][MAX_MMPDU_SIZE]; 31 - u8 SaveRxBufSlotInUse[(MAX_NUM_RX_MMPDU + 3) & ~0x03]; 32 - 33 - u16 wNumRxMMPDU; 34 - u16 wNumRxMMPDUDiscarded; 35 - 36 - u16 wNumRxMMPDUInMLME; /* Number of the Rx MMPDU */ 37 - u16 reserved_1; /* in MLME. */ 38 - /* excluding the discarded */ 39 - }; 40 - 41 - #define WBLINUX_PACKET_ARRAY_SIZE (ETHERNET_TX_DESCRIPTORS*4) 42 - 43 - #define WB_MAX_LINK_NAME_LEN 40 44 - 45 - struct wbsoft_priv { 46 - struct wb_local_para sLocalPara; /* Myself connected 47 - parameters */ 48 - 49 - struct mlme_frame sMlmeFrame; /* connect to peerSTA parameters */ 50 - 51 - struct wb35_mto_params sMtoPara; /* MTO_struct ... */ 52 - struct hw_data sHwData; /*For HAL */ 53 - struct wb35_mds Mds; 54 - 55 - u32 RxByteCount; 56 - u32 TxByteCount; 57 - 58 - bool enabled; 59 - }; 60 - 61 - #endif /* __WINBOND_CORE_H */
-311
drivers/staging/winbond/localpara.h
··· 1 - #ifndef __WINBOND_LOCALPARA_H 2 - #define __WINBOND_LOCALPARA_H 3 - 4 - /* 5 - * ============================================================= 6 - * LocalPara.h - 7 - * ============================================================= 8 - */ 9 - 10 - #include "mac_structures.h" 11 - 12 - /* Define the local ability */ 13 - 14 - #define LOCAL_DEFAULT_BEACON_PERIOD 100 /* ms */ 15 - #define LOCAL_DEFAULT_ATIM_WINDOW 0 16 - #define LOCAL_DEFAULT_ERP_CAPABILITY 0x0431 /* 17 - * 0x0001: ESS 18 - * 0x0010: Privacy 19 - * 0x0020: short preamble 20 - * 0x0400: short slot time 21 - */ 22 - #define LOCAL_DEFAULT_LISTEN_INTERVAL 5 23 - 24 - #define LOCAL_DEFAULT_24_CHANNEL_NUM 13 /* channel 1..13 */ 25 - #define LOCAL_DEFAULT_5_CHANNEL_NUM 8 /* channel 36..64 */ 26 - 27 - #define LOCAL_USA_24_CHANNEL_NUM 11 28 - #define LOCAL_USA_5_CHANNEL_NUM 12 29 - #define LOCAL_EUROPE_24_CHANNEL_NUM 13 30 - #define LOCAL_EUROPE_5_CHANNEL_NUM 19 31 - #define LOCAL_JAPAN_24_CHANNEL_NUM 14 32 - #define LOCAL_JAPAN_5_CHANNEL_NUM 11 33 - #define LOCAL_UNKNOWN_24_CHANNEL_NUM 14 34 - #define LOCAL_UNKNOWN_5_CHANNEL_NUM 34 /* not include 165 */ 35 - 36 - #define psLOCAL (&(adapter->sLocalPara)) 37 - 38 - #define MODE_802_11_BG 0 39 - #define MODE_802_11_A 1 40 - #define MODE_802_11_ABG 2 41 - #define MODE_802_11_BG_IBSS 3 42 - #define MODE_802_11_B 4 43 - #define MODE_AUTO 255 44 - 45 - #define BAND_TYPE_DSSS 0 46 - #define BAND_TYPE_OFDM_24 1 47 - #define BAND_TYPE_OFDM_5 2 48 - 49 - /* refer Bitmap2RateValue table */ 50 - 51 - /* the bitmap value of all the H/W supported rates: */ 52 - /* 1, 2, 5.5, 11, 6, 9, 12, 18, 24, 36, 48, 54 */ 53 - #define LOCAL_ALL_SUPPORTED_RATES_BITMAP 0x130c1a66 54 - /* the bitmap value of all the H/W supported rates except to non-OFDM rates: */ 55 - /* 6, 9, 12, 18, 24, 36, 48, 54 */ 56 - #define LOCAL_OFDM_SUPPORTED_RATES_BITMAP 0x130c1240 57 - #define LOCAL_11B_SUPPORTED_RATE_BITMAP 0x826 58 - #define LOCAL_11B_BASIC_RATE_BITMAP 0x826 59 - #define LOCAL_11B_OPERATION_RATE_BITMAP 0x826 60 - #define LOCAL_11G_BASIC_RATE_BITMAP 0x826 /* 1, 2, 5.5, 11 */ 61 - #define LOCAL_11G_OPERATION_RATE_BITMAP 0x130c1240 /* 6, 9, 12, 18, 62 - * 24, 36, 48, 54 63 - */ 64 - #define LOCAL_11A_BASIC_RATE_BITMAP 0x01001040 /* 6, 12, 24 */ 65 - #define LOCAL_11A_OPERATION_RATE_BITMAP 0x120c0200 /* 9, 18, 36, 66 - * 48, 54 67 - */ 68 - 69 - 70 - #define PWR_ACTIVE 0 71 - #define PWR_SAVE 1 72 - #define PWR_TX_IDLE_CYCLE 6 73 - 74 - /* bPreambleMode and bSlotTimeMode */ 75 - #define AUTO_MODE 0 76 - #define LONG_MODE 1 77 - 78 - /* Region definition */ 79 - #define REGION_AUTO 0xff 80 - #define REGION_UNKNOWN 0 81 - #define REGION_EUROPE 1 /* ETSI */ 82 - #define REGION_JAPAN 2 /* MKK */ 83 - #define REGION_USA 3 /* FCC */ 84 - #define REGION_FRANCE 4 /* FRANCE */ 85 - #define REGION_SPAIN 5 /* SPAIN */ 86 - #define REGION_ISRAEL 6 /* ISRAEL */ 87 - 88 - #define MAX_BSS_DESCRIPT_ELEMENT 32 89 - #define MAX_PMKID_CandidateList 16 90 - 91 - /* 92 - * High byte : Event number, low byte : reason 93 - * Event definition 94 - * -- SME/MLME event 95 - */ 96 - #define EVENT_RCV_DEAUTH 0x0100 97 - #define EVENT_JOIN_FAIL 0x0200 98 - #define EVENT_AUTH_FAIL 0x0300 99 - #define EVENT_ASSOC_FAIL 0x0400 100 - #define EVENT_LOST_SIGNAL 0x0500 101 - #define EVENT_BSS_DESCRIPT_LACK 0x0600 102 - #define EVENT_COUNTERMEASURE 0x0700 103 - #define EVENT_JOIN_FILTER 0x0800 104 - /* -- TX/RX event */ 105 - #define EVENT_RX_BUFF_UNAVAILABLE 0x4100 106 - 107 - #define EVENT_CONNECT 0x8100 108 - #define EVENT_DISCONNECT 0x8200 109 - #define EVENT_SCAN_REQ 0x8300 110 - 111 - /* Reason of Event */ 112 - #define EVENT_REASON_FILTER_BASIC_RATE 0x0001 113 - #define EVENT_REASON_FILTER_PRIVACY 0x0002 114 - #define EVENT_REASON_FILTER_AUTH_MODE 0x0003 115 - #define EVENT_REASON_TIMEOUT 0x00ff 116 - 117 - /* Due to[E id][Length][OUI][Data] may be 257 bytes */ 118 - #define MAX_IE_APPEND_SIZE (256 + 4) 119 - 120 - struct chan_info { 121 - u8 band; 122 - u8 ChanNo; 123 - }; 124 - 125 - struct radio_off { 126 - u8 boHwRadioOff; 127 - u8 boSwRadioOff; 128 - }; 129 - 130 - struct wb_local_para { 131 - /* read from EPROM, manufacture set for each NetCard */ 132 - u8 PermanentAddress[MAC_ADDR_LENGTH + 2]; 133 - /* the driver will use this one actually. */ 134 - u8 ThisMacAddress[MAC_ADDR_LENGTH + 2]; 135 - u32 MTUsize; /* Ind to Uplayer, Max transmission unit size */ 136 - u8 region_INF; /* region setting from INF */ 137 - u8 region; /* real region setting of the device */ 138 - u8 Reserved_1[2]; 139 - 140 - /* power-save variables */ 141 - u8 iPowerSaveMode; /* 0 indicates on, 1 indicates off */ 142 - u8 ATIMmode; 143 - u8 ExcludeUnencrypted; 144 - /* Unit time count for the decision to enter PS mode */ 145 - u16 CheckCountForPS; 146 - u8 boHasTxActivity;/* tx activity has occurred */ 147 - u8 boMacPsValid; /* Power save mode obtained 148 - * from H/W is valid or not 149 - */ 150 - 151 - /* Rate */ 152 - u8 TxRateMode; /* 153 - * Initial, input from Registry, 154 - * may be updated by GUI 155 - * Tx Rate Mode: auto(DTO on), max, 1M, 2M, .. 156 - */ 157 - u8 CurrentTxRate; /* The current Tx rate */ 158 - u8 CurrentTxRateForMng; /* 159 - * The current Tx rate for management 160 - * frames. It will be decided before 161 - * connection succeeds. 162 - */ 163 - u8 CurrentTxFallbackRate; 164 - 165 - /* for Rate handler */ 166 - u8 BRateSet[32]; /* basic rate set */ 167 - u8 SRateSet[32]; /* support rate set */ 168 - 169 - u8 NumOfBRate; 170 - u8 NumOfSRate; 171 - u8 NumOfDsssRateInSRate; /* number of DSSS rates in 172 - * supported rate set 173 - */ 174 - u8 reserved1; 175 - 176 - u32 dwBasicRateBitmap; /* bit map of basic rates */ 177 - 178 - u32 dwSupportRateBitmap; /* bit map of all support rates 179 - * including basic and operational 180 - * rates 181 - */ 182 - 183 - 184 - /* For SME/MLME handler */ 185 - 186 - u16 wOldSTAindex; /* valid when boHandover=TRUE, 187 - * store old connected STA index 188 - */ 189 - u16 wConnectedSTAindex; /* Index of peerly connected AP or 190 - * IBSS in the descriptionset. 191 - */ 192 - u16 Association_ID; /* The Association ID in the 193 - * (Re)Association Response frame. 194 - */ 195 - u16 ListenInterval; /* The listen interval when SME invoking 196 - * MLME_ (Re)Associate_Request(). 197 - */ 198 - 199 - struct radio_off RadioOffStatus; 200 - u8 Reserved0[2]; 201 - u8 boMsRadioOff; /* Ndis demands to be true when set 202 - * Disassoc. OID and be false when 203 - * set SSID OID. 204 - */ 205 - u8 bAntennaNo; /* which antenna */ 206 - u8 bConnectFlag; /* the connect status flag for 207 - * roaming task 208 - */ 209 - 210 - u8 RoamStatus; 211 - u8 reserved7[3]; 212 - 213 - struct chan_info CurrentChan; /* Current channel no. and channel band. 214 - * It may be changed by scanning. 215 - */ 216 - u8 boHandover; /* Roaming, Handover to other AP. */ 217 - u8 boCCAbusy; 218 - 219 - u16 CWMax; /* It may not be the real value 220 - * that H/W used 221 - */ 222 - u8 CWMin; /* 255: set according to 802.11 spec. */ 223 - u8 reserved2; 224 - 225 - /* 11G: */ 226 - u8 bMacOperationMode; /* operation in 802.11b or 802.11g */ 227 - u8 bSlotTimeMode; /* AUTO, s32 */ 228 - u8 bPreambleMode; /* AUTO, s32 */ 229 - u8 boNonERPpresent; 230 - 231 - u8 boProtectMechanism; /* H/W will take the necessary action 232 - * based on this variable 233 - */ 234 - u8 boShortPreamble; /* Same here */ 235 - u8 boShortSlotTime; /* Same here */ 236 - u8 reserved_3; 237 - 238 - u32 RSN_IE_Bitmap; 239 - u32 RSN_OUI_Type; 240 - 241 - /* For the BSSID */ 242 - u8 HwBssid[MAC_ADDR_LENGTH + 2]; 243 - u32 HwBssidValid; 244 - 245 - /* For scan list */ 246 - u8 BssListCount; /* Total count of valid 247 - * descriptor indexes 248 - */ 249 - u8 boReceiveUncorrectInfo; /* important settings in beacon/probe 250 - * resp. have been changed 251 - */ 252 - u8 NoOfJoinerInIbss; 253 - u8 reserved_4; 254 - 255 - /* Store the valid descriptor indexes obtained from scannings */ 256 - u8 BssListIndex[(MAX_BSS_DESCRIPT_ELEMENT + 3) & ~0x03]; 257 - /* 258 - * Save the BssDescriptor index in this IBSS. 259 - * The index 0 is local descriptor (psLOCAL->wConnectedSTAindex). 260 - * If CONNECTED : NoOfJoinerInIbss >= 2 261 - * else : NoOfJoinerInIbss <= 1 262 - */ 263 - u8 JoinerInIbss[(MAX_BSS_DESCRIPT_ELEMENT + 3) & ~0x03]; 264 - 265 - /* General Statistics, count at Rx_handler or 266 - * Tx_callback interrupt handler 267 - */ 268 - u64 GS_XMIT_OK; /* Good Frames Transmitted */ 269 - u64 GS_RCV_OK; /* Good Frames Received */ 270 - u32 GS_RCV_ERROR; /* Frames received with crc error */ 271 - u32 GS_XMIT_ERROR; /* Bad Frames Transmitted */ 272 - u32 GS_RCV_NO_BUFFER; /* Receive Buffer underrun */ 273 - u32 GS_XMIT_ONE_COLLISION; /* one collision */ 274 - u32 GS_XMIT_MORE_COLLISIONS;/* more collisions */ 275 - 276 - /* 277 - * ================================================================ 278 - * Statistics (no matter whether it had done successfully) -wkchen 279 - * ================================================================ 280 - */ 281 - u32 _NumRxMSDU; 282 - u32 _NumTxMSDU; 283 - u32 _dot11WEPExcludedCount; 284 - u32 _dot11WEPUndecryptableCount; 285 - u32 _dot11FrameDuplicateCount; 286 - 287 - struct chan_info IbssChanSetting; /* 2B. Start IBSS Channel 288 - * setting by registry or 289 - * WWU. 290 - */ 291 - u8 reserved_5[2]; /* It may not be used after 292 - * considering RF type, region 293 - * and modulation type. 294 - */ 295 - 296 - u8 reserved_6[2]; /* two variables are for wep 297 - * key error detection 298 - */ 299 - u32 bWepKeyError; 300 - u32 bToSelfPacketReceived; 301 - u32 WepKeyDetectTimerCount; 302 - 303 - u16 SignalLostTh; 304 - u16 SignalRoamTh; 305 - 306 - u8 IE_Append_data[MAX_IE_APPEND_SIZE]; 307 - u16 IE_Append_size; 308 - u16 reserved_7; 309 - }; 310 - 311 - #endif
-71
drivers/staging/winbond/mac_structures.h
··· 1 - /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 - // MAC_Structures.h 3 - // 4 - // This file contains the definitions and data structures used by SW-MAC. 5 - // 6 - // Revision Histoy 7 - //================= 8 - // 0.1 2002 UN00 9 - // 0.2 20021004 PD43 CCLiu6 10 - // 20021018 PD43 CCLiu6 11 - // Add enum_TxRate type 12 - // Modify enum_STAState type 13 - // 0.3 20021023 PE23 CYLiu update MAC session struct 14 - // 20021108 15 - // 20021122 PD43 Austin 16 - // Deleted some unused. 17 - // 20021129 PD43 Austin 18 - // 20030617 increase the 802.11g definition 19 - //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 20 - 21 - #ifndef _MAC_Structures_H_ 22 - #define _MAC_Structures_H_ 23 - 24 - #define MAC_ADDR_LENGTH 6 25 - 26 - /* ======================================================== 27 - // 802.11 Frame define 28 - //----- */ 29 - #define DOT_11_MAC_HEADER_SIZE 24 30 - #define DOT_11_SNAP_SIZE 6 31 - #define DOT_11_DURATION_OFFSET 2 32 - /* Sequence control offset */ 33 - #define DOT_11_SEQUENCE_OFFSET 22 34 - /* The start offset of 802.11 Frame// */ 35 - #define DOT_11_TYPE_OFFSET 30 36 - #define DOT_11_DATA_OFFSET 24 37 - #define DOT_11_DA_OFFSET 4 38 - 39 - #define MAX_ETHERNET_PACKET_SIZE 1514 40 - 41 - /* ----- management : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7) */ 42 - #define MAC_SUBTYPE_MNGMNT_ASSOC_REQUEST 0x00 43 - #define MAC_SUBTYPE_MNGMNT_ASSOC_RESPONSE 0x10 44 - #define MAC_SUBTYPE_MNGMNT_REASSOC_REQUEST 0x20 45 - #define MAC_SUBTYPE_MNGMNT_REASSOC_RESPONSE 0x30 46 - #define MAC_SUBTYPE_MNGMNT_PROBE_REQUEST 0x40 47 - #define MAC_SUBTYPE_MNGMNT_PROBE_RESPONSE 0x50 48 - #define MAC_SUBTYPE_MNGMNT_BEACON 0x80 49 - #define MAC_SUBTYPE_MNGMNT_ATIM 0x90 50 - #define MAC_SUBTYPE_MNGMNT_DISASSOCIATION 0xA0 51 - #define MAC_SUBTYPE_MNGMNT_AUTHENTICATION 0xB0 52 - #define MAC_SUBTYPE_MNGMNT_DEAUTHENTICATION 0xC0 53 - 54 - #define RATE_AUTO 0 55 - #define RATE_1M 2 56 - #define RATE_2M 4 57 - #define RATE_5dot5M 11 58 - #define RATE_6M 12 59 - #define RATE_9M 18 60 - #define RATE_11M 22 61 - #define RATE_12M 24 62 - #define RATE_18M 36 63 - #define RATE_22M 44 64 - #define RATE_24M 48 65 - #define RATE_33M 66 66 - #define RATE_36M 72 67 - #define RATE_48M 96 68 - #define RATE_54M 108 69 - #define RATE_MAX 255 70 - 71 - #endif /* _MAC_Structure_H_ */
-650
drivers/staging/winbond/mds.c
··· 1 - #include "mds_f.h" 2 - #include "mto.h" 3 - #include "wbhal.h" 4 - #include "wb35tx_f.h" 5 - 6 - unsigned char 7 - Mds_initial(struct wbsoft_priv *adapter) 8 - { 9 - struct wb35_mds *pMds = &adapter->Mds; 10 - 11 - pMds->TxPause = false; 12 - pMds->TxRTSThreshold = DEFAULT_RTSThreshold; 13 - pMds->TxFragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; 14 - 15 - return hal_get_tx_buffer(&adapter->sHwData, &pMds->pTxBuffer); 16 - } 17 - 18 - static void Mds_DurationSet(struct wbsoft_priv *adapter, 19 - struct wb35_descriptor *pDes, u8 *buffer) 20 - { 21 - struct T00_descriptor *pT00; 22 - struct T01_descriptor *pT01; 23 - u16 Duration, NextBodyLen, OffsetSize; 24 - u8 Rate, i; 25 - unsigned char CTS_on = false, RTS_on = false; 26 - struct T00_descriptor *pNextT00; 27 - u16 BodyLen = 0; 28 - unsigned char boGroupAddr = false; 29 - 30 - OffsetSize = pDes->FragmentThreshold + 32 + 3; 31 - OffsetSize &= ~0x03; 32 - Rate = pDes->TxRate >> 1; 33 - if (!Rate) 34 - Rate = 1; 35 - 36 - pT00 = (struct T00_descriptor *)buffer; 37 - pT01 = (struct T01_descriptor *)(buffer+4); 38 - pNextT00 = (struct T00_descriptor *)(buffer+OffsetSize); 39 - 40 - if (buffer[DOT_11_DA_OFFSET+8] & 0x1) /* +8 for USB hdr */ 41 - boGroupAddr = true; 42 - 43 - /****************************************** 44 - * Set RTS/CTS mechanism 45 - ******************************************/ 46 - if (!boGroupAddr) { 47 - /* NOTE : If the protection mode is enabled and the MSDU will 48 - * be fragmented, the tx rates of MPDUs will all be DSSS 49 - * rates. So it will not use CTS-to-self in this case. 50 - * CTS-To-self will only be used when without 51 - * fragmentation. -- 20050112 */ 52 - BodyLen = (u16)pT00->T00_frame_length; /* include 802.11 header */ 53 - BodyLen += 4; /* CRC */ 54 - 55 - if (BodyLen >= CURRENT_RTS_THRESHOLD) 56 - RTS_on = true; /* Using RTS */ 57 - else { 58 - if (pT01->T01_modulation_type) { /* Is using OFDM */ 59 - /* Is using protect */ 60 - if (CURRENT_PROTECT_MECHANISM) 61 - CTS_on = true; /* Using CTS */ 62 - } 63 - } 64 - } 65 - 66 - if (RTS_on || CTS_on) { 67 - if (pT01->T01_modulation_type) { /* Is using OFDM */ 68 - /* CTS duration 69 - * 2 SIFS + DATA transmit time + 1 ACK 70 - * ACK Rate : 24 Mega bps 71 - * ACK frame length = 14 bytes */ 72 - Duration = 2*DEFAULT_SIFSTIME + 73 - 2*PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION + 74 - ((BodyLen*8 + 22 + Rate*4 - 1)/(Rate*4))*Tsym + 75 - ((112 + 22 + 95)/96)*Tsym; 76 - } else { /* DSSS */ 77 - /* CTS duration 78 - * 2 SIFS + DATA transmit time + 1 ACK 79 - * Rate : ?? Mega bps 80 - * ACK frame length = 14 bytes */ 81 - if (pT01->T01_plcp_header_length) /* long preamble */ 82 - Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*2; 83 - else 84 - Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*2; 85 - 86 - Duration += (((BodyLen + 14)*8 + Rate-1) / Rate + 87 - DEFAULT_SIFSTIME*2); 88 - } 89 - 90 - if (RTS_on) { 91 - if (pT01->T01_modulation_type) { /* Is using OFDM */ 92 - /* CTS + 1 SIFS + CTS duration 93 - * CTS Rate : 24 Mega bps 94 - * CTS frame length = 14 bytes */ 95 - Duration += (DEFAULT_SIFSTIME + 96 - PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION + 97 - ((112 + 22 + 95)/96)*Tsym); 98 - } else { 99 - /* CTS + 1 SIFS + CTS duration 100 - * CTS Rate : ?? Mega bps 101 - * CTS frame length = 14 bytes 102 - */ 103 - /* long preamble */ 104 - if (pT01->T01_plcp_header_length) 105 - Duration += LONG_PREAMBLE_PLUS_PLCPHEADER_TIME; 106 - else 107 - Duration += SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME; 108 - 109 - Duration += (((112 + Rate-1) / Rate) + 110 - DEFAULT_SIFSTIME); 111 - } 112 - } 113 - 114 - /* Set the value into USB descriptor */ 115 - pT01->T01_add_rts = RTS_on ? 1 : 0; 116 - pT01->T01_add_cts = CTS_on ? 1 : 0; 117 - pT01->T01_rts_cts_duration = Duration; 118 - } 119 - 120 - /****************************************** 121 - * Fill the more fragment descriptor 122 - ******************************************/ 123 - if (boGroupAddr) 124 - Duration = 0; 125 - else { 126 - for (i = pDes->FragmentCount-1; i > 0; i--) { 127 - NextBodyLen = (u16)pNextT00->T00_frame_length; 128 - NextBodyLen += 4; /* CRC */ 129 - 130 - if (pT01->T01_modulation_type) { 131 - /* OFDM 132 - * data transmit time + 3 SIFS + 2 ACK 133 - * Rate : ??Mega bps 134 - * ACK frame length = 14 bytes, tx rate = 24M */ 135 - Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION * 3; 136 - Duration += (((NextBodyLen*8 + 22 + Rate*4 - 1) 137 - /(Rate*4)) * Tsym + 138 - (((2*14)*8 + 22 + 95)/96)*Tsym + 139 - DEFAULT_SIFSTIME*3); 140 - } else { 141 - /* DSSS 142 - * data transmit time + 2 ACK + 3 SIFS 143 - * Rate : ??Mega bps 144 - * ACK frame length = 14 bytes 145 - * TODO : */ 146 - if (pT01->T01_plcp_header_length) /* long preamble */ 147 - Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*3; 148 - else 149 - Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*3; 150 - 151 - Duration += (((NextBodyLen + (2*14))*8 152 - + Rate-1) / Rate + 153 - DEFAULT_SIFSTIME*3); 154 - } 155 - /* 4 USHOR for skip 8B USB, 2USHORT=FC + Duration */ 156 - ((u16 *)buffer)[5] = cpu_to_le16(Duration); 157 - 158 - /* ----20061009 add by anson's endian */ 159 - pNextT00->value = cpu_to_le32(pNextT00->value); 160 - pT01->value = cpu_to_le32(pT01->value); 161 - /* ----end 20061009 add by anson's endian */ 162 - 163 - buffer += OffsetSize; 164 - pT01 = (struct T01_descriptor *)(buffer+4); 165 - /* The last fragment will not have the next fragment */ 166 - if (i != 1) 167 - pNextT00 = (struct T00_descriptor *)(buffer+OffsetSize); 168 - } 169 - 170 - /******************************************* 171 - * Fill the last fragment descriptor 172 - *******************************************/ 173 - if (pT01->T01_modulation_type) { 174 - /* OFDM 175 - * 1 SIFS + 1 ACK 176 - * Rate : 24 Mega bps 177 - * ACK frame length = 14 bytes */ 178 - Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION; 179 - /* The Tx rate of ACK use 24M */ 180 - Duration += (((112 + 22 + 95)/96)*Tsym + 181 - DEFAULT_SIFSTIME); 182 - } else { 183 - /* DSSS 184 - * 1 ACK + 1 SIFS 185 - * Rate : ?? Mega bps 186 - * ACK frame length = 14 bytes(112 bits) */ 187 - if (pT01->T01_plcp_header_length) /* long preamble */ 188 - Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME; 189 - else 190 - Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME; 191 - 192 - Duration += ((112 + Rate-1)/Rate + DEFAULT_SIFSTIME); 193 - } 194 - } 195 - 196 - /* 4 USHOR for skip 8B USB, 2USHORT=FC + Duration */ 197 - ((u16 *)buffer)[5] = cpu_to_le16(Duration); 198 - pT00->value = cpu_to_le32(pT00->value); 199 - pT01->value = cpu_to_le32(pT01->value); 200 - /* --end 20061009 add */ 201 - 202 - } 203 - 204 - /* The function return the 4n size of usb pk */ 205 - static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, 206 - struct wb35_descriptor *pDes, u8 *TargetBuffer) 207 - { 208 - struct T00_descriptor *pT00; 209 - struct wb35_mds *pMds = &adapter->Mds; 210 - u8 *buffer; 211 - u8 *src_buffer; 212 - u8 *pctmp; 213 - u16 Size = 0; 214 - u16 SizeLeft, CopySize, CopyLeft, stmp; 215 - u8 buf_index, FragmentCount = 0; 216 - 217 - 218 - /* Copy fragment body */ 219 - buffer = TargetBuffer; /* shift 8B usb + 24B 802.11 */ 220 - SizeLeft = pDes->buffer_total_size; 221 - buf_index = pDes->buffer_start_index; 222 - 223 - pT00 = (struct T00_descriptor *)buffer; 224 - while (SizeLeft) { 225 - pT00 = (struct T00_descriptor *)buffer; 226 - CopySize = SizeLeft; 227 - if (SizeLeft > pDes->FragmentThreshold) { 228 - CopySize = pDes->FragmentThreshold; 229 - /* Set USB length */ 230 - pT00->T00_frame_length = 24 + CopySize; 231 - } else /* Set USB length */ 232 - pT00->T00_frame_length = 24 + SizeLeft; 233 - 234 - SizeLeft -= CopySize; 235 - 236 - /* 1 Byte operation */ 237 - pctmp = (u8 *)(buffer + 8 + DOT_11_SEQUENCE_OFFSET); 238 - *pctmp &= 0xf0; 239 - *pctmp |= FragmentCount; /* 931130.5.m */ 240 - if (!FragmentCount) 241 - pT00->T00_first_mpdu = 1; 242 - 243 - buffer += 32; /* 8B usb + 24B 802.11 header */ 244 - Size += 32; 245 - 246 - /* Copy into buffer */ 247 - stmp = CopySize + 3; 248 - stmp &= ~0x03; /* 4n Alignment */ 249 - Size += stmp; /* Current 4n offset of mpdu */ 250 - 251 - while (CopySize) { 252 - /* Copy body */ 253 - src_buffer = pDes->buffer_address[buf_index]; 254 - CopyLeft = CopySize; 255 - if (CopySize >= pDes->buffer_size[buf_index]) { 256 - CopyLeft = pDes->buffer_size[buf_index]; 257 - 258 - /* Get the next buffer of descriptor */ 259 - buf_index++; 260 - buf_index %= MAX_DESCRIPTOR_BUFFER_INDEX; 261 - } else { 262 - u8 *pctmp = pDes->buffer_address[buf_index]; 263 - pctmp += CopySize; 264 - pDes->buffer_address[buf_index] = pctmp; 265 - pDes->buffer_size[buf_index] -= CopySize; 266 - } 267 - 268 - memcpy(buffer, src_buffer, CopyLeft); 269 - buffer += CopyLeft; 270 - CopySize -= CopyLeft; 271 - } 272 - 273 - /* 931130.5.n */ 274 - if (pMds->MicAdd) { 275 - if (!SizeLeft) { 276 - pMds->MicWriteAddress[pMds->MicWriteIndex] = 277 - buffer - pMds->MicAdd; 278 - pMds->MicWriteSize[pMds->MicWriteIndex] = 279 - pMds->MicAdd; 280 - pMds->MicAdd = 0; 281 - } else if (SizeLeft < 8) { /* 931130.5.p */ 282 - pMds->MicAdd = SizeLeft; 283 - pMds->MicWriteAddress[pMds->MicWriteIndex] = 284 - buffer - (8 - SizeLeft); 285 - pMds->MicWriteSize[pMds->MicWriteIndex] = 286 - 8 - SizeLeft; 287 - pMds->MicWriteIndex++; 288 - } 289 - } 290 - 291 - /* Does it need to generate the new header for next mpdu? */ 292 - if (SizeLeft) { 293 - /* Get the next 4n start address */ 294 - buffer = TargetBuffer + Size; 295 - /* Copy 8B USB +24B 802.11 */ 296 - memcpy(buffer, TargetBuffer, 32); 297 - pT00 = (struct T00_descriptor *)buffer; 298 - pT00->T00_first_mpdu = 0; 299 - } 300 - 301 - FragmentCount++; 302 - } 303 - 304 - pT00->T00_last_mpdu = 1; 305 - pT00->T00_IsLastMpdu = 1; 306 - buffer = (u8 *)pT00 + 8; /* +8 for USB hdr */ 307 - buffer[1] &= ~0x04; /* Clear more frag bit of 802.11 frame control */ 308 - /* Update the correct fragment number */ 309 - pDes->FragmentCount = FragmentCount; 310 - return Size; 311 - } 312 - 313 - static void Mds_HeaderCopy(struct wbsoft_priv *adapter, 314 - struct wb35_descriptor *pDes, u8 *TargetBuffer) 315 - { 316 - struct wb35_mds *pMds = &adapter->Mds; 317 - u8 *src_buffer = pDes->buffer_address[0]; /* 931130.5.g */ 318 - struct T00_descriptor *pT00; 319 - struct T01_descriptor *pT01; 320 - u16 stmp; 321 - u8 i, ctmp1, ctmp2, ctmpf; 322 - u16 FragmentThreshold = CURRENT_FRAGMENT_THRESHOLD; 323 - 324 - 325 - stmp = pDes->buffer_total_size; 326 - /* 327 - * Set USB header 8 byte 328 - */ 329 - pT00 = (struct T00_descriptor *)TargetBuffer; 330 - TargetBuffer += 4; 331 - pT01 = (struct T01_descriptor *)TargetBuffer; 332 - TargetBuffer += 4; 333 - 334 - pT00->value = 0; /* Clear */ 335 - pT01->value = 0; /* Clear */ 336 - 337 - pT00->T00_tx_packet_id = pDes->Descriptor_ID; /* Set packet ID */ 338 - pT00->T00_header_length = 24; /* Set header length */ 339 - pT01->T01_retry_abort_enable = 1; /* 921013 931130.5.h */ 340 - 341 - /* Key ID setup */ 342 - pT01->T01_wep_id = 0; 343 - 344 - FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; /* Do not fragment */ 345 - /* Copy full data, the 1'st buffer contain all the data 931130.5.j */ 346 - /* Copy header */ 347 - memcpy(TargetBuffer, src_buffer, DOT_11_MAC_HEADER_SIZE); 348 - pDes->buffer_address[0] = src_buffer + DOT_11_MAC_HEADER_SIZE; 349 - pDes->buffer_total_size -= DOT_11_MAC_HEADER_SIZE; 350 - pDes->buffer_size[0] = pDes->buffer_total_size; 351 - 352 - /* Set fragment threshold */ 353 - FragmentThreshold -= (DOT_11_MAC_HEADER_SIZE + 4); 354 - pDes->FragmentThreshold = FragmentThreshold; 355 - 356 - /* Set more frag bit */ 357 - TargetBuffer[1] |= 0x04; /* Set more frag bit */ 358 - 359 - /* 360 - * Set tx rate 361 - */ 362 - stmp = *(u16 *)(TargetBuffer+30); /* 2n alignment address */ 363 - 364 - /* Use basic rate */ 365 - ctmp1 = ctmpf = CURRENT_TX_RATE_FOR_MNG; 366 - 367 - pDes->TxRate = ctmp1; 368 - pr_debug("Tx rate =%x\n", ctmp1); 369 - 370 - pT01->T01_modulation_type = (ctmp1%3) ? 0 : 1; 371 - 372 - for (i = 0; i < 2; i++) { 373 - if (i == 1) 374 - ctmp1 = ctmpf; 375 - /* backup the ta rate and fall back rate */ 376 - pMds->TxRate[pDes->Descriptor_ID][i] = ctmp1; 377 - 378 - if (ctmp1 == 108) 379 - ctmp2 = 7; 380 - else if (ctmp1 == 96) 381 - ctmp2 = 6; /* Rate convert for USB */ 382 - else if (ctmp1 == 72) 383 - ctmp2 = 5; 384 - else if (ctmp1 == 48) 385 - ctmp2 = 4; 386 - else if (ctmp1 == 36) 387 - ctmp2 = 3; 388 - else if (ctmp1 == 24) 389 - ctmp2 = 2; 390 - else if (ctmp1 == 18) 391 - ctmp2 = 1; 392 - else if (ctmp1 == 12) 393 - ctmp2 = 0; 394 - else if (ctmp1 == 22) 395 - ctmp2 = 3; 396 - else if (ctmp1 == 11) 397 - ctmp2 = 2; 398 - else if (ctmp1 == 4) 399 - ctmp2 = 1; 400 - else 401 - ctmp2 = 0; /* if( ctmp1 == 2 ) or default */ 402 - 403 - if (i == 0) 404 - pT01->T01_transmit_rate = ctmp2; 405 - else 406 - pT01->T01_fall_back_rate = ctmp2; 407 - } 408 - 409 - /* 410 - * Set preamble type 411 - */ 412 - /* RATE_1M */ 413 - if ((pT01->T01_modulation_type == 0) && (pT01->T01_transmit_rate == 0)) 414 - pDes->PreambleMode = WLAN_PREAMBLE_TYPE_LONG; 415 - else 416 - pDes->PreambleMode = CURRENT_PREAMBLE_MODE; 417 - pT01->T01_plcp_header_length = pDes->PreambleMode; /* Set preamble */ 418 - 419 - } 420 - 421 - static void MLME_GetNextPacket(struct wbsoft_priv *adapter, 422 - struct wb35_descriptor *desc) 423 - { 424 - desc->InternalUsed = desc->buffer_start_index + desc->buffer_number; 425 - desc->InternalUsed %= MAX_DESCRIPTOR_BUFFER_INDEX; 426 - desc->buffer_address[desc->InternalUsed] = adapter->sMlmeFrame.pMMPDU; 427 - desc->buffer_size[desc->InternalUsed] = adapter->sMlmeFrame.len; 428 - desc->buffer_total_size += adapter->sMlmeFrame.len; 429 - desc->buffer_number++; 430 - desc->Type = adapter->sMlmeFrame.data_type; 431 - } 432 - 433 - static void MLMEfreeMMPDUBuffer(struct wbsoft_priv *adapter, s8 *pData) 434 - { 435 - int i; 436 - 437 - /* Reclaim the data buffer */ 438 - for (i = 0; i < MAX_NUM_TX_MMPDU; i++) { 439 - if (pData == (s8 *)&(adapter->sMlmeFrame.TxMMPDU[i])) 440 - break; 441 - } 442 - if (adapter->sMlmeFrame.TxMMPDUInUse[i]) 443 - adapter->sMlmeFrame.TxMMPDUInUse[i] = false; 444 - else { 445 - /* Something wrong 446 - PD43 Add debug code here??? */ 447 - } 448 - } 449 - 450 - static void MLME_SendComplete(struct wbsoft_priv *adapter, u8 PacketID, 451 - unsigned char SendOK) 452 - { 453 - /* Reclaim the data buffer */ 454 - adapter->sMlmeFrame.len = 0; 455 - MLMEfreeMMPDUBuffer(adapter, adapter->sMlmeFrame.pMMPDU); 456 - 457 - /* Return resource */ 458 - adapter->sMlmeFrame.is_in_used = PACKET_FREE_TO_USE; 459 - } 460 - 461 - void 462 - Mds_Tx(struct wbsoft_priv *adapter) 463 - { 464 - struct hw_data *pHwData = &adapter->sHwData; 465 - struct wb35_mds *pMds = &adapter->Mds; 466 - struct wb35_descriptor TxDes; 467 - struct wb35_descriptor *pTxDes = &TxDes; 468 - u8 *XmitBufAddress; 469 - u16 XmitBufSize, PacketSize, stmp, CurrentSize, FragmentThreshold; 470 - u8 FillIndex, TxDesIndex, FragmentCount, FillCount; 471 - unsigned char BufferFilled = false; 472 - 473 - 474 - if (pMds->TxPause) 475 - return; 476 - if (!hal_driver_init_OK(pHwData)) 477 - return; 478 - 479 - /* Only one thread can be run here */ 480 - if (atomic_inc_return(&pMds->TxThreadCount) != 1) 481 - goto cleanup; 482 - 483 - /* Start to fill the data */ 484 - do { 485 - FillIndex = pMds->TxFillIndex; 486 - /* Is owned by software 0:Yes 1:No */ 487 - if (pMds->TxOwner[FillIndex]) { 488 - pr_debug("[Mds_Tx] Tx Owner is H/W.\n"); 489 - break; 490 - } 491 - 492 - /* Get buffer */ 493 - XmitBufAddress = pMds->pTxBuffer + (MAX_USB_TX_BUFFER * FillIndex); 494 - XmitBufSize = 0; 495 - FillCount = 0; 496 - do { 497 - PacketSize = adapter->sMlmeFrame.len; 498 - if (!PacketSize) 499 - break; 500 - 501 - /* For Check the buffer resource */ 502 - FragmentThreshold = CURRENT_FRAGMENT_THRESHOLD; 503 - /* 931130.5.b */ 504 - FragmentCount = PacketSize/FragmentThreshold + 1; 505 - /* 931130.5.c 8:MIC */ 506 - stmp = PacketSize + FragmentCount*32 + 8; 507 - if ((XmitBufSize + stmp) >= MAX_USB_TX_BUFFER) 508 - break; /* buffer is not enough */ 509 - 510 - /* 511 - * Start transmitting 512 - */ 513 - BufferFilled = true; 514 - 515 - /* Leaves first u8 intact */ 516 - memset((u8 *)pTxDes + 1, 0, sizeof(struct wb35_descriptor) - 1); 517 - 518 - TxDesIndex = pMds->TxDesIndex; /* Get the current ID */ 519 - pTxDes->Descriptor_ID = TxDesIndex; 520 - /* Storing the information of source coming from */ 521 - pMds->TxDesFrom[TxDesIndex] = 2; 522 - pMds->TxDesIndex++; 523 - pMds->TxDesIndex %= MAX_USB_TX_DESCRIPTOR; 524 - 525 - MLME_GetNextPacket(adapter, pTxDes); 526 - 527 - /* 528 - * Copy header. 8byte USB + 24byte 802.11Hdr. 529 - * Set TxRate, Preamble type 530 - */ 531 - Mds_HeaderCopy(adapter, pTxDes, XmitBufAddress); 532 - 533 - /* For speed up Key setting */ 534 - if (pTxDes->EapFix) { 535 - pr_debug("35: EPA 4th frame detected. Size = %d\n", 536 - PacketSize); 537 - pHwData->IsKeyPreSet = 1; 538 - } 539 - 540 - /* Copy (fragment) frame body, and set USB, 802.11 hdr flag */ 541 - CurrentSize = Mds_BodyCopy(adapter, pTxDes, XmitBufAddress); 542 - 543 - /* Set RTS/CTS and Normal duration field into buffer */ 544 - Mds_DurationSet(adapter, pTxDes, XmitBufAddress); 545 - 546 - /* Shift to the next address */ 547 - XmitBufSize += CurrentSize; 548 - XmitBufAddress += CurrentSize; 549 - 550 - /* Get packet to transmit completed, 551 - * 1:TESTSTA 2:MLME 3: Ndis data 552 - */ 553 - MLME_SendComplete(adapter, 0, true); 554 - 555 - /* Software TSC count 20060214 */ 556 - pMds->TxTsc++; 557 - if (pMds->TxTsc == 0) 558 - pMds->TxTsc_2++; 559 - 560 - FillCount++; /* 20060928 */ 561 - /* 562 - * End of multiple MSDU copy loop. 563 - * false = single 564 - * true = multiple sending 565 - */ 566 - } while (HAL_USB_MODE_BURST(pHwData)); 567 - 568 - /* Move to the next one, if necessary */ 569 - if (BufferFilled) { 570 - /* size setting */ 571 - pMds->TxBufferSize[FillIndex] = XmitBufSize; 572 - 573 - /* 20060928 set Tx count */ 574 - pMds->TxCountInBuffer[FillIndex] = FillCount; 575 - 576 - /* Set owner flag */ 577 - pMds->TxOwner[FillIndex] = 1; 578 - 579 - pMds->TxFillIndex++; 580 - pMds->TxFillIndex %= MAX_USB_TX_BUFFER_NUMBER; 581 - BufferFilled = false; 582 - } else 583 - break; 584 - 585 - if (!PacketSize) /* No more pk for transmitting */ 586 - break; 587 - 588 - } while (true); 589 - 590 - /* 591 - * Start to send by lower module 592 - */ 593 - if (!pHwData->IsKeyPreSet) 594 - Wb35Tx_start(adapter); 595 - 596 - cleanup: 597 - atomic_dec(&pMds->TxThreadCount); 598 - } 599 - 600 - void 601 - Mds_SendComplete(struct wbsoft_priv *adapter, struct T02_descriptor *pT02) 602 - { 603 - struct wb35_mds *pMds = &adapter->Mds; 604 - struct hw_data *pHwData = &adapter->sHwData; 605 - u8 PacketId = (u8)pT02->T02_Tx_PktID; 606 - unsigned char SendOK = true; 607 - u8 RetryCount, TxRate; 608 - 609 - if (pT02->T02_IgnoreResult) /* Don't care about the result */ 610 - return; 611 - if (pT02->T02_IsLastMpdu) { 612 - /* TODO: DTO -- get the retry count and fragment count */ 613 - /* Tx rate */ 614 - TxRate = pMds->TxRate[PacketId][0]; 615 - RetryCount = (u8)pT02->T02_MPDU_Cnt; 616 - if (pT02->value & FLAG_ERROR_TX_MASK) { 617 - SendOK = false; 618 - 619 - if (pT02->T02_transmit_abort || pT02->T02_out_of_MaxTxMSDULiftTime) { 620 - /* retry error */ 621 - pHwData->dto_tx_retry_count += (RetryCount+1); 622 - /* [for tx debug] */ 623 - if (RetryCount < 7) 624 - pHwData->tx_retry_count[RetryCount] += RetryCount; 625 - else 626 - pHwData->tx_retry_count[7] += RetryCount; 627 - pr_debug("dto_tx_retry_count =%d\n", 628 - pHwData->dto_tx_retry_count); 629 - MTO_SetTxCount(adapter, TxRate, RetryCount); 630 - } 631 - pHwData->dto_tx_frag_count += (RetryCount+1); 632 - 633 - /* [for tx debug] */ 634 - if (pT02->T02_transmit_abort_due_to_TBTT) 635 - pHwData->tx_TBTT_start_count++; 636 - if (pT02->T02_transmit_without_encryption_due_to_wep_on_false) 637 - pHwData->tx_WepOn_false_count++; 638 - if (pT02->T02_discard_due_to_null_wep_key) 639 - pHwData->tx_Null_key_count++; 640 - } else { 641 - if (pT02->T02_effective_transmission_rate) 642 - pHwData->tx_ETR_count++; 643 - MTO_SetTxCount(adapter, TxRate, RetryCount); 644 - } 645 - 646 - /* Clear send result buffer */ 647 - pMds->TxResult[PacketId] = 0; 648 - } else 649 - pMds->TxResult[PacketId] |= ((u16)(pT02->value & 0x0ffff)); 650 - }
-22
drivers/staging/winbond/mds_f.h
··· 1 - #ifndef __WINBOND_MDS_F_H 2 - #define __WINBOND_MDS_F_H 3 - 4 - #include "wbhal.h" 5 - #include "core.h" 6 - 7 - unsigned char Mds_initial(struct wbsoft_priv *adapter); 8 - void Mds_Tx(struct wbsoft_priv *adapter); 9 - void Mds_SendComplete(struct wbsoft_priv *adapter, struct T02_descriptor *pt02); 10 - void Mds_MpduProcess(struct wbsoft_priv *adapter, 11 - struct wb35_descriptor *prxdes); 12 - 13 - /* For data frame sending */ 14 - u16 MDS_GetPacketSize(struct wbsoft_priv *adapter); 15 - void MDS_GetNextPacket(struct wbsoft_priv *adapter, 16 - struct wb35_descriptor *pdes); 17 - void MDS_GetNextPacketComplete(struct wbsoft_priv *adapter, 18 - struct wb35_descriptor *pdes); 19 - void MDS_SendResult(struct wbsoft_priv *adapter, u8 packetid, 20 - unsigned char sendok); 21 - 22 - #endif
-130
drivers/staging/winbond/mds_s.h
··· 1 - #ifndef __WINBOND_MDS_H 2 - #define __WINBOND_MDS_H 3 - 4 - #include <linux/timer.h> 5 - #include <linux/types.h> 6 - #include <linux/atomic.h> 7 - 8 - #include "localpara.h" 9 - #include "mac_structures.h" 10 - 11 - /* Preamble_Type, see <SFS-802.11G-MIB-203> */ 12 - enum { 13 - WLAN_PREAMBLE_TYPE_SHORT, 14 - WLAN_PREAMBLE_TYPE_LONG, 15 - }; 16 - 17 - /*****************************************************************************/ 18 - #define MAX_USB_TX_DESCRIPTOR 15 /* IS89C35 ability */ 19 - #define MAX_USB_TX_BUFFER_NUMBER 4 /* Virtual pre-buffer number of MAX_USB_TX_BUFFER */ 20 - #define MAX_USB_TX_BUFFER 4096 /* IS89C35 ability 4n alignment is required for hardware */ 21 - 22 - #define AUTH_REQUEST_PAIRWISE_ERROR 0 /* _F flag setting */ 23 - #define AUTH_REQUEST_GROUP_ERROR 1 /* _F flag setting */ 24 - 25 - #define CURRENT_FRAGMENT_THRESHOLD (adapter->Mds.TxFragmentThreshold & ~0x1) 26 - #define CURRENT_PREAMBLE_MODE (psLOCAL->boShortPreamble ? WLAN_PREAMBLE_TYPE_SHORT : WLAN_PREAMBLE_TYPE_LONG) 27 - #define CURRENT_TX_RATE_FOR_MNG (adapter->sLocalPara.CurrentTxRateForMng) 28 - #define CURRENT_PROTECT_MECHANISM (psLOCAL->boProtectMechanism) 29 - #define CURRENT_RTS_THRESHOLD (adapter->Mds.TxRTSThreshold) 30 - 31 - #define MIB_GS_XMIT_OK_INC (adapter->sLocalPara.GS_XMIT_OK++) 32 - #define MIB_GS_RCV_OK_INC (adapter->sLocalPara.GS_RCV_OK++) 33 - #define MIB_GS_XMIT_ERROR_INC (adapter->sLocalPara.GS_XMIT_ERROR) 34 - 35 - /* ---------- TX ----------------------------------- */ 36 - #define ETHERNET_TX_DESCRIPTORS MAX_USB_TX_BUFFER_NUMBER 37 - 38 - /* ---------- RX ----------------------------------- */ 39 - #define ETHERNET_RX_DESCRIPTORS 8 /* It's not necessary to allocate more than 2 in sync indicate */ 40 - 41 - /* 42 - * ================================================================ 43 - * Configuration default value 44 - * ================================================================ 45 - */ 46 - #define DEFAULT_MULTICASTLISTMAX 32 /* standard */ 47 - #define DEFAULT_TX_BURSTLENGTH 3 /* 32 Longwords */ 48 - #define DEFAULT_RX_BURSTLENGTH 3 /* 32 Longwords */ 49 - #define DEFAULT_TX_THRESHOLD 0 /* Full Packet */ 50 - #define DEFAULT_RX_THRESHOLD 0 /* Full Packet */ 51 - #define DEFAULT_MAXTXRATE 6 /* 11 Mbps (Long) */ 52 - #define DEFAULT_CHANNEL 3 /* Chennel 3 */ 53 - #define DEFAULT_RTSThreshold 2347 /* Disable RTS */ 54 - #define DEFAULT_PME 0 /* Disable */ 55 - #define DEFAULT_SIFSTIME 10 56 - #define DEFAULT_ACKTIME_1ML 304 /* 148 + 44 + 112 */ 57 - #define DEFAULT_ACKTIME_2ML 248 /* 148 + 44 + 56 */ 58 - #define DEFAULT_FRAGMENT_THRESHOLD 2346 /* No fragment */ 59 - #define DEFAULT_PREAMBLE_LENGTH 72 60 - #define DEFAULT_PLCPHEADERTIME_LENGTH 24 61 - 62 - /* 63 - * ------------------------------------------------------------------------ 64 - * 0.96 sec since time unit of the R03 for the current, W89C32 is about 60ns 65 - * instead of 960 ns. This shall be fixed in the future W89C32 66 - * ------------------------------------------------------------------------- 67 - */ 68 - #define DEFAULT_MAX_RECEIVE_TIME 16440000 69 - 70 - #define RX_BUF_SIZE 2352 /* 600 - For 301 must be multiple of 8 */ 71 - #define MAX_RX_DESCRIPTORS 18 /* Rx Layer 2 */ 72 - 73 - /* For brand-new rx system */ 74 - #define MDS_ID_IGNORE ETHERNET_RX_DESCRIPTORS 75 - 76 - /* For Tx Packet status classify */ 77 - #define PACKET_FREE_TO_USE 0 78 - #define PACKET_COME_FROM_NDIS 0x08 79 - #define PACKET_COME_FROM_MLME 0x80 80 - #define PACKET_SEND_COMPLETE 0xff 81 - 82 - struct wb35_mds { 83 - /* For Tx usage */ 84 - u8 TxOwner[((MAX_USB_TX_BUFFER_NUMBER + 3) & ~0x03)]; 85 - u8 *pTxBuffer; 86 - u16 TxBufferSize[((MAX_USB_TX_BUFFER_NUMBER + 1) & ~0x01)]; 87 - u8 TxDesFrom[((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03)];/* 1: MLME 2: NDIS control 3: NDIS data */ 88 - u8 TxCountInBuffer[((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03)]; 89 - 90 - u8 TxFillIndex; /* the next index of TxBuffer can be used */ 91 - u8 TxDesIndex; /* The next index of TxDes can be used */ 92 - u8 ScanTxPause; /* data Tx pause because the scanning is progressing, but probe request Tx won't. */ 93 - u8 TxPause; /*For pause the Mds_Tx modult */ 94 - 95 - atomic_t TxThreadCount; /* For thread counting */ 96 - 97 - u16 TxResult[((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01)];/* Collect the sending result of Mpdu */ 98 - 99 - u8 MicRedundant[8]; /* For tmp use */ 100 - u8 *MicWriteAddress[2]; /* The start address to fill the Mic, use 2 point due to Mic maybe fragment */ 101 - 102 - u16 MicWriteSize[2]; 103 - 104 - u16 MicAdd; /* If want to add the Mic, this variable equal to 8 */ 105 - u16 MicWriteIndex; /* The number of MicWriteAddress */ 106 - 107 - u8 TxRate[((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01)][2]; /* [0] current tx rate, [1] fall back rate */ 108 - u8 TxInfo[((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01)]; /*Store information for callback function */ 109 - 110 - /* ---- for Tx Parameter */ 111 - u16 TxFragmentThreshold; /* For frame body only */ 112 - u16 TxRTSThreshold; 113 - 114 - u32 MaxReceiveTime; 115 - 116 - /* depend on OS, */ 117 - u32 MulticastListNo; 118 - u32 PacketFilter; /* Setting by NDIS, the current packet filter in use. */ 119 - u8 MulticastAddressesArray[DEFAULT_MULTICASTLISTMAX][MAC_ADDR_LENGTH]; 120 - 121 - /* COUNTERMEASURE */ 122 - u8 bMICfailCount; 123 - u8 boCounterMeasureBlock; 124 - u8 reserved_4[2]; 125 - 126 - u32 TxTsc; 127 - u32 TxTsc_2; 128 - }; 129 - 130 - #endif
-167
drivers/staging/winbond/mto.c
··· 1 - /* 2 - * ============================================================================ 3 - * MTO.C - 4 - * 5 - * Description: 6 - * MAC Throughput Optimization for W89C33 802.11g WLAN STA. 7 - * 8 - * The following MIB attributes or internal variables will be affected 9 - * while the MTO is being executed: 10 - * dot11FragmentationThreshold, 11 - * dot11RTSThreshold, 12 - * transmission rate and PLCP preamble type, 13 - * CCA mode, 14 - * antenna diversity. 15 - * 16 - * Copyright (c) 2003 Winbond Electronics Corp. All rights reserved. 17 - * ============================================================================ 18 - */ 19 - 20 - #include "sme_api.h" 21 - #include "wbhal.h" 22 - #include "wb35reg_f.h" 23 - #include "core.h" 24 - #include "mto.h" 25 - 26 - /* Declare SQ3 to rate and fragmentation threshold table */ 27 - /* Declare fragmentation threshold table */ 28 - #define MTO_MAX_FRAG_TH_LEVELS 5 29 - #define MTO_MAX_DATA_RATE_LEVELS 12 30 - 31 - u16 MTO_Frag_Th_Tbl[MTO_MAX_FRAG_TH_LEVELS] = { 32 - 256, 384, 512, 768, 1536 33 - }; 34 - 35 - /* 36 - * Declare data rate table: 37 - * The following table will be changed at anytime if the operation rate 38 - * supported by AP don't match the table 39 - */ 40 - static u8 MTO_Data_Rate_Tbl[MTO_MAX_DATA_RATE_LEVELS] = { 41 - 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 42 - }; 43 - 44 - /* this record the retry rate at different data rate */ 45 - static int retryrate_rec[MTO_MAX_DATA_RATE_LEVELS]; 46 - 47 - static u8 boSparseTxTraffic; 48 - 49 - /* 50 - * =========================================================================== 51 - * MTO_Init -- 52 - * 53 - * Description: 54 - * Initialize MTO parameters. 55 - * 56 - * This function should be invoked during system initialization. 57 - * 58 - * Arguments: 59 - * adapter - The pointer to the Miniport adapter Context 60 - * =========================================================================== 61 - */ 62 - void MTO_Init(struct wbsoft_priv *adapter) 63 - { 64 - int i; 65 - 66 - MTO_PREAMBLE_TYPE() = MTO_PREAMBLE_SHORT; /* for test */ 67 - 68 - MTO_CNT_ANT(0) = 0; 69 - MTO_CNT_ANT(1) = 0; 70 - MTO_SQ_ANT(0) = 0; 71 - MTO_SQ_ANT(1) = 0; 72 - 73 - MTO_AGING_TIMEOUT() = 0; 74 - 75 - /* The following parameters should be initialized to the values set by user */ 76 - MTO_RATE_LEVEL() = 0; 77 - MTO_FRAG_TH_LEVEL() = 4; 78 - MTO_RTS_THRESHOLD() = MTO_FRAG_TH() + 1; 79 - MTO_RTS_THRESHOLD_SETUP() = MTO_FRAG_TH() + 1; 80 - MTO_RATE_CHANGE_ENABLE() = 1; 81 - MTO_FRAG_CHANGE_ENABLE() = 0; 82 - MTO_POWER_CHANGE_ENABLE() = 1; 83 - MTO_PREAMBLE_CHANGE_ENABLE() = 1; 84 - MTO_RTS_CHANGE_ENABLE() = 0; 85 - 86 - for (i = 0; i < MTO_MAX_DATA_RATE_LEVELS; i++) 87 - retryrate_rec[i] = 5; 88 - 89 - MTO_TXFLOWCOUNT() = 0; 90 - /* --------- DTO threshold parameters ------------- */ 91 - MTOPARA_PERIODIC_CHECK_CYCLE() = 10; 92 - MTOPARA_RSSI_TH_FOR_ANTDIV() = 10; 93 - MTOPARA_TXCOUNT_TH_FOR_CALC_RATE() = 50; 94 - MTOPARA_TXRATE_INC_TH() = 10; 95 - MTOPARA_TXRATE_DEC_TH() = 30; 96 - MTOPARA_TXRATE_EQ_TH() = 40; 97 - MTOPARA_TXRATE_BACKOFF() = 12; 98 - MTOPARA_TXRETRYRATE_REDUCE() = 6; 99 - if (MTO_TXPOWER_FROM_EEPROM == 0xff) { 100 - switch (MTO_HAL()->phy_type) { 101 - case RF_AIROHA_2230: 102 - case RF_AIROHA_2230S: 103 - MTOPARA_TXPOWER_INDEX() = 46; /* MAX-8 @@ Only for AL 2230 */ 104 - break; 105 - case RF_AIROHA_7230: 106 - MTOPARA_TXPOWER_INDEX() = 49; 107 - break; 108 - case RF_WB_242: 109 - MTOPARA_TXPOWER_INDEX() = 10; 110 - break; 111 - case RF_WB_242_1: 112 - MTOPARA_TXPOWER_INDEX() = 24; 113 - break; 114 - } 115 - } else { /* follow the setting from EEPROM */ 116 - MTOPARA_TXPOWER_INDEX() = MTO_TXPOWER_FROM_EEPROM; 117 - } 118 - RFSynthesizer_SetPowerIndex(MTO_HAL(), (u8) MTOPARA_TXPOWER_INDEX()); 119 - /* ------------------------------------------------ */ 120 - 121 - /* For RSSI turning -- Cancel load from EEPROM */ 122 - MTO_DATA().RSSI_high = -41; 123 - MTO_DATA().RSSI_low = -60; 124 - } 125 - 126 - /* =========================================================================== 127 - * Description: 128 - * If we enable DTO, we will ignore the tx count with different tx rate 129 - * from DTO rate. This is because when we adjust DTO tx rate, there could 130 - * be some packets in the tx queue with previous tx rate 131 - */ 132 - 133 - void MTO_SetTxCount(struct wbsoft_priv *adapter, u8 tx_rate, u8 index) 134 - { 135 - MTO_TXFLOWCOUNT()++; 136 - if ((MTO_ENABLE == 1) && (MTO_RATE_CHANGE_ENABLE() == 1)) { 137 - if (tx_rate == MTO_DATA_RATE()) { 138 - if (index == 0) { 139 - if (boSparseTxTraffic) 140 - MTO_HAL()->dto_tx_frag_count += MTOPARA_PERIODIC_CHECK_CYCLE(); 141 - else 142 - MTO_HAL()->dto_tx_frag_count += 1; 143 - } else { 144 - if (index < 8) { 145 - MTO_HAL()->dto_tx_retry_count += index; 146 - MTO_HAL()->dto_tx_frag_count += (index + 1); 147 - } else { 148 - MTO_HAL()->dto_tx_retry_count += 7; 149 - MTO_HAL()->dto_tx_frag_count += 7; 150 - } 151 - } 152 - } else if (MTO_DATA_RATE() > 48 && tx_rate == 48) { 153 - /* for reducing data rate scheme, do not calculate different data rate. 3 is the reducing data rate at retry. */ 154 - if (index < 3) { 155 - MTO_HAL()->dto_tx_retry_count += index; 156 - MTO_HAL()->dto_tx_frag_count += (index + 1); 157 - } else { 158 - MTO_HAL()->dto_tx_retry_count += 3; 159 - MTO_HAL()->dto_tx_frag_count += 3; 160 - } 161 - 162 - } 163 - } else { 164 - MTO_HAL()->dto_tx_retry_count += index; 165 - MTO_HAL()->dto_tx_frag_count += (index + 1); 166 - } 167 - }
-134
drivers/staging/winbond/mto.h
··· 1 - /* 2 - * ================================================================== 3 - * MTO.H 4 - * 5 - * Copyright (c) 2003 Winbond Electronics Corp. All rights reserved. 6 - * ================================================================== 7 - */ 8 - #ifndef __MTO_H__ 9 - #define __MTO_H__ 10 - 11 - #include <linux/types.h> 12 - 13 - struct wbsoft_priv; 14 - 15 - #define MTO_PREAMBLE_LONG WLAN_PREAMBLE_TYPE_LONG 16 - #define MTO_PREAMBLE_SHORT WLAN_PREAMBLE_TYPE_SHORT 17 - 18 - /* Defines the parameters used in the MAC Throughput Optimization algorithm */ 19 - struct wb35_mto_params { 20 - u32 TxFlowCount; /* to judge what kind the tx flow(sparse or busy) is */ 21 - 22 - /* --------- DTO threshold parameters ------------- */ 23 - u16 DTO_PeriodicCheckCycle; 24 - u16 DTO_RssiThForAntDiv; 25 - 26 - u16 DTO_TxCountThForCalcNewRate; 27 - u16 DTO_TxRateIncTh; 28 - 29 - u16 DTO_TxRateDecTh; 30 - u16 DTO_TxRateEqTh; 31 - 32 - u16 DTO_TxRateBackOff; 33 - u16 DTO_TxRetryRateReduce; 34 - 35 - u16 DTO_TxPowerIndex; /* 0 ~ 31 */ 36 - u16 reserved_1; 37 - /* ------------------------------------------------ */ 38 - 39 - u8 PowerChangeEnable; 40 - u8 AntDiversityEnable; 41 - u8 CCA_Mode; 42 - u8 CCA_Mode_Setup; 43 - u8 Preamble_Type; 44 - u8 PreambleChangeEnable; 45 - 46 - u8 DataRateLevel; 47 - u8 DataRateChangeEnable; 48 - u8 FragThresholdLevel; 49 - u8 FragThresholdChangeEnable; 50 - 51 - u16 RTSThreshold; 52 - u16 RTSThreshold_Setup; 53 - 54 - u32 AvgIdleSlot; 55 - u32 Pr_Interf; 56 - u32 AvgGapBtwnInterf; 57 - 58 - u8 RTSChangeEnable; 59 - u8 Ant_sel; 60 - u8 aging_timeout; 61 - u8 reserved_2; 62 - 63 - u32 Cnt_Ant[2]; 64 - u32 SQ_Ant[2]; 65 - 66 - u8 FallbackRateLevel; 67 - u8 OfdmRateLevel; 68 - 69 - u8 RatePolicy; 70 - u8 reserved_3[3]; 71 - 72 - /* For RSSI turning */ 73 - s32 RSSI_high; 74 - s32 RSSI_low; 75 - }; 76 - 77 - 78 - #define MTO_DATA() (adapter->sMtoPara) 79 - #define MTO_HAL() (&adapter->sHwData) 80 - #define MTO_SET_PREAMBLE_TYPE(x) /* Turbo mark LM_PREAMBLE_TYPE(&pcore_data->lm_data) = (x) */ 81 - #define MTO_ENABLE (adapter->sLocalPara.TxRateMode == RATE_AUTO) 82 - #define MTO_TXPOWER_FROM_EEPROM (adapter->sHwData.PowerIndexFromEEPROM) 83 - #define LOCAL_ANTENNA_NO() (adapter->sLocalPara.bAntennaNo) 84 - #define LOCAL_IS_CONNECTED() (adapter->sLocalPara.wConnectedSTAindex != 0) 85 - #define MTO_INITTXRATE_MODE (adapter->sHwData.SoftwareSet&0x2) /* bit 1 */ 86 - 87 - #define MTO_POWER_CHANGE_ENABLE() MTO_DATA().PowerChangeEnable 88 - #define MTO_CCA_MODE() MTO_DATA().CCA_Mode 89 - #define MTO_CCA_MODE_SETUP() MTO_DATA().CCA_Mode_Setup 90 - #define MTO_PREAMBLE_TYPE() MTO_DATA().Preamble_Type 91 - #define MTO_PREAMBLE_CHANGE_ENABLE() MTO_DATA().PreambleChangeEnable 92 - 93 - #define MTO_RATE_LEVEL() MTO_DATA().DataRateLevel 94 - #define MTO_OFDM_RATE_LEVEL() MTO_DATA().OfdmRateLevel 95 - #define MTO_RATE_CHANGE_ENABLE() MTO_DATA().DataRateChangeEnable 96 - #define MTO_FRAG_TH_LEVEL() MTO_DATA().FragThresholdLevel 97 - #define MTO_FRAG_CHANGE_ENABLE() MTO_DATA().FragThresholdChangeEnable 98 - #define MTO_RTS_THRESHOLD() MTO_DATA().RTSThreshold 99 - #define MTO_RTS_CHANGE_ENABLE() MTO_DATA().RTSChangeEnable 100 - #define MTO_RTS_THRESHOLD_SETUP() MTO_DATA().RTSThreshold_Setup 101 - 102 - #define MTO_AVG_IDLE_SLOT() MTO_DATA().AvgIdleSlot 103 - #define MTO_PR_INTERF() MTO_DATA().Pr_Interf 104 - #define MTO_AVG_GAP_BTWN_INTERF() MTO_DATA().AvgGapBtwnInterf 105 - 106 - #define MTO_CNT_ANT(x) MTO_DATA().Cnt_Ant[(x)] 107 - #define MTO_SQ_ANT(x) MTO_DATA().SQ_Ant[(x)] 108 - #define MTO_AGING_TIMEOUT() MTO_DATA().aging_timeout 109 - 110 - #define MTO_TXFLOWCOUNT() MTO_DATA().TxFlowCount 111 - 112 - /* --------- DTO threshold parameters ------------- */ 113 - #define MTOPARA_PERIODIC_CHECK_CYCLE() MTO_DATA().DTO_PeriodicCheckCycle 114 - #define MTOPARA_RSSI_TH_FOR_ANTDIV() MTO_DATA().DTO_RssiThForAntDiv 115 - #define MTOPARA_TXCOUNT_TH_FOR_CALC_RATE() MTO_DATA().DTO_TxCountThForCalcNewRate 116 - #define MTOPARA_TXRATE_INC_TH() MTO_DATA().DTO_TxRateIncTh 117 - #define MTOPARA_TXRATE_DEC_TH() MTO_DATA().DTO_TxRateDecTh 118 - #define MTOPARA_TXRATE_EQ_TH() MTO_DATA().DTO_TxRateEqTh 119 - #define MTOPARA_TXRATE_BACKOFF() MTO_DATA().DTO_TxRateBackOff 120 - #define MTOPARA_TXRETRYRATE_REDUCE() MTO_DATA().DTO_TxRetryRateReduce 121 - #define MTOPARA_TXPOWER_INDEX() MTO_DATA().DTO_TxPowerIndex 122 - /* ------------------------------------------------ */ 123 - 124 - 125 - extern u16 MTO_Frag_Th_Tbl[]; 126 - 127 - #define MTO_DATA_RATE() MTO_Data_Rate_Tbl[MTO_RATE_LEVEL()] 128 - #define MTO_FRAG_TH() MTO_Frag_Th_Tbl[MTO_FRAG_TH_LEVEL()] 129 - 130 - void MTO_Init(struct wbsoft_priv *); 131 - void MTO_SetTxCount(struct wbsoft_priv *adapter, u8 t0, u8 index); 132 - 133 - #endif /* __MTO_H__ */ 134 -
-1317
drivers/staging/winbond/phy_calibration.c
··· 1 - /* 2 - * phy_302_calibration.c 3 - * 4 - * Copyright (C) 2002, 2005 Winbond Electronics Corp. 5 - * 6 - * modification history 7 - * --------------------------------------------------------------------------- 8 - * 0.01.001, 2003-04-16, Kevin created 9 - * 10 - */ 11 - 12 - /****************** INCLUDE FILES SECTION ***********************************/ 13 - #include "phy_calibration.h" 14 - #include "wbhal.h" 15 - #include "wb35reg_f.h" 16 - #include "core.h" 17 - 18 - 19 - /****************** DEBUG CONSTANT AND MACRO SECTION ************************/ 20 - 21 - /****************** LOCAL CONSTANT AND MACRO SECTION ************************/ 22 - #define LOOP_TIMES 20 23 - #define US 1000/* MICROSECOND*/ 24 - 25 - #define AG_CONST 0.6072529350 26 - #define FIXED(X) ((s32)((X) * 32768.0)) 27 - #define DEG2RAD(X) (0.017453 * (X)) 28 - 29 - static const s32 Angles[] = { 30 - FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), 31 - FIXED(DEG2RAD(14.0362)), FIXED(DEG2RAD(7.12502)), 32 - FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)), 33 - FIXED(DEG2RAD(0.895174)), FIXED(DEG2RAD(0.447614)), 34 - FIXED(DEG2RAD(0.223811)), FIXED(DEG2RAD(0.111906)), 35 - FIXED(DEG2RAD(0.055953)), FIXED(DEG2RAD(0.027977)) 36 - }; 37 - 38 - /****************** LOCAL FUNCTION DECLARATION SECTION **********************/ 39 - 40 - /* 41 - * void _phy_rf_write_delay(struct hw_data *phw_data); 42 - * void phy_init_rf(struct hw_data *phw_data); 43 - */ 44 - 45 - /****************** FUNCTION DEFINITION SECTION *****************************/ 46 - 47 - static s32 _s13_to_s32(u32 data) 48 - { 49 - u32 val; 50 - 51 - val = (data & 0x0FFF); 52 - 53 - if ((data & BIT(12)) != 0) 54 - val |= 0xFFFFF000; 55 - 56 - return (s32) val; 57 - } 58 - 59 - /****************************************************************************/ 60 - static s32 _s4_to_s32(u32 data) 61 - { 62 - s32 val; 63 - 64 - val = (data & 0x0007); 65 - 66 - if ((data & BIT(3)) != 0) 67 - val |= 0xFFFFFFF8; 68 - 69 - return val; 70 - } 71 - 72 - static u32 _s32_to_s4(s32 data) 73 - { 74 - u32 val; 75 - 76 - if (data > 7) 77 - data = 7; 78 - else if (data < -8) 79 - data = -8; 80 - 81 - val = data & 0x000F; 82 - 83 - return val; 84 - } 85 - 86 - /****************************************************************************/ 87 - static s32 _s5_to_s32(u32 data) 88 - { 89 - s32 val; 90 - 91 - val = (data & 0x000F); 92 - 93 - if ((data & BIT(4)) != 0) 94 - val |= 0xFFFFFFF0; 95 - 96 - return val; 97 - } 98 - 99 - static u32 _s32_to_s5(s32 data) 100 - { 101 - u32 val; 102 - 103 - if (data > 15) 104 - data = 15; 105 - else if (data < -16) 106 - data = -16; 107 - 108 - val = data & 0x001F; 109 - 110 - return val; 111 - } 112 - 113 - /****************************************************************************/ 114 - static s32 _s6_to_s32(u32 data) 115 - { 116 - s32 val; 117 - 118 - val = (data & 0x001F); 119 - 120 - if ((data & BIT(5)) != 0) 121 - val |= 0xFFFFFFE0; 122 - 123 - return val; 124 - } 125 - 126 - static u32 _s32_to_s6(s32 data) 127 - { 128 - u32 val; 129 - 130 - if (data > 31) 131 - data = 31; 132 - else if (data < -32) 133 - data = -32; 134 - 135 - val = data & 0x003F; 136 - 137 - return val; 138 - } 139 - 140 - /****************************************************************************/ 141 - static s32 _floor(s32 n) 142 - { 143 - if (n > 0) 144 - n += 5; 145 - else 146 - n -= 5; 147 - 148 - return n/10; 149 - } 150 - 151 - /****************************************************************************/ 152 - /* 153 - * The following code is sqare-root function. 154 - * sqsum is the input and the output is sq_rt; 155 - * The maximum of sqsum = 2^27 -1; 156 - */ 157 - static u32 _sqrt(u32 sqsum) 158 - { 159 - u32 sq_rt; 160 - 161 - int g0, g1, g2, g3, g4; 162 - int seed; 163 - int next; 164 - int step; 165 - 166 - g4 = sqsum / 100000000; 167 - g3 = (sqsum - g4*100000000) / 1000000; 168 - g2 = (sqsum - g4*100000000 - g3*1000000) / 10000; 169 - g1 = (sqsum - g4*100000000 - g3*1000000 - g2*10000) / 100; 170 - g0 = (sqsum - g4*100000000 - g3*1000000 - g2*10000 - g1*100); 171 - 172 - next = g4; 173 - step = 0; 174 - seed = 0; 175 - while (((seed+1)*(step+1)) <= next) { 176 - step++; 177 - seed++; 178 - } 179 - 180 - sq_rt = seed * 10000; 181 - next = (next-(seed*step))*100 + g3; 182 - 183 - step = 0; 184 - seed = 2 * seed * 10; 185 - while (((seed+1)*(step+1)) <= next) { 186 - step++; 187 - seed++; 188 - } 189 - 190 - sq_rt = sq_rt + step * 1000; 191 - next = (next - seed * step) * 100 + g2; 192 - seed = (seed + step) * 10; 193 - step = 0; 194 - while (((seed+1)*(step+1)) <= next) { 195 - step++; 196 - seed++; 197 - } 198 - 199 - sq_rt = sq_rt + step * 100; 200 - next = (next - seed * step) * 100 + g1; 201 - seed = (seed + step) * 10; 202 - step = 0; 203 - 204 - while (((seed+1)*(step+1)) <= next) { 205 - step++; 206 - seed++; 207 - } 208 - 209 - sq_rt = sq_rt + step * 10; 210 - next = (next - seed * step) * 100 + g0; 211 - seed = (seed + step) * 10; 212 - step = 0; 213 - 214 - while (((seed+1)*(step+1)) <= next) { 215 - step++; 216 - seed++; 217 - } 218 - 219 - sq_rt = sq_rt + step; 220 - 221 - return sq_rt; 222 - } 223 - 224 - /****************************************************************************/ 225 - static void _sin_cos(s32 angle, s32 *sin, s32 *cos) 226 - { 227 - s32 X, Y, TargetAngle, CurrAngle; 228 - unsigned Step; 229 - 230 - X = FIXED(AG_CONST); /* AG_CONST * cos(0) */ 231 - Y = 0; /* AG_CONST * sin(0) */ 232 - TargetAngle = abs(angle); 233 - CurrAngle = 0; 234 - 235 - for (Step = 0; Step < 12; Step++) { 236 - s32 NewX; 237 - 238 - if (TargetAngle > CurrAngle) { 239 - NewX = X - (Y >> Step); 240 - Y = (X >> Step) + Y; 241 - X = NewX; 242 - CurrAngle += Angles[Step]; 243 - } else { 244 - NewX = X + (Y >> Step); 245 - Y = -(X >> Step) + Y; 246 - X = NewX; 247 - CurrAngle -= Angles[Step]; 248 - } 249 - } 250 - 251 - if (angle > 0) { 252 - *cos = X; 253 - *sin = Y; 254 - } else { 255 - *cos = X; 256 - *sin = -Y; 257 - } 258 - } 259 - 260 - static unsigned char hal_get_dxx_reg(struct hw_data *pHwData, u16 number, 261 - u32 *pValue) 262 - { 263 - if (number < 0x1000) 264 - number += 0x1000; 265 - return Wb35Reg_ReadSync(pHwData, number, pValue); 266 - } 267 - #define hw_get_dxx_reg(_A, _B, _C) hal_get_dxx_reg(_A, _B, (u32 *)_C) 268 - 269 - static unsigned char hal_set_dxx_reg(struct hw_data *pHwData, u16 number, 270 - u32 value) 271 - { 272 - unsigned char ret; 273 - 274 - if (number < 0x1000) 275 - number += 0x1000; 276 - ret = Wb35Reg_WriteSync(pHwData, number, value); 277 - return ret; 278 - } 279 - #define hw_set_dxx_reg(_A, _B, _C) hal_set_dxx_reg(_A, _B, (u32)_C) 280 - 281 - 282 - static void _reset_rx_cal(struct hw_data *phw_data) 283 - { 284 - u32 val; 285 - 286 - hw_get_dxx_reg(phw_data, 0x54, &val); 287 - 288 - if (phw_data->revision == 0x2002) /* 1st-cut */ 289 - val &= 0xFFFF0000; 290 - else /* 2nd-cut */ 291 - val &= 0x000003FF; 292 - 293 - hw_set_dxx_reg(phw_data, 0x54, val); 294 - } 295 - 296 - 297 - /**************for winbond calibration*********/ 298 - 299 - 300 - 301 - /**********************************************/ 302 - static void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency) 303 - { 304 - u32 reg_agc_ctrl3; 305 - u32 reg_a_acq_ctrl; 306 - u32 reg_b_acq_ctrl; 307 - u32 val; 308 - 309 - PHY_DEBUG(("[CAL] -> [1]_rxadc_dc_offset_cancellation()\n")); 310 - phy_init_rf(phw_data); 311 - 312 - /* set calibration channel */ 313 - if ((RF_WB_242 == phw_data->phy_type) || 314 - (RF_WB_242_1 == phw_data->phy_type)) /* 20060619.5 Add */{ 315 - if ((frequency >= 2412) && (frequency <= 2484)) { 316 - /* w89rf242 change frequency to 2390Mhz */ 317 - PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n")); 318 - phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); 319 - 320 - } 321 - } else { 322 - 323 - } 324 - 325 - /* reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel */ 326 - hw_get_dxx_reg(phw_data, 0x5C, &val); 327 - val &= ~(0x03FF); 328 - hw_set_dxx_reg(phw_data, 0x5C, val); 329 - 330 - /* reset the TX and RX IQ calibration data */ 331 - hw_set_dxx_reg(phw_data, 0x3C, 0); 332 - hw_set_dxx_reg(phw_data, 0x54, 0); 333 - 334 - hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */ 335 - 336 - /* a. Disable AGC */ 337 - hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3); 338 - reg_agc_ctrl3 &= ~BIT(2); 339 - reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 340 - hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 341 - 342 - hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val); 343 - val |= MASK_AGC_FIX_GAIN; 344 - hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); 345 - 346 - /* b. Turn off BB RX */ 347 - hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, &reg_a_acq_ctrl); 348 - reg_a_acq_ctrl |= MASK_AMER_OFF_REG; 349 - hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl); 350 - 351 - hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, &reg_b_acq_ctrl); 352 - reg_b_acq_ctrl |= MASK_BMER_OFF_REG; 353 - hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl); 354 - 355 - /* c. Make sure MAC is in receiving mode 356 - * d. Turn ON ADC calibration 357 - * - ADC calibrator is triggered by this signal rising from 0 to 1 */ 358 - hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); 359 - val &= ~MASK_ADC_DC_CAL_STR; 360 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); 361 - 362 - val |= MASK_ADC_DC_CAL_STR; 363 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); 364 - 365 - /* e. The results are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]" */ 366 - #ifdef _DEBUG 367 - hw_get_dxx_reg(phw_data, REG_OFFSET_READ, &val); 368 - PHY_DEBUG(("[CAL] REG_OFFSET_READ = 0x%08X\n", val)); 369 - 370 - PHY_DEBUG(("[CAL] ** adc_dc_cal_i = %d (0x%04X)\n", 371 - _s9_to_s32(val&0x000001FF), val&0x000001FF)); 372 - PHY_DEBUG(("[CAL] ** adc_dc_cal_q = %d (0x%04X)\n", 373 - _s9_to_s32((val&0x0003FE00)>>9), 374 - (val&0x0003FE00)>>9)); 375 - #endif 376 - 377 - hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); 378 - val &= ~MASK_ADC_DC_CAL_STR; 379 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); 380 - 381 - /* f. Turn on BB RX */ 382 - /* hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, &reg_a_acq_ctrl); */ 383 - reg_a_acq_ctrl &= ~MASK_AMER_OFF_REG; 384 - hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl); 385 - 386 - /* hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, &reg_b_acq_ctrl); */ 387 - reg_b_acq_ctrl &= ~MASK_BMER_OFF_REG; 388 - hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl); 389 - 390 - /* g. Enable AGC */ 391 - /* hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); */ 392 - reg_agc_ctrl3 |= BIT(2); 393 - reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 394 - hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 395 - } 396 - 397 - /* 20060612.1.a 20060718.1 Modify */ 398 - static u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, 399 - s32 a_2_threshold, 400 - s32 b_2_threshold) 401 - { 402 - u32 reg_mode_ctrl; 403 - s32 iq_mag_0_tx; 404 - s32 iqcal_tone_i0; 405 - s32 iqcal_tone_q0; 406 - s32 iqcal_tone_i; 407 - s32 iqcal_tone_q; 408 - u32 sqsum; 409 - s32 rot_i_b; 410 - s32 rot_q_b; 411 - s32 tx_cal_flt_b[4]; 412 - s32 tx_cal[4]; 413 - s32 tx_cal_reg[4]; 414 - s32 a_2, b_2; 415 - s32 sin_b, sin_2b; 416 - s32 cos_b, cos_2b; 417 - s32 divisor; 418 - s32 temp1, temp2; 419 - u32 val; 420 - u16 loop; 421 - s32 iqcal_tone_i_avg, iqcal_tone_q_avg; 422 - u8 verify_count; 423 - int capture_time; 424 - 425 - PHY_DEBUG(("[CAL] -> _tx_iq_calibration_loop()\n")); 426 - PHY_DEBUG(("[CAL] ** a_2_threshold = %d\n", a_2_threshold)); 427 - PHY_DEBUG(("[CAL] ** b_2_threshold = %d\n", b_2_threshold)); 428 - 429 - verify_count = 0; 430 - 431 - hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 432 - PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); 433 - 434 - loop = LOOP_TIMES; 435 - 436 - while (loop > 0) { 437 - PHY_DEBUG(("[CAL] [%d.] <_tx_iq_calibration_loop>\n", 438 - (LOOP_TIMES-loop+1))); 439 - 440 - iqcal_tone_i_avg = 0; 441 - iqcal_tone_q_avg = 0; 442 - if (!hw_set_dxx_reg(phw_data, 0x3C, 0x00)) /* 20060718.1 modify */ 443 - return 0; 444 - for (capture_time = 0; capture_time < 10; capture_time++) { 445 - /* 446 - * a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" 447 - * to 0x1 to enable "IQ calibration Mode II" 448 - */ 449 - reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); 450 - reg_mode_ctrl &= ~MASK_IQCAL_MODE; 451 - reg_mode_ctrl |= (MASK_CALIB_START|0x02); 452 - reg_mode_ctrl |= (MASK_CALIB_START|0x02|2<<2); 453 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 454 - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 455 - 456 - /* b. */ 457 - hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); 458 - PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); 459 - 460 - iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF); 461 - iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13); 462 - PHY_DEBUG(("[CAL] ** iqcal_tone_i0=%d, iqcal_tone_q0=%d\n", 463 - iqcal_tone_i0, iqcal_tone_q0)); 464 - 465 - sqsum = iqcal_tone_i0*iqcal_tone_i0 + 466 - iqcal_tone_q0*iqcal_tone_q0; 467 - iq_mag_0_tx = (s32) _sqrt(sqsum); 468 - PHY_DEBUG(("[CAL] ** iq_mag_0_tx=%d\n", iq_mag_0_tx)); 469 - 470 - /* c. Set "calib_start" to 0x0 */ 471 - reg_mode_ctrl &= ~MASK_CALIB_START; 472 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 473 - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 474 - 475 - /* 476 - * d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" 477 - * to 0x1 to enable "IQ calibration Mode II" 478 - */ 479 - /* hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); */ 480 - hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 481 - reg_mode_ctrl &= ~MASK_IQCAL_MODE; 482 - reg_mode_ctrl |= (MASK_CALIB_START|0x03); 483 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 484 - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 485 - 486 - /* e. */ 487 - hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); 488 - PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); 489 - 490 - iqcal_tone_i = _s13_to_s32(val & 0x00001FFF); 491 - iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13); 492 - PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n", 493 - iqcal_tone_i, iqcal_tone_q)); 494 - if (capture_time == 0) 495 - continue; 496 - else { 497 - iqcal_tone_i_avg = (iqcal_tone_i_avg*(capture_time-1) + iqcal_tone_i)/capture_time; 498 - iqcal_tone_q_avg = (iqcal_tone_q_avg*(capture_time-1) + iqcal_tone_q)/capture_time; 499 - } 500 - } 501 - 502 - iqcal_tone_i = iqcal_tone_i_avg; 503 - iqcal_tone_q = iqcal_tone_q_avg; 504 - 505 - 506 - rot_i_b = (iqcal_tone_i * iqcal_tone_i0 + 507 - iqcal_tone_q * iqcal_tone_q0) / 1024; 508 - rot_q_b = (iqcal_tone_i * iqcal_tone_q0 * (-1) + 509 - iqcal_tone_q * iqcal_tone_i0) / 1024; 510 - PHY_DEBUG(("[CAL] ** rot_i_b = %d, rot_q_b = %d\n", 511 - rot_i_b, rot_q_b)); 512 - 513 - /* f. */ 514 - divisor = ((iq_mag_0_tx * iq_mag_0_tx * 2)/1024 - rot_i_b) * 2; 515 - 516 - if (divisor == 0) { 517 - PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n")); 518 - PHY_DEBUG(("[CAL] ** divisor=0 to calculate EPS and THETA !!\n")); 519 - PHY_DEBUG(("[CAL] ******************************************\n")); 520 - break; 521 - } 522 - 523 - a_2 = (rot_i_b * 32768) / divisor; 524 - b_2 = (rot_q_b * (-32768)) / divisor; 525 - PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2)); 526 - PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2)); 527 - 528 - phw_data->iq_rsdl_gain_tx_d2 = a_2; 529 - phw_data->iq_rsdl_phase_tx_d2 = b_2; 530 - 531 - /* if ((abs(a_2) < 150) && (abs(b_2) < 100)) */ 532 - /* if ((abs(a_2) < 200) && (abs(b_2) < 200)) */ 533 - if ((abs(a_2) < a_2_threshold) && (abs(b_2) < b_2_threshold)) { 534 - verify_count++; 535 - 536 - PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n")); 537 - PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count)); 538 - PHY_DEBUG(("[CAL] ******************************************\n")); 539 - 540 - if (verify_count > 2) { 541 - PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); 542 - PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION (EPS,THETA) OK !!\n")); 543 - PHY_DEBUG(("[CAL] **************************************\n")); 544 - return 0; 545 - } 546 - 547 - continue; 548 - } else 549 - verify_count = 0; 550 - 551 - _sin_cos(b_2, &sin_b, &cos_b); 552 - _sin_cos(b_2*2, &sin_2b, &cos_2b); 553 - PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b)); 554 - PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b)); 555 - 556 - if (cos_2b == 0) { 557 - PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n")); 558 - PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n")); 559 - PHY_DEBUG(("[CAL] ******************************************\n")); 560 - break; 561 - } 562 - 563 - /* 1280 * 32768 = 41943040 */ 564 - temp1 = (41943040/cos_2b)*cos_b; 565 - 566 - /* temp2 = (41943040/cos_2b)*sin_b*(-1); */ 567 - if (phw_data->revision == 0x2002) /* 1st-cut */ 568 - temp2 = (41943040/cos_2b)*sin_b*(-1); 569 - else /* 2nd-cut */ 570 - temp2 = (41943040*4/cos_2b)*sin_b*(-1); 571 - 572 - tx_cal_flt_b[0] = _floor(temp1/(32768+a_2)); 573 - tx_cal_flt_b[1] = _floor(temp2/(32768+a_2)); 574 - tx_cal_flt_b[2] = _floor(temp2/(32768-a_2)); 575 - tx_cal_flt_b[3] = _floor(temp1/(32768-a_2)); 576 - PHY_DEBUG(("[CAL] ** tx_cal_flt_b[0] = %d\n", tx_cal_flt_b[0])); 577 - PHY_DEBUG(("[CAL] tx_cal_flt_b[1] = %d\n", tx_cal_flt_b[1])); 578 - PHY_DEBUG(("[CAL] tx_cal_flt_b[2] = %d\n", tx_cal_flt_b[2])); 579 - PHY_DEBUG(("[CAL] tx_cal_flt_b[3] = %d\n", tx_cal_flt_b[3])); 580 - 581 - tx_cal[2] = tx_cal_flt_b[2]; 582 - tx_cal[2] = tx_cal[2] + 3; 583 - tx_cal[1] = tx_cal[2]; 584 - tx_cal[3] = tx_cal_flt_b[3] - 128; 585 - tx_cal[0] = -tx_cal[3] + 1; 586 - 587 - PHY_DEBUG(("[CAL] tx_cal[0] = %d\n", tx_cal[0])); 588 - PHY_DEBUG(("[CAL] tx_cal[1] = %d\n", tx_cal[1])); 589 - PHY_DEBUG(("[CAL] tx_cal[2] = %d\n", tx_cal[2])); 590 - PHY_DEBUG(("[CAL] tx_cal[3] = %d\n", tx_cal[3])); 591 - 592 - /* if ((tx_cal[0] == 0) && (tx_cal[1] == 0) && 593 - (tx_cal[2] == 0) && (tx_cal[3] == 0)) 594 - { */ 595 - /* PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n")); 596 - * PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION COMPLETE !!\n")); 597 - * PHY_DEBUG(("[CAL] ******************************************\n")); 598 - * return 0; 599 - } */ 600 - 601 - /* g. */ 602 - if (phw_data->revision == 0x2002) /* 1st-cut */{ 603 - hw_get_dxx_reg(phw_data, 0x54, &val); 604 - PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); 605 - tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28); 606 - tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24); 607 - tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20); 608 - tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16); 609 - } else /* 2nd-cut */{ 610 - hw_get_dxx_reg(phw_data, 0x3C, &val); 611 - PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val)); 612 - tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); 613 - tx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); 614 - tx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); 615 - tx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10); 616 - 617 - } 618 - 619 - PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg[0])); 620 - PHY_DEBUG(("[CAL] tx_cal_reg[1] = %d\n", tx_cal_reg[1])); 621 - PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2])); 622 - PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3])); 623 - 624 - if (phw_data->revision == 0x2002) /* 1st-cut */{ 625 - if (((tx_cal_reg[0] == 7) || (tx_cal_reg[0] == (-8))) && 626 - ((tx_cal_reg[3] == 7) || (tx_cal_reg[3] == (-8)))) { 627 - PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); 628 - PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n")); 629 - PHY_DEBUG(("[CAL] **************************************\n")); 630 - break; 631 - } 632 - } else /* 2nd-cut */{ 633 - if (((tx_cal_reg[0] == 31) || (tx_cal_reg[0] == (-32))) && 634 - ((tx_cal_reg[3] == 31) || (tx_cal_reg[3] == (-32)))) { 635 - PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); 636 - PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n")); 637 - PHY_DEBUG(("[CAL] **************************************\n")); 638 - break; 639 - } 640 - } 641 - 642 - tx_cal[0] = tx_cal[0] + tx_cal_reg[0]; 643 - tx_cal[1] = tx_cal[1] + tx_cal_reg[1]; 644 - tx_cal[2] = tx_cal[2] + tx_cal_reg[2]; 645 - tx_cal[3] = tx_cal[3] + tx_cal_reg[3]; 646 - PHY_DEBUG(("[CAL] ** apply tx_cal[0] = %d\n", tx_cal[0])); 647 - PHY_DEBUG(("[CAL] apply tx_cal[1] = %d\n", tx_cal[1])); 648 - PHY_DEBUG(("[CAL] apply tx_cal[2] = %d\n", tx_cal[2])); 649 - PHY_DEBUG(("[CAL] apply tx_cal[3] = %d\n", tx_cal[3])); 650 - 651 - if (phw_data->revision == 0x2002) /* 1st-cut */{ 652 - val &= 0x0000FFFF; 653 - val |= ((_s32_to_s4(tx_cal[0]) << 28)| 654 - (_s32_to_s4(tx_cal[1]) << 24)| 655 - (_s32_to_s4(tx_cal[2]) << 20)| 656 - (_s32_to_s4(tx_cal[3]) << 16)); 657 - hw_set_dxx_reg(phw_data, 0x54, val); 658 - PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val)); 659 - return 0; 660 - } else /* 2nd-cut */{ 661 - val &= 0x000003FF; 662 - val |= ((_s32_to_s5(tx_cal[0]) << 27)| 663 - (_s32_to_s6(tx_cal[1]) << 21)| 664 - (_s32_to_s6(tx_cal[2]) << 15)| 665 - (_s32_to_s5(tx_cal[3]) << 10)); 666 - hw_set_dxx_reg(phw_data, 0x3C, val); 667 - PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION = 0x%08X\n", val)); 668 - return 0; 669 - } 670 - 671 - /* i. Set "calib_start" to 0x0 */ 672 - reg_mode_ctrl &= ~MASK_CALIB_START; 673 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 674 - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 675 - 676 - loop--; 677 - } 678 - 679 - return 1; 680 - } 681 - 682 - static void _tx_iq_calibration_winbond(struct hw_data *phw_data) 683 - { 684 - u32 reg_agc_ctrl3; 685 - #ifdef _DEBUG 686 - s32 tx_cal_reg[4]; 687 - 688 - #endif 689 - u32 reg_mode_ctrl; 690 - u32 val; 691 - u8 result; 692 - 693 - PHY_DEBUG(("[CAL] -> [4]_tx_iq_calibration()\n")); 694 - 695 - /* 0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits */ 696 - phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); 697 - /* 0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit */ 698 - phy_set_rf_data(phw_data, 11, (11<<24)|0x19BDD6); /* 20060612.1.a 0x1905D6); */ 699 - /* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */ 700 - phy_set_rf_data(phw_data, 5, (5<<24)|0x24C60A); /* 0x24C60A (high temperature) */ 701 - /* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */ 702 - phy_set_rf_data(phw_data, 6, (6<<24)|0x34880C); /* 20060612.1.a 0x06890C); */ 703 - /* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */ 704 - phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); 705 - /* ; [BB-chip]: Calibration (6f).Send test pattern */ 706 - /* ; [BB-chip]: Calibration (6g). Search RXGCL optimal value */ 707 - /* ; [BB-chip]: Calibration (6h). Calculate TX-path IQ imbalance and setting TX path IQ compensation table */ 708 - /* phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); */ 709 - 710 - msleep(30); /* 20060612.1.a 30ms delay. Add the follow 2 lines */ 711 - /* To adjust TXVGA to fit iq_mag_0 range from 1250 ~ 1750 */ 712 - adjust_TXVGA_for_iq_mag(phw_data); 713 - 714 - /* a. Disable AGC */ 715 - hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3); 716 - reg_agc_ctrl3 &= ~BIT(2); 717 - reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 718 - hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 719 - 720 - hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val); 721 - val |= MASK_AGC_FIX_GAIN; 722 - hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); 723 - 724 - result = _tx_iq_calibration_loop_winbond(phw_data, 150, 100); 725 - 726 - if (result > 0) { 727 - if (phw_data->revision == 0x2002) /* 1st-cut */{ 728 - hw_get_dxx_reg(phw_data, 0x54, &val); 729 - val &= 0x0000FFFF; 730 - hw_set_dxx_reg(phw_data, 0x54, val); 731 - } else /* 2nd-cut*/{ 732 - hw_get_dxx_reg(phw_data, 0x3C, &val); 733 - val &= 0x000003FF; 734 - hw_set_dxx_reg(phw_data, 0x3C, val); 735 - } 736 - 737 - result = _tx_iq_calibration_loop_winbond(phw_data, 300, 200); 738 - 739 - if (result > 0) { 740 - if (phw_data->revision == 0x2002) /* 1st-cut */{ 741 - hw_get_dxx_reg(phw_data, 0x54, &val); 742 - val &= 0x0000FFFF; 743 - hw_set_dxx_reg(phw_data, 0x54, val); 744 - } else /* 2nd-cut*/{ 745 - hw_get_dxx_reg(phw_data, 0x3C, &val); 746 - val &= 0x000003FF; 747 - hw_set_dxx_reg(phw_data, 0x3C, val); 748 - } 749 - 750 - result = _tx_iq_calibration_loop_winbond(phw_data, 500, 400); 751 - if (result > 0) { 752 - if (phw_data->revision == 0x2002) /* 1st-cut */{ 753 - hw_get_dxx_reg(phw_data, 0x54, &val); 754 - val &= 0x0000FFFF; 755 - hw_set_dxx_reg(phw_data, 0x54, val); 756 - } else /* 2nd-cut */{ 757 - hw_get_dxx_reg(phw_data, 0x3C, &val); 758 - val &= 0x000003FF; 759 - hw_set_dxx_reg(phw_data, 0x3C, val); 760 - } 761 - 762 - 763 - result = _tx_iq_calibration_loop_winbond(phw_data, 700, 500); 764 - 765 - if (result > 0) { 766 - PHY_DEBUG(("[CAL] ** <_tx_iq_calibration> **************\n")); 767 - PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION FAILURE !!\n")); 768 - PHY_DEBUG(("[CAL] **************************************\n")); 769 - 770 - if (phw_data->revision == 0x2002) /* 1st-cut */{ 771 - hw_get_dxx_reg(phw_data, 0x54, &val); 772 - val &= 0x0000FFFF; 773 - hw_set_dxx_reg(phw_data, 0x54, val); 774 - } else /* 2nd-cut */{ 775 - hw_get_dxx_reg(phw_data, 0x3C, &val); 776 - val &= 0x000003FF; 777 - hw_set_dxx_reg(phw_data, 0x3C, val); 778 - } 779 - } 780 - } 781 - } 782 - } 783 - 784 - /* i. Set "calib_start" to 0x0 */ 785 - hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 786 - reg_mode_ctrl &= ~MASK_CALIB_START; 787 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 788 - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 789 - 790 - /* g. Enable AGC */ 791 - /* hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); */ 792 - reg_agc_ctrl3 |= BIT(2); 793 - reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 794 - hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 795 - 796 - #ifdef _DEBUG 797 - if (phw_data->revision == 0x2002) /* 1st-cut */{ 798 - hw_get_dxx_reg(phw_data, 0x54, &val); 799 - PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); 800 - tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28); 801 - tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24); 802 - tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20); 803 - tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16); 804 - } else /* 2nd-cut */ { 805 - hw_get_dxx_reg(phw_data, 0x3C, &val); 806 - PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val)); 807 - tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); 808 - tx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); 809 - tx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); 810 - tx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10); 811 - 812 - } 813 - 814 - PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg[0])); 815 - PHY_DEBUG(("[CAL] tx_cal_reg[1] = %d\n", tx_cal_reg[1])); 816 - PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2])); 817 - PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3])); 818 - #endif 819 - 820 - 821 - /* 822 - * for test - BEN 823 - * RF Control Override 824 - */ 825 - } 826 - 827 - /*****************************************************/ 828 - static u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency) 829 - { 830 - u32 reg_mode_ctrl; 831 - s32 iqcal_tone_i; 832 - s32 iqcal_tone_q; 833 - s32 iqcal_image_i; 834 - s32 iqcal_image_q; 835 - s32 rot_tone_i_b; 836 - s32 rot_tone_q_b; 837 - s32 rot_image_i_b; 838 - s32 rot_image_q_b; 839 - s32 rx_cal_flt_b[4]; 840 - s32 rx_cal[4]; 841 - s32 rx_cal_reg[4]; 842 - s32 a_2, b_2; 843 - s32 sin_b, sin_2b; 844 - s32 cos_b, cos_2b; 845 - s32 temp1, temp2; 846 - u32 val; 847 - u16 loop; 848 - 849 - u32 pwr_tone; 850 - u32 pwr_image; 851 - u8 verify_count; 852 - 853 - s32 iqcal_tone_i_avg, iqcal_tone_q_avg; 854 - s32 iqcal_image_i_avg, iqcal_image_q_avg; 855 - u16 capture_time; 856 - 857 - PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration_loop()\n")); 858 - PHY_DEBUG(("[CAL] ** factor = %d\n", factor)); 859 - 860 - hw_set_dxx_reg(phw_data, 0x58, 0x44444444); /* IQ_Alpha */ 861 - 862 - /* b. */ 863 - 864 - hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 865 - PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); 866 - 867 - verify_count = 0; 868 - 869 - /* for (loop = 0; loop < 1; loop++) */ 870 - /* for (loop = 0; loop < LOOP_TIMES; loop++) */ 871 - loop = LOOP_TIMES; 872 - while (loop > 0) { 873 - PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n", 874 - (LOOP_TIMES-loop+1))); 875 - iqcal_tone_i_avg = 0; 876 - iqcal_tone_q_avg = 0; 877 - iqcal_image_i_avg = 0; 878 - iqcal_image_q_avg = 0; 879 - capture_time = 0; 880 - 881 - for (capture_time = 0; capture_time < 10; capture_time++) { 882 - /* i. Set "calib_start" to 0x0 */ 883 - reg_mode_ctrl &= ~MASK_CALIB_START; 884 - if (!hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl))/*20060718.1 modify */ 885 - return 0; 886 - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 887 - 888 - reg_mode_ctrl &= ~MASK_IQCAL_MODE; 889 - reg_mode_ctrl |= (MASK_CALIB_START|0x1); 890 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 891 - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 892 - 893 - /* c. */ 894 - hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); 895 - PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); 896 - 897 - iqcal_tone_i = _s13_to_s32(val & 0x00001FFF); 898 - iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13); 899 - PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n", 900 - iqcal_tone_i, iqcal_tone_q)); 901 - 902 - hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); 903 - PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); 904 - 905 - iqcal_image_i = _s13_to_s32(val & 0x00001FFF); 906 - iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); 907 - PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n", 908 - iqcal_image_i, iqcal_image_q)); 909 - if (capture_time == 0) 910 - continue; 911 - else { 912 - iqcal_image_i_avg = (iqcal_image_i_avg*(capture_time-1) + iqcal_image_i)/capture_time; 913 - iqcal_image_q_avg = (iqcal_image_q_avg*(capture_time-1) + iqcal_image_q)/capture_time; 914 - iqcal_tone_i_avg = (iqcal_tone_i_avg*(capture_time-1) + iqcal_tone_i)/capture_time; 915 - iqcal_tone_q_avg = (iqcal_tone_q_avg*(capture_time-1) + iqcal_tone_q)/capture_time; 916 - } 917 - } 918 - 919 - 920 - iqcal_image_i = iqcal_image_i_avg; 921 - iqcal_image_q = iqcal_image_q_avg; 922 - iqcal_tone_i = iqcal_tone_i_avg; 923 - iqcal_tone_q = iqcal_tone_q_avg; 924 - 925 - /* d. */ 926 - rot_tone_i_b = (iqcal_tone_i * iqcal_tone_i + 927 - iqcal_tone_q * iqcal_tone_q) / 1024; 928 - rot_tone_q_b = (iqcal_tone_i * iqcal_tone_q * (-1) + 929 - iqcal_tone_q * iqcal_tone_i) / 1024; 930 - rot_image_i_b = (iqcal_image_i * iqcal_tone_i - 931 - iqcal_image_q * iqcal_tone_q) / 1024; 932 - rot_image_q_b = (iqcal_image_i * iqcal_tone_q + 933 - iqcal_image_q * iqcal_tone_i) / 1024; 934 - 935 - PHY_DEBUG(("[CAL] ** rot_tone_i_b = %d\n", rot_tone_i_b)); 936 - PHY_DEBUG(("[CAL] ** rot_tone_q_b = %d\n", rot_tone_q_b)); 937 - PHY_DEBUG(("[CAL] ** rot_image_i_b = %d\n", rot_image_i_b)); 938 - PHY_DEBUG(("[CAL] ** rot_image_q_b = %d\n", rot_image_q_b)); 939 - 940 - /* f. */ 941 - if (rot_tone_i_b == 0) { 942 - PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n")); 943 - PHY_DEBUG(("[CAL] ** rot_tone_i_b=0 to calculate EPS and THETA !!\n")); 944 - PHY_DEBUG(("[CAL] ******************************************\n")); 945 - break; 946 - } 947 - 948 - a_2 = (rot_image_i_b * 32768) / rot_tone_i_b - 949 - phw_data->iq_rsdl_gain_tx_d2; 950 - b_2 = (rot_image_q_b * 32768) / rot_tone_i_b - 951 - phw_data->iq_rsdl_phase_tx_d2; 952 - 953 - PHY_DEBUG(("[CAL] ** iq_rsdl_gain_tx_d2 = %d\n", 954 - phw_data->iq_rsdl_gain_tx_d2)); 955 - PHY_DEBUG(("[CAL] ** iq_rsdl_phase_tx_d2= %d\n", 956 - phw_data->iq_rsdl_phase_tx_d2)); 957 - PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2)); 958 - PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2)); 959 - 960 - _sin_cos(b_2, &sin_b, &cos_b); 961 - _sin_cos(b_2*2, &sin_2b, &cos_2b); 962 - PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b)); 963 - PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b)); 964 - 965 - if (cos_2b == 0) { 966 - PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n")); 967 - PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n")); 968 - PHY_DEBUG(("[CAL] ******************************************\n")); 969 - break; 970 - } 971 - 972 - /* 1280 * 32768 = 41943040 */ 973 - temp1 = (41943040/cos_2b)*cos_b; 974 - 975 - /* temp2 = (41943040/cos_2b)*sin_b*(-1); */ 976 - if (phw_data->revision == 0x2002)/* 1st-cut */ 977 - temp2 = (41943040/cos_2b)*sin_b*(-1); 978 - else/* 2nd-cut */ 979 - temp2 = (41943040*4/cos_2b)*sin_b*(-1); 980 - 981 - rx_cal_flt_b[0] = _floor(temp1/(32768+a_2)); 982 - rx_cal_flt_b[1] = _floor(temp2/(32768-a_2)); 983 - rx_cal_flt_b[2] = _floor(temp2/(32768+a_2)); 984 - rx_cal_flt_b[3] = _floor(temp1/(32768-a_2)); 985 - 986 - PHY_DEBUG(("[CAL] ** rx_cal_flt_b[0] = %d\n", rx_cal_flt_b[0])); 987 - PHY_DEBUG(("[CAL] rx_cal_flt_b[1] = %d\n", rx_cal_flt_b[1])); 988 - PHY_DEBUG(("[CAL] rx_cal_flt_b[2] = %d\n", rx_cal_flt_b[2])); 989 - PHY_DEBUG(("[CAL] rx_cal_flt_b[3] = %d\n", rx_cal_flt_b[3])); 990 - 991 - rx_cal[0] = rx_cal_flt_b[0] - 128; 992 - rx_cal[1] = rx_cal_flt_b[1]; 993 - rx_cal[2] = rx_cal_flt_b[2]; 994 - rx_cal[3] = rx_cal_flt_b[3] - 128; 995 - PHY_DEBUG(("[CAL] ** rx_cal[0] = %d\n", rx_cal[0])); 996 - PHY_DEBUG(("[CAL] rx_cal[1] = %d\n", rx_cal[1])); 997 - PHY_DEBUG(("[CAL] rx_cal[2] = %d\n", rx_cal[2])); 998 - PHY_DEBUG(("[CAL] rx_cal[3] = %d\n", rx_cal[3])); 999 - 1000 - /* e. */ 1001 - pwr_tone = (iqcal_tone_i*iqcal_tone_i + iqcal_tone_q*iqcal_tone_q); 1002 - pwr_image = (iqcal_image_i*iqcal_image_i + 1003 - iqcal_image_q*iqcal_image_q)*factor; 1004 - 1005 - PHY_DEBUG(("[CAL] ** pwr_tone = %d\n", pwr_tone)); 1006 - PHY_DEBUG(("[CAL] ** pwr_image = %d\n", pwr_image)); 1007 - 1008 - if (pwr_tone > pwr_image) { 1009 - verify_count++; 1010 - 1011 - PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *************\n")); 1012 - PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count)); 1013 - PHY_DEBUG(("[CAL] ******************************************\n")); 1014 - 1015 - if (verify_count > 2) { 1016 - PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); 1017 - PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION OK !!\n")); 1018 - PHY_DEBUG(("[CAL] **************************************\n")); 1019 - return 0; 1020 - } 1021 - 1022 - continue; 1023 - } 1024 - /* g. */ 1025 - hw_get_dxx_reg(phw_data, 0x54, &val); 1026 - PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); 1027 - 1028 - if (phw_data->revision == 0x2002) /* 1st-cut */{ 1029 - rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12); 1030 - rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8); 1031 - rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4); 1032 - rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F)); 1033 - } else /* 2nd-cut */{ 1034 - rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); 1035 - rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); 1036 - rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); 1037 - rx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10); 1038 - } 1039 - 1040 - PHY_DEBUG(("[CAL] ** rx_cal_reg[0] = %d\n", rx_cal_reg[0])); 1041 - PHY_DEBUG(("[CAL] rx_cal_reg[1] = %d\n", rx_cal_reg[1])); 1042 - PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2])); 1043 - PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3])); 1044 - 1045 - if (phw_data->revision == 0x2002) /* 1st-cut */{ 1046 - if (((rx_cal_reg[0] == 7) || (rx_cal_reg[0] == (-8))) && 1047 - ((rx_cal_reg[3] == 7) || (rx_cal_reg[3] == (-8)))) { 1048 - PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); 1049 - PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n")); 1050 - PHY_DEBUG(("[CAL] **************************************\n")); 1051 - break; 1052 - } 1053 - } else /* 2nd-cut */{ 1054 - if (((rx_cal_reg[0] == 31) || (rx_cal_reg[0] == (-32))) && 1055 - ((rx_cal_reg[3] == 31) || (rx_cal_reg[3] == (-32)))) { 1056 - PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); 1057 - PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n")); 1058 - PHY_DEBUG(("[CAL] **************************************\n")); 1059 - break; 1060 - } 1061 - } 1062 - 1063 - rx_cal[0] = rx_cal[0] + rx_cal_reg[0]; 1064 - rx_cal[1] = rx_cal[1] + rx_cal_reg[1]; 1065 - rx_cal[2] = rx_cal[2] + rx_cal_reg[2]; 1066 - rx_cal[3] = rx_cal[3] + rx_cal_reg[3]; 1067 - PHY_DEBUG(("[CAL] ** apply rx_cal[0] = %d\n", rx_cal[0])); 1068 - PHY_DEBUG(("[CAL] apply rx_cal[1] = %d\n", rx_cal[1])); 1069 - PHY_DEBUG(("[CAL] apply rx_cal[2] = %d\n", rx_cal[2])); 1070 - PHY_DEBUG(("[CAL] apply rx_cal[3] = %d\n", rx_cal[3])); 1071 - 1072 - hw_get_dxx_reg(phw_data, 0x54, &val); 1073 - if (phw_data->revision == 0x2002) /* 1st-cut */{ 1074 - val &= 0x0000FFFF; 1075 - val |= ((_s32_to_s4(rx_cal[0]) << 12)| 1076 - (_s32_to_s4(rx_cal[1]) << 8)| 1077 - (_s32_to_s4(rx_cal[2]) << 4)| 1078 - (_s32_to_s4(rx_cal[3]))); 1079 - hw_set_dxx_reg(phw_data, 0x54, val); 1080 - } else /* 2nd-cut */{ 1081 - val &= 0x000003FF; 1082 - val |= ((_s32_to_s5(rx_cal[0]) << 27)| 1083 - (_s32_to_s6(rx_cal[1]) << 21)| 1084 - (_s32_to_s6(rx_cal[2]) << 15)| 1085 - (_s32_to_s5(rx_cal[3]) << 10)); 1086 - hw_set_dxx_reg(phw_data, 0x54, val); 1087 - 1088 - if (loop == 3) 1089 - return 0; 1090 - } 1091 - PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val)); 1092 - 1093 - loop--; 1094 - } 1095 - 1096 - return 1; 1097 - } 1098 - 1099 - /*************************************************/ 1100 - 1101 - /***************************************************************/ 1102 - static void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency) 1103 - { 1104 - /* figo 20050523 marked this flag for can't compile for release */ 1105 - #ifdef _DEBUG 1106 - s32 rx_cal_reg[4]; 1107 - u32 val; 1108 - #endif 1109 - 1110 - u8 result; 1111 - 1112 - PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration()\n")); 1113 - /* a. Set RFIC to "RX calibration mode" */ 1114 - /* ; ----- Calibration (7). RX path IQ imbalance calibration loop */ 1115 - /* 0x01 0xFFBFC2 ; 3FEFF ; Calibration (7a). enable RX IQ calibration loop circuits */ 1116 - phy_set_rf_data(phw_data, 1, (1<<24)|0xEFBFC2); 1117 - /* 0x0B 0x1A01D6 ; 06817 ; Calibration (7b). enable RX I/Q cal loop SW1 circuits */ 1118 - phy_set_rf_data(phw_data, 11, (11<<24)|0x1A05D6); 1119 - /* 0x05 0x24848A ; 09212 ; Calibration (7c). setting TX-VGA gain (TXGCH) to 2 --> to be optimized */ 1120 - phy_set_rf_data(phw_data, 5, (5<<24) | phw_data->txvga_setting_for_cal); 1121 - /* 0x06 0x06840C ; 01A10 ; Calibration (7d). RXGCH=00; RXGCL=010 000 (RXVGA) --> to be optimized */ 1122 - phy_set_rf_data(phw_data, 6, (6<<24)|0x06834C); 1123 - /* 0x00 0xFFF1C0 ; 3F7C7 ; Calibration (7e). turn on IQ imbalance/Test mode */ 1124 - phy_set_rf_data(phw_data, 0, (0<<24)|0xFFF1C0); 1125 - 1126 - /* ; [BB-chip]: Calibration (7f). Send test pattern */ 1127 - /* ; [BB-chip]: Calibration (7g). Search RXGCL optimal value */ 1128 - /* ; [BB-chip]: Calibration (7h). Calculate RX-path IQ imbalance and setting RX path IQ compensation table */ 1129 - 1130 - result = _rx_iq_calibration_loop_winbond(phw_data, 12589, frequency); 1131 - 1132 - if (result > 0) { 1133 - _reset_rx_cal(phw_data); 1134 - result = _rx_iq_calibration_loop_winbond(phw_data, 7943, frequency); 1135 - 1136 - if (result > 0) { 1137 - _reset_rx_cal(phw_data); 1138 - result = _rx_iq_calibration_loop_winbond(phw_data, 5011, frequency); 1139 - 1140 - if (result > 0) { 1141 - PHY_DEBUG(("[CAL] ** <_rx_iq_calibration> **************\n")); 1142 - PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION FAILURE !!\n")); 1143 - PHY_DEBUG(("[CAL] **************************************\n")); 1144 - _reset_rx_cal(phw_data); 1145 - } 1146 - } 1147 - } 1148 - 1149 - #ifdef _DEBUG 1150 - hw_get_dxx_reg(phw_data, 0x54, &val); 1151 - PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); 1152 - 1153 - if (phw_data->revision == 0x2002) /* 1st-cut */{ 1154 - rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12); 1155 - rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8); 1156 - rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4); 1157 - rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F)); 1158 - } else /* 2nd-cut */{ 1159 - rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); 1160 - rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); 1161 - rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); 1162 - rx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10); 1163 - } 1164 - 1165 - PHY_DEBUG(("[CAL] ** rx_cal_reg[0] = %d\n", rx_cal_reg[0])); 1166 - PHY_DEBUG(("[CAL] rx_cal_reg[1] = %d\n", rx_cal_reg[1])); 1167 - PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2])); 1168 - PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3])); 1169 - #endif 1170 - 1171 - } 1172 - 1173 - /*******************************************************/ 1174 - void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency) 1175 - { 1176 - u32 reg_mode_ctrl; 1177 - u32 iq_alpha; 1178 - 1179 - PHY_DEBUG(("[CAL] -> phy_calibration_winbond()\n")); 1180 - 1181 - hw_get_dxx_reg(phw_data, 0x58, &iq_alpha); 1182 - 1183 - _rxadc_dc_offset_cancellation_winbond(phw_data, frequency); 1184 - /* _txidac_dc_offset_cancellation_winbond(phw_data); */ 1185 - /* _txqdac_dc_offset_cancellation_winbond(phw_data); */ 1186 - 1187 - _tx_iq_calibration_winbond(phw_data); 1188 - _rx_iq_calibration_winbond(phw_data, frequency); 1189 - 1190 - /*********************************************************************/ 1191 - hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 1192 - reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE|MASK_CALIB_START); /* set when finish */ 1193 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 1194 - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 1195 - 1196 - /* i. Set RFIC to "Normal mode" */ 1197 - hw_set_dxx_reg(phw_data, 0x58, iq_alpha); 1198 - 1199 - /*********************************************************************/ 1200 - phy_init_rf(phw_data); 1201 - 1202 - } 1203 - 1204 - /******************/ 1205 - void phy_set_rf_data(struct hw_data *pHwData, u32 index, u32 value) 1206 - { 1207 - u32 ltmp = 0; 1208 - 1209 - switch (pHwData->phy_type) { 1210 - case RF_MAXIM_2825: 1211 - case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */ 1212 - ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18); 1213 - break; 1214 - 1215 - case RF_MAXIM_2827: 1216 - ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18); 1217 - break; 1218 - 1219 - case RF_MAXIM_2828: 1220 - ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18); 1221 - break; 1222 - 1223 - case RF_MAXIM_2829: 1224 - ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18); 1225 - break; 1226 - 1227 - case RF_AIROHA_2230: 1228 - case RF_AIROHA_2230S: /* 20060420 Add this */ 1229 - ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(value, 20); 1230 - break; 1231 - 1232 - case RF_AIROHA_7230: 1233 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | (value&0xffffff); 1234 - break; 1235 - 1236 - case RF_WB_242: 1237 - case RF_WB_242_1:/* 20060619.5 Add */ 1238 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(value, 24); 1239 - break; 1240 - } 1241 - 1242 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1243 - } 1244 - 1245 - /* 20060717 modify as Bruce's mail */ 1246 - unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data) 1247 - { 1248 - int init_txvga = 0; 1249 - u32 reg_mode_ctrl; 1250 - u32 val; 1251 - s32 iqcal_tone_i0; 1252 - s32 iqcal_tone_q0; 1253 - u32 sqsum; 1254 - s32 iq_mag_0_tx; 1255 - u8 reg_state; 1256 - int current_txvga; 1257 - 1258 - 1259 - reg_state = 0; 1260 - for (init_txvga = 0; init_txvga < 10; init_txvga++) { 1261 - current_txvga = (0x24C40A|(init_txvga<<6)); 1262 - phy_set_rf_data(phw_data, 5, ((5<<24)|current_txvga)); 1263 - phw_data->txvga_setting_for_cal = current_txvga; 1264 - 1265 - msleep(30);/* 20060612.1.a */ 1266 - 1267 - if (!hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl))/* 20060718.1 modify */ 1268 - return false; 1269 - 1270 - PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); 1271 - 1272 - /* 1273 - * a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to 1274 - * enable "IQ alibration Mode II" 1275 - */ 1276 - reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); 1277 - reg_mode_ctrl &= ~MASK_IQCAL_MODE; 1278 - reg_mode_ctrl |= (MASK_CALIB_START|0x02); 1279 - reg_mode_ctrl |= (MASK_CALIB_START|0x02|2<<2); 1280 - hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 1281 - PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 1282 - 1283 - udelay(1);/* 20060612.1.a */ 1284 - 1285 - udelay(300);/* 20060612.1.a */ 1286 - 1287 - /* b. */ 1288 - hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); 1289 - 1290 - PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); 1291 - udelay(300);/* 20060612.1.a */ 1292 - 1293 - iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF); 1294 - iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13); 1295 - PHY_DEBUG(("[CAL] ** iqcal_tone_i0=%d, iqcal_tone_q0=%d\n", 1296 - iqcal_tone_i0, iqcal_tone_q0)); 1297 - 1298 - sqsum = iqcal_tone_i0*iqcal_tone_i0 + iqcal_tone_q0*iqcal_tone_q0; 1299 - iq_mag_0_tx = (s32) _sqrt(sqsum); 1300 - PHY_DEBUG(("[CAL] ** auto_adjust_txvga_for_iq_mag_0_tx=%d\n", 1301 - iq_mag_0_tx)); 1302 - 1303 - if (iq_mag_0_tx >= 700 && iq_mag_0_tx <= 1750) 1304 - break; 1305 - else if (iq_mag_0_tx > 1750) { 1306 - init_txvga = -2; 1307 - continue; 1308 - } else 1309 - continue; 1310 - 1311 - } 1312 - 1313 - if (iq_mag_0_tx >= 700 && iq_mag_0_tx <= 1750) 1314 - return true; 1315 - else 1316 - return false; 1317 - }
-85
drivers/staging/winbond/phy_calibration.h
··· 1 - #ifndef __WINBOND_PHY_CALIBRATION_H 2 - #define __WINBOND_PHY_CALIBRATION_H 3 - 4 - #include "wbhal.h" 5 - 6 - #define REG_AGC_CTRL1 0x1000 7 - #define REG_AGC_CTRL2 0x1004 8 - #define REG_AGC_CTRL3 0x1008 9 - #define REG_AGC_CTRL4 0x100C 10 - #define REG_AGC_CTRL5 0x1010 11 - #define REG_AGC_CTRL6 0x1014 12 - #define REG_AGC_CTRL7 0x1018 13 - #define REG_AGC_CTRL8 0x101C 14 - #define REG_AGC_CTRL9 0x1020 15 - #define REG_AGC_CTRL10 0x1024 16 - #define REG_CCA_CTRL 0x1028 17 - #define REG_A_ACQ_CTRL 0x102C 18 - #define REG_B_ACQ_CTRL 0x1030 19 - #define REG_A_TXRX_CTRL 0x1034 20 - #define REG_B_TXRX_CTRL 0x1038 21 - #define REG_A_TX_COEF3 0x103C 22 - #define REG_A_TX_COEF2 0x1040 23 - #define REG_A_TX_COEF1 0x1044 24 - #define REG_B_TX_COEF2 0x1048 25 - #define REG_B_TX_COEF1 0x104C 26 - #define REG_MODE_CTRL 0x1050 27 - #define REG_CALIB_DATA 0x1054 28 - #define REG_IQ_ALPHA 0x1058 29 - #define REG_DC_CANCEL 0x105C 30 - #define REG_WTO_READ 0x1060 31 - #define REG_OFFSET_READ 0x1064 32 - #define REG_CALIB_READ1 0x1068 33 - #define REG_CALIB_READ2 0x106C 34 - #define REG_A_FREQ_EST 0x1070 35 - 36 - 37 - #define MASK_AMER_OFF_REG BIT(31) 38 - 39 - #define MASK_BMER_OFF_REG BIT(31) 40 - 41 - #define MASK_LNA_FIX_GAIN (BIT(3) | BIT(4)) 42 - #define MASK_AGC_FIX BIT(1) 43 - 44 - #define MASK_AGC_FIX_GAIN 0xFF00 45 - 46 - #define MASK_ADC_DC_CAL_STR BIT(10) 47 - #define MASK_CALIB_START BIT(4) 48 - #define MASK_IQCAL_TONE_SEL (BIT(3) | BIT(2)) 49 - #define MASK_IQCAL_MODE (BIT(1) | BIT(0)) 50 - 51 - #define MASK_TX_CAL_0 0xF0000000 52 - #define TX_CAL_0_SHIFT 28 53 - #define MASK_TX_CAL_1 0x0F000000 54 - #define TX_CAL_1_SHIFT 24 55 - #define MASK_TX_CAL_2 0x00F00000 56 - #define TX_CAL_2_SHIFT 20 57 - #define MASK_TX_CAL_3 0x000F0000 58 - #define TX_CAL_3_SHIFT 16 59 - #define MASK_RX_CAL_0 0x0000F000 60 - #define RX_CAL_0_SHIFT 12 61 - #define MASK_RX_CAL_1 0x00000F00 62 - #define RX_CAL_1_SHIFT 8 63 - #define MASK_RX_CAL_2 0x000000F0 64 - #define RX_CAL_2_SHIFT 4 65 - #define MASK_RX_CAL_3 0x0000000F 66 - #define RX_CAL_3_SHIFT 0 67 - 68 - #define MASK_CANCEL_DC_I 0x3E0 69 - #define CANCEL_DC_I_SHIFT 5 70 - #define MASK_CANCEL_DC_Q 0x01F 71 - #define CANCEL_DC_Q_SHIFT 0 72 - 73 - #define MASK_ADC_DC_CAL_I(x) (((x) & 0x0003FE00) >> 9) 74 - #define MASK_ADC_DC_CAL_Q(x) ((x) & 0x000001FF) 75 - 76 - #define MASK_IQCAL_TONE_I 0x00001FFF 77 - #define SHIFT_IQCAL_TONE_I(x) ((x) >> 0) 78 - #define MASK_IQCAL_TONE_Q 0x03FFE000 79 - #define SHIFT_IQCAL_TONE_Q(x) ((x) >> 13) 80 - 81 - void phy_set_rf_data(struct hw_data *pHwData, u32 index, u32 value); 82 - void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency); 83 - #define phy_init_rf(_A) /* RFSynthesizer_initial(_A) */ 84 - 85 - #endif
-2328
drivers/staging/winbond/reg.c
··· 1 - #include "wbhal.h" 2 - #include "wb35reg_f.h" 3 - #include "core.h" 4 - 5 - /* 6 - * ==================================================== 7 - * Original Phy.h 8 - * ==================================================== 9 - */ 10 - 11 - /* 12 - * ==================================================== 13 - * For MAXIM2825/6/7 Ver. 331 or more 14 - * 15 - * 0x00 0x000a2 16 - * 0x01 0x21cc0 17 - * 0x02 0x13802 18 - * 0x02 0x1383a 19 - * 20 - * channe1 01 ; 0x03 0x30142 ; 0x04 0x0b333; 21 - * channe1 02 ; 0x03 0x32141 ; 0x04 0x08444; 22 - * channe1 03 ; 0x03 0x32143 ; 0x04 0x0aeee; 23 - * channe1 04 ; 0x03 0x32142 ; 0x04 0x0b333; 24 - * channe1 05 ; 0x03 0x31141 ; 0x04 0x08444; 25 - * channe1 06 ; 0x03 0x31143 ; 0x04 0x0aeee; 26 - * channe1 07 ; 0x03 0x31142 ; 0x04 0x0b333; 27 - * channe1 08 ; 0x03 0x33141 ; 0x04 0x08444; 28 - * channe1 09 ; 0x03 0x33143 ; 0x04 0x0aeee; 29 - * channe1 10 ; 0x03 0x33142 ; 0x04 0x0b333; 30 - * channe1 11 ; 0x03 0x30941 ; 0x04 0x08444; 31 - * channe1 12 ; 0x03 0x30943 ; 0x04 0x0aeee; 32 - * channe1 13 ; 0x03 0x30942 ; 0x04 0x0b333; 33 - * 34 - * 0x05 0x28986 35 - * 0x06 0x18008 36 - * 0x07 0x38400 37 - * 0x08 0x05100; 100 Hz DC 38 - * 0x08 0x05900; 30 KHz DC 39 - * 0x09 0x24f08 40 - * 0x0a 0x17e00, 0x17ea0 41 - * 0x0b 0x37d80 42 - * 0x0c 0x0c900 -- 0x0ca00 (lager power 9db than 0x0c000), 0x0c000 43 - */ 44 - 45 - /* MAX2825 (pure b/g) */ 46 - static u32 max2825_rf_data[] = { 47 - (0x00<<18) | 0x000a2, 48 - (0x01<<18) | 0x21cc0, 49 - (0x02<<18) | 0x13806, 50 - (0x03<<18) | 0x30142, 51 - (0x04<<18) | 0x0b333, 52 - (0x05<<18) | 0x289A6, 53 - (0x06<<18) | 0x18008, 54 - (0x07<<18) | 0x38000, 55 - (0x08<<18) | 0x05100, 56 - (0x09<<18) | 0x24f08, 57 - (0x0A<<18) | 0x14000, 58 - (0x0B<<18) | 0x37d80, 59 - (0x0C<<18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */ 60 - }; 61 - 62 - static u32 max2825_channel_data_24[][3] = { 63 - {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 01 */ 64 - {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 02 */ 65 - {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 03 */ 66 - {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 04 */ 67 - {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 05 */ 68 - {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 06 */ 69 - {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 07 */ 70 - {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 08 */ 71 - {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 09 */ 72 - {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 10 */ 73 - {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 11 */ 74 - {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 12 */ 75 - {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 13 */ 76 - {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */ 77 - }; 78 - 79 - static u32 max2825_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; 80 - 81 - /* ========================================== */ 82 - /* MAX2827 (a/b/g) */ 83 - static u32 max2827_rf_data[] = { 84 - (0x00 << 18) | 0x000a2, 85 - (0x01 << 18) | 0x21cc0, 86 - (0x02 << 18) | 0x13806, 87 - (0x03 << 18) | 0x30142, 88 - (0x04 << 18) | 0x0b333, 89 - (0x05 << 18) | 0x289A6, 90 - (0x06 << 18) | 0x18008, 91 - (0x07 << 18) | 0x38000, 92 - (0x08 << 18) | 0x05100, 93 - (0x09 << 18) | 0x24f08, 94 - (0x0A << 18) | 0x14000, 95 - (0x0B << 18) | 0x37d80, 96 - (0x0C << 18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */ 97 - }; 98 - 99 - static u32 max2827_channel_data_24[][3] = { 100 - {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 01 */ 101 - {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 02 */ 102 - {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 03 */ 103 - {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 04 */ 104 - {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 05 */ 105 - {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 06 */ 106 - {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 07 */ 107 - {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 08 */ 108 - {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 09 */ 109 - {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 10 */ 110 - {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 11 */ 111 - {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 12 */ 112 - {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 13 */ 113 - {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */ 114 - }; 115 - 116 - static u32 max2827_channel_data_50[][3] = { 117 - {(0x03 << 18) | 0x33cc3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x2A9A6}, /* channel 36 */ 118 - {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2A9A6}, /* channel 40 */ 119 - {(0x03 << 18) | 0x302c2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2A9A6}, /* channel 44 */ 120 - {(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x2A9A6}, /* channel 48 */ 121 - {(0x03 << 18) | 0x312c1, (0x04 << 18) | 0x0a666, (0x05 << 18) | 0x2A9A6}, /* channel 52 */ 122 - {(0x03 << 18) | 0x332c3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x2A9A6}, /* channel 56 */ 123 - {(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2A9A6}, /* channel 60 */ 124 - {(0x03 << 18) | 0x30ac2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2A9A6} /* channel 64 */ 125 - }; 126 - 127 - static u32 max2827_power_data_24[] = {(0x0C << 18) | 0x0C000, (0x0C << 18) | 0x0D600, (0x0C << 18) | 0x0C100}; 128 - static u32 max2827_power_data_50[] = {(0x0C << 18) | 0x0C400, (0x0C << 18) | 0x0D500, (0x0C << 18) | 0x0C300}; 129 - 130 - /* ======================================================= */ 131 - /* MAX2828 (a/b/g) */ 132 - static u32 max2828_rf_data[] = { 133 - (0x00 << 18) | 0x000a2, 134 - (0x01 << 18) | 0x21cc0, 135 - (0x02 << 18) | 0x13806, 136 - (0x03 << 18) | 0x30142, 137 - (0x04 << 18) | 0x0b333, 138 - (0x05 << 18) | 0x289A6, 139 - (0x06 << 18) | 0x18008, 140 - (0x07 << 18) | 0x38000, 141 - (0x08 << 18) | 0x05100, 142 - (0x09 << 18) | 0x24f08, 143 - (0x0A << 18) | 0x14000, 144 - (0x0B << 18) | 0x37d80, 145 - (0x0C << 18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */ 146 - }; 147 - 148 - static u32 max2828_channel_data_24[][3] = { 149 - {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 01 */ 150 - {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 02 */ 151 - {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 03 */ 152 - {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 04 */ 153 - {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 05 */ 154 - {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 06 */ 155 - {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 07 */ 156 - {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 08 */ 157 - {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 09 */ 158 - {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 10 */ 159 - {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 11 */ 160 - {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 12 */ 161 - {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 13 */ 162 - {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */ 163 - }; 164 - 165 - static u32 max2828_channel_data_50[][3] = { 166 - {(0x03 << 18) | 0x33cc3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x289A6}, /* channel 36 */ 167 - {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x289A6}, /* channel 40 */ 168 - {(0x03 << 18) | 0x302c2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 44 */ 169 - {(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6}, /* channel 48 */ 170 - {(0x03 << 18) | 0x312c1, (0x04 << 18) | 0x0a666, (0x05 << 18) | 0x289A6}, /* channel 52 */ 171 - {(0x03 << 18) | 0x332c3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x289A6}, /* channel 56 */ 172 - {(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x289A6}, /* channel 60 */ 173 - {(0x03 << 18) | 0x30ac2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6} /* channel 64 */ 174 - }; 175 - 176 - static u32 max2828_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; 177 - static u32 max2828_power_data_50[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; 178 - 179 - /* ========================================================== */ 180 - /* MAX2829 (a/b/g) */ 181 - static u32 max2829_rf_data[] = { 182 - (0x00 << 18) | 0x000a2, 183 - (0x01 << 18) | 0x23520, 184 - (0x02 << 18) | 0x13802, 185 - (0x03 << 18) | 0x30142, 186 - (0x04 << 18) | 0x0b333, 187 - (0x05 << 18) | 0x28906, 188 - (0x06 << 18) | 0x18008, 189 - (0x07 << 18) | 0x3B500, 190 - (0x08 << 18) | 0x05100, 191 - (0x09 << 18) | 0x24f08, 192 - (0x0A << 18) | 0x14000, 193 - (0x0B << 18) | 0x37d80, 194 - (0x0C << 18) | 0x0F300 /* TXVGA=51, (MAX-6 dB) */ 195 - }; 196 - 197 - static u32 max2829_channel_data_24[][3] = { 198 - {(3 << 18) | 0x30142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 01 (2412MHz) */ 199 - {(3 << 18) | 0x32141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 02 (2417MHz) */ 200 - {(3 << 18) | 0x32143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 03 (2422MHz) */ 201 - {(3 << 18) | 0x32142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 04 (2427MHz) */ 202 - {(3 << 18) | 0x31141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 05 (2432MHz) */ 203 - {(3 << 18) | 0x31143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 06 (2437MHz) */ 204 - {(3 << 18) | 0x31142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 07 (2442MHz) */ 205 - {(3 << 18) | 0x33141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 08 (2447MHz) */ 206 - {(3 << 18) | 0x33143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 09 (2452MHz) */ 207 - {(3 << 18) | 0x33142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 10 (2457MHz) */ 208 - {(3 << 18) | 0x30941, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 11 (2462MHz) */ 209 - {(3 << 18) | 0x30943, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 12 (2467MHz) */ 210 - {(3 << 18) | 0x30942, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 13 (2472MHz) */ 211 - {(3 << 18) | 0x32941, (4 << 18) | 0x09999, (5 << 18) | 0x289C6}, /* 14 (2484MHz) */ 212 - }; 213 - 214 - static u32 max2829_channel_data_50[][4] = { 215 - {36, (3 << 18) | 0x33cc3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 36 (5.180GHz) */ 216 - {40, (3 << 18) | 0x302c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A946}, /* 40 (5.200GHz) */ 217 - {44, (3 << 18) | 0x302c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 44 (5.220GHz) */ 218 - {48, (3 << 18) | 0x322c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 48 (5.240GHz) */ 219 - {52, (3 << 18) | 0x312c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 52 (5.260GHz) */ 220 - {56, (3 << 18) | 0x332c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 56 (5.280GHz) */ 221 - {60, (3 << 18) | 0x30ac0, (4 << 18) | 0x08000, (5 << 18) | 0x2A946}, /* 60 (5.300GHz) */ 222 - {64, (3 << 18) | 0x30ac2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 64 (5.320GHz) */ 223 - 224 - {100, (3 << 18) | 0x30ec0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 100 (5.500GHz) */ 225 - {104, (3 << 18) | 0x30ec2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 104 (5.520GHz) */ 226 - {108, (3 << 18) | 0x32ec1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 108 (5.540GHz) */ 227 - {112, (3 << 18) | 0x31ec1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 112 (5.560GHz) */ 228 - {116, (3 << 18) | 0x33ec3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 116 (5.580GHz) */ 229 - {120, (3 << 18) | 0x301c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 120 (5.600GHz) */ 230 - {124, (3 << 18) | 0x301c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 124 (5.620GHz) */ 231 - {128, (3 << 18) | 0x321c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 128 (5.640GHz) */ 232 - {132, (3 << 18) | 0x311c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 132 (5.660GHz) */ 233 - {136, (3 << 18) | 0x331c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 136 (5.680GHz) */ 234 - {140, (3 << 18) | 0x309c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 140 (5.700GHz) */ 235 - 236 - {149, (3 << 18) | 0x329c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 149 (5.745GHz) */ 237 - {153, (3 << 18) | 0x319c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 153 (5.765GHz) */ 238 - {157, (3 << 18) | 0x339c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 157 (5.785GHz) */ 239 - {161, (3 << 18) | 0x305c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 161 (5.805GHz) */ 240 - 241 - /* Japan */ 242 - { 184, (3 << 18) | 0x308c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 184 (4.920GHz) */ 243 - { 188, (3 << 18) | 0x328c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 188 (4.940GHz) */ 244 - { 192, (3 << 18) | 0x318c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 192 (4.960GHz) */ 245 - { 196, (3 << 18) | 0x338c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 196 (4.980GHz) */ 246 - { 8, (3 << 18) | 0x324c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 8 (5.040GHz) */ 247 - { 12, (3 << 18) | 0x314c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 12 (5.060GHz) */ 248 - { 16, (3 << 18) | 0x334c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 16 (5.080GHz) */ 249 - { 34, (3 << 18) | 0x31cc2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 34 (5.170GHz) */ 250 - { 38, (3 << 18) | 0x33cc1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 38 (5.190GHz) */ 251 - { 42, (3 << 18) | 0x302c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 42 (5.210GHz) */ 252 - { 46, (3 << 18) | 0x322c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 46 (5.230GHz) */ 253 - }; 254 - 255 - /* 256 - * ==================================================================== 257 - * For MAXIM2825/6/7 Ver. 317 or less 258 - * 259 - * 0x00 0x00080 260 - * 0x01 0x214c0 261 - * 0x02 0x13802 262 - * 263 - * 2.4GHz Channels 264 - * channe1 01 (2.412GHz); 0x03 0x30143 ;0x04 0x0accc 265 - * channe1 02 (2.417GHz); 0x03 0x32140 ;0x04 0x09111 266 - * channe1 03 (2.422GHz); 0x03 0x32142 ;0x04 0x0bbbb 267 - * channe1 04 (2.427GHz); 0x03 0x32143 ;0x04 0x0accc 268 - * channe1 05 (2.432GHz); 0x03 0x31140 ;0x04 0x09111 269 - * channe1 06 (2.437GHz); 0x03 0x31142 ;0x04 0x0bbbb 270 - * channe1 07 (2.442GHz); 0x03 0x31143 ;0x04 0x0accc 271 - * channe1 08 (2.447GHz); 0x03 0x33140 ;0x04 0x09111 272 - * channe1 09 (2.452GHz); 0x03 0x33142 ;0x04 0x0bbbb 273 - * channe1 10 (2.457GHz); 0x03 0x33143 ;0x04 0x0accc 274 - * channe1 11 (2.462GHz); 0x03 0x30940 ;0x04 0x09111 275 - * channe1 12 (2.467GHz); 0x03 0x30942 ;0x04 0x0bbbb 276 - * channe1 13 (2.472GHz); 0x03 0x30943 ;0x04 0x0accc 277 - * 278 - * 5.0Ghz Channels 279 - * channel 36 (5.180GHz); 0x03 0x33cc0 ;0x04 0x0b333 280 - * channel 40 (5.200GHz); 0x03 0x302c0 ;0x04 0x08000 281 - * channel 44 (5.220GHz); 0x03 0x302c2 ;0x04 0x0b333 282 - * channel 48 (5.240GHz); 0x03 0x322c1 ;0x04 0x09999 283 - * channel 52 (5.260GHz); 0x03 0x312c1 ;0x04 0x0a666 284 - * channel 56 (5.280GHz); 0x03 0x332c3 ;0x04 0x08ccc 285 - * channel 60 (5.300GHz); 0x03 0x30ac0 ;0x04 0x08000 286 - * channel 64 (5.320GHz); 0x03 0x30ac2 ;0x04 0x08333 287 - * 288 - * 2.4GHz band ; 0x05 0x28986; 289 - * 5.0GHz band ; 0x05 0x2a986 290 - * 0x06 0x18008 291 - * 0x07 0x38400 292 - * 0x08 0x05108 293 - * 0x09 0x27ff8 294 - * 0x0a 0x14000 295 - * 0x0b 0x37f99 296 - * 0x0c 0x0c000 297 - * ==================================================================== 298 - */ 299 - 300 - /* 301 - * =================================================================== 302 - * AL2230 MP (Mass Production Version) 303 - * RF Registers Setting for Airoha AL2230 silicon after June 1st, 2004 304 - * 20-bit length and LSB first 305 - * 306 - * Ch01 (2412MHz) ;0x00 0x09EFC ;0x01 0x8CCCC; 307 - * Ch02 (2417MHz) ;0x00 0x09EFC ;0x01 0x8CCCD; 308 - * Ch03 (2422MHz) ;0x00 0x09E7C ;0x01 0x8CCCC; 309 - * Ch04 (2427MHz) ;0x00 0x09E7C ;0x01 0x8CCCD; 310 - * Ch05 (2432MHz) ;0x00 0x05EFC ;0x01 0x8CCCC; 311 - * Ch06 (2437MHz) ;0x00 0x05EFC ;0x01 0x8CCCD; 312 - * Ch07 (2442MHz) ;0x00 0x05E7C ;0x01 0x8CCCC; 313 - * Ch08 (2447MHz) ;0x00 0x05E7C ;0x01 0x8CCCD; 314 - * Ch09 (2452MHz) ;0x00 0x0DEFC ;0x01 0x8CCCC; 315 - * Ch10 (2457MHz) ;0x00 0x0DEFC ;0x01 0x8CCCD; 316 - * Ch11 (2462MHz) ;0x00 0x0DE7C ;0x01 0x8CCCC; 317 - * Ch12 (2467MHz) ;0x00 0x0DE7C ;0x01 0x8CCCD; 318 - * Ch13 (2472MHz) ;0x00 0x03EFC ;0x01 0x8CCCC; 319 - * Ch14 (2484Mhz) ;0x00 0x03E7C ;0x01 0x86666; 320 - * 321 - * 0x02 0x401D8; RXDCOC BW 100Hz for RXHP low 322 - * 0x02 0x481DC; RXDCOC BW 30Khz for RXHP low 323 - * 324 - * 0x03 0xCFFF0 325 - * 0x04 0x23800 326 - * 0x05 0xA3B72 327 - * 0x06 0x6DA01 328 - * 0x07 0xE1688 329 - * 0x08 0x11600 330 - * 0x09 0x99E02 331 - * 0x0A 0x5DDB0 332 - * 0x0B 0xD9900 333 - * 0x0C 0x3FFBD 334 - * 0x0D 0xB0000 335 - * 0x0F 0xF00A0 336 - * 337 - * RF Calibration for Airoha AL2230 338 - * 339 - * 0x0f 0xf00a0 ; Initial Setting 340 - * 0x0f 0xf00b0 ; Activate TX DCC 341 - * 0x0f 0xf02a0 ; Activate Phase Calibration 342 - * 0x0f 0xf00e0 ; Activate Filter RC Calibration 343 - * 0x0f 0xf00a0 ; Restore Initial Setting 344 - * ================================================================== 345 - */ 346 - static u32 al2230_rf_data[] = { 347 - (0x00 << 20) | 0x09EFC, 348 - (0x01 << 20) | 0x8CCCC, 349 - (0x02 << 20) | 0x40058, 350 - (0x03 << 20) | 0xCFFF0, 351 - (0x04 << 20) | 0x24100, 352 - (0x05 << 20) | 0xA3B2F, 353 - (0x06 << 20) | 0x6DA01, 354 - (0x07 << 20) | 0xE3628, 355 - (0x08 << 20) | 0x11600, 356 - (0x09 << 20) | 0x9DC02, 357 - (0x0A << 20) | 0x5ddb0, 358 - (0x0B << 20) | 0xD9900, 359 - (0x0C << 20) | 0x3FFBD, 360 - (0x0D << 20) | 0xB0000, 361 - (0x0F << 20) | 0xF01A0 362 - }; 363 - 364 - static u32 al2230s_rf_data[] = { 365 - (0x00 << 20) | 0x09EFC, 366 - (0x01 << 20) | 0x8CCCC, 367 - (0x02 << 20) | 0x40058, 368 - (0x03 << 20) | 0xCFFF0, 369 - (0x04 << 20) | 0x24100, 370 - (0x05 << 20) | 0xA3B2F, 371 - (0x06 << 20) | 0x6DA01, 372 - (0x07 << 20) | 0xE3628, 373 - (0x08 << 20) | 0x11600, 374 - (0x09 << 20) | 0x9DC02, 375 - (0x0A << 20) | 0x5DDB0, 376 - (0x0B << 20) | 0xD9900, 377 - (0x0C << 20) | 0x3FFBD, 378 - (0x0D << 20) | 0xB0000, 379 - (0x0F << 20) | 0xF01A0 380 - }; 381 - 382 - static u32 al2230_channel_data_24[][2] = { 383 - {(0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 01 */ 384 - {(0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCD}, /* channe1 02 */ 385 - {(0x00 << 20) | 0x09E7C, (0x01 << 20) | 0x8CCCC}, /* channe1 03 */ 386 - {(0x00 << 20) | 0x09E7C, (0x01 << 20) | 0x8CCCD}, /* channe1 04 */ 387 - {(0x00 << 20) | 0x05EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 05 */ 388 - {(0x00 << 20) | 0x05EFC, (0x01 << 20) | 0x8CCCD}, /* channe1 06 */ 389 - {(0x00 << 20) | 0x05E7C, (0x01 << 20) | 0x8CCCC}, /* channe1 07 */ 390 - {(0x00 << 20) | 0x05E7C, (0x01 << 20) | 0x8CCCD}, /* channe1 08 */ 391 - {(0x00 << 20) | 0x0DEFC, (0x01 << 20) | 0x8CCCC}, /* channe1 09 */ 392 - {(0x00 << 20) | 0x0DEFC, (0x01 << 20) | 0x8CCCD}, /* channe1 10 */ 393 - {(0x00 << 20) | 0x0DE7C, (0x01 << 20) | 0x8CCCC}, /* channe1 11 */ 394 - {(0x00 << 20) | 0x0DE7C, (0x01 << 20) | 0x8CCCD}, /* channe1 12 */ 395 - {(0x00 << 20) | 0x03EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 13 */ 396 - {(0x00 << 20) | 0x03E7C, (0x01 << 20) | 0x86666} /* channe1 14 */ 397 - }; 398 - 399 - /* Current setting. u32 airoha_power_data_24[] = {(0x09 << 20) | 0x90202, (0x09 << 20) | 0x96602, (0x09 << 20) | 0x97602}; */ 400 - #define AIROHA_TXVGA_LOW_INDEX 31 /* Index for 0x90202 */ 401 - #define AIROHA_TXVGA_MIDDLE_INDEX 12 /* Index for 0x96602 */ 402 - #define AIROHA_TXVGA_HIGH_INDEX 8 /* Index for 0x97602 1.0.24.0 1.0.28.0 */ 403 - 404 - static u32 al2230_txvga_data[][2] = { 405 - /* value , index */ 406 - {0x090202, 0}, 407 - {0x094202, 2}, 408 - {0x092202, 4}, 409 - {0x096202, 6}, 410 - {0x091202, 8}, 411 - {0x095202, 10}, 412 - {0x093202, 12}, 413 - {0x097202, 14}, 414 - {0x090A02, 16}, 415 - {0x094A02, 18}, 416 - {0x092A02, 20}, 417 - {0x096A02, 22}, 418 - {0x091A02, 24}, 419 - {0x095A02, 26}, 420 - {0x093A02, 28}, 421 - {0x097A02, 30}, 422 - {0x090602, 32}, 423 - {0x094602, 34}, 424 - {0x092602, 36}, 425 - {0x096602, 38}, 426 - {0x091602, 40}, 427 - {0x095602, 42}, 428 - {0x093602, 44}, 429 - {0x097602, 46}, 430 - {0x090E02, 48}, 431 - {0x098E02, 49}, 432 - {0x094E02, 50}, 433 - {0x09CE02, 51}, 434 - {0x092E02, 52}, 435 - {0x09AE02, 53}, 436 - {0x096E02, 54}, 437 - {0x09EE02, 55}, 438 - {0x091E02, 56}, 439 - {0x099E02, 57}, 440 - {0x095E02, 58}, 441 - {0x09DE02, 59}, 442 - {0x093E02, 60}, 443 - {0x09BE02, 61}, 444 - {0x097E02, 62}, 445 - {0x09FE02, 63} 446 - }; 447 - 448 - /* 449 - * ========================================== 450 - * For Airoha AL7230, 2.4Ghz band 451 - * 24bit, MSB first 452 - */ 453 - 454 - /* channel independent registers: */ 455 - static u32 al7230_rf_data_24[] = { 456 - (0x00 << 24) | 0x003790, 457 - (0x01 << 24) | 0x133331, 458 - (0x02 << 24) | 0x841FF2, 459 - (0x03 << 24) | 0x3FDFA3, 460 - (0x04 << 24) | 0x7FD784, 461 - (0x05 << 24) | 0x802B55, 462 - (0x06 << 24) | 0x56AF36, 463 - (0x07 << 24) | 0xCE0207, 464 - (0x08 << 24) | 0x6EBC08, 465 - (0x09 << 24) | 0x221BB9, 466 - (0x0A << 24) | 0xE0000A, 467 - (0x0B << 24) | 0x08071B, 468 - (0x0C << 24) | 0x000A3C, 469 - (0x0D << 24) | 0xFFFFFD, 470 - (0x0E << 24) | 0x00000E, 471 - (0x0F << 24) | 0x1ABA8F 472 - }; 473 - 474 - static u32 al7230_channel_data_24[][2] = { 475 - {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x133331}, /* channe1 01 */ 476 - {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x1B3331}, /* channe1 02 */ 477 - {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x033331}, /* channe1 03 */ 478 - {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x0B3331}, /* channe1 04 */ 479 - {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x133331}, /* channe1 05 */ 480 - {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x1B3331}, /* channe1 06 */ 481 - {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x033331}, /* channe1 07 */ 482 - {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x0B3331}, /* channe1 08 */ 483 - {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x133331}, /* channe1 09 */ 484 - {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x1B3331}, /* channe1 10 */ 485 - {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x033331}, /* channe1 11 */ 486 - {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x0B3331}, /* channe1 12 */ 487 - {(0x00 << 24) | 0x0037C0, (0x01 << 24) | 0x133331}, /* channe1 13 */ 488 - {(0x00 << 24) | 0x0037C0, (0x01 << 24) | 0x066661} /* channel 14 */ 489 - }; 490 - 491 - /* channel independent registers: */ 492 - static u32 al7230_rf_data_50[] = { 493 - (0x00 << 24) | 0x0FF520, 494 - (0x01 << 24) | 0x000001, 495 - (0x02 << 24) | 0x451FE2, 496 - (0x03 << 24) | 0x5FDFA3, 497 - (0x04 << 24) | 0x6FD784, 498 - (0x05 << 24) | 0x853F55, 499 - (0x06 << 24) | 0x56AF36, 500 - (0x07 << 24) | 0xCE0207, 501 - (0x08 << 24) | 0x6EBC08, 502 - (0x09 << 24) | 0x221BB9, 503 - (0x0A << 24) | 0xE0600A, 504 - (0x0B << 24) | 0x08044B, 505 - (0x0C << 24) | 0x00143C, 506 - (0x0D << 24) | 0xFFFFFD, 507 - (0x0E << 24) | 0x00000E, 508 - (0x0F << 24) | 0x12BACF /* 5Ghz default state */ 509 - }; 510 - 511 - static u32 al7230_channel_data_5[][4] = { 512 - /* channel dependent registers: 0x00, 0x01 and 0x04 */ 513 - /* 11J =========== */ 514 - {184, (0x00 << 24) | 0x0FF520, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 184 */ 515 - {188, (0x00 << 24) | 0x0FF520, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 188 */ 516 - {192, (0x00 << 24) | 0x0FF530, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 192 */ 517 - {196, (0x00 << 24) | 0x0FF530, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 196 */ 518 - {8, (0x00 << 24) | 0x0FF540, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 008 */ 519 - {12, (0x00 << 24) | 0x0FF540, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 012 */ 520 - {16, (0x00 << 24) | 0x0FF550, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 016 */ 521 - {34, (0x00 << 24) | 0x0FF560, (0x01 << 24) | 0x055551, (0x04 << 24) | 0x77F784}, /* channel 034 */ 522 - {38, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x100001, (0x04 << 24) | 0x77F784}, /* channel 038 */ 523 - {42, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x1AAAA1, (0x04 << 24) | 0x77F784}, /* channel 042 */ 524 - {46, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x055551, (0x04 << 24) | 0x77F784}, /* channel 046 */ 525 - /* 11 A/H ========= */ 526 - {36, (0x00 << 24) | 0x0FF560, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 036 */ 527 - {40, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 040 */ 528 - {44, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 044 */ 529 - {48, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 048 */ 530 - {52, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 052 */ 531 - {56, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 056 */ 532 - {60, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 060 */ 533 - {64, (0x00 << 24) | 0x0FF590, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 064 */ 534 - {100, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 100 */ 535 - {104, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 104 */ 536 - {108, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 108 */ 537 - {112, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 112 */ 538 - {116, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 116 */ 539 - {120, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 120 */ 540 - {124, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 124 */ 541 - {128, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 128 */ 542 - {132, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 132 */ 543 - {136, (0x00 << 24) | 0x0FF5F0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 136 */ 544 - {140, (0x00 << 24) | 0x0FF5F0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 140 */ 545 - {149, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x180001, (0x04 << 24) | 0x77F784}, /* channel 149 */ 546 - {153, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x02AAA1, (0x04 << 24) | 0x77F784}, /* channel 153 */ 547 - {157, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x0D5551, (0x04 << 24) | 0x77F784}, /* channel 157 */ 548 - {161, (0x00 << 24) | 0x0FF610, (0x01 << 24) | 0x180001, (0x04 << 24) | 0x77F784}, /* channel 161 */ 549 - {165, (0x00 << 24) | 0x0FF610, (0x01 << 24) | 0x02AAA1, (0x04 << 24) | 0x77F784} /* channel 165 */ 550 - }; 551 - 552 - /* 553 - * RF Calibration <=== Register 0x0F 554 - * 0x0F 0x1ABA8F; start from 2.4Ghz default state 555 - * 0x0F 0x9ABA8F; TXDC compensation 556 - * 0x0F 0x3ABA8F; RXFIL adjustment 557 - * 0x0F 0x1ABA8F; restore 2.4Ghz default state 558 - */ 559 - 560 - /* TXVGA Mapping Table <=== Register 0x0B */ 561 - static u32 al7230_txvga_data[][2] = { 562 - {0x08040B, 0}, /* TXVGA = 0; */ 563 - {0x08041B, 1}, /* TXVGA = 1; */ 564 - {0x08042B, 2}, /* TXVGA = 2; */ 565 - {0x08043B, 3}, /* TXVGA = 3; */ 566 - {0x08044B, 4}, /* TXVGA = 4; */ 567 - {0x08045B, 5}, /* TXVGA = 5; */ 568 - {0x08046B, 6}, /* TXVGA = 6; */ 569 - {0x08047B, 7}, /* TXVGA = 7; */ 570 - {0x08048B, 8}, /* TXVGA = 8; */ 571 - {0x08049B, 9}, /* TXVGA = 9; */ 572 - {0x0804AB, 10}, /* TXVGA = 10; */ 573 - {0x0804BB, 11}, /* TXVGA = 11; */ 574 - {0x0804CB, 12}, /* TXVGA = 12; */ 575 - {0x0804DB, 13}, /* TXVGA = 13; */ 576 - {0x0804EB, 14}, /* TXVGA = 14; */ 577 - {0x0804FB, 15}, /* TXVGA = 15; */ 578 - {0x08050B, 16}, /* TXVGA = 16; */ 579 - {0x08051B, 17}, /* TXVGA = 17; */ 580 - {0x08052B, 18}, /* TXVGA = 18; */ 581 - {0x08053B, 19}, /* TXVGA = 19; */ 582 - {0x08054B, 20}, /* TXVGA = 20; */ 583 - {0x08055B, 21}, /* TXVGA = 21; */ 584 - {0x08056B, 22}, /* TXVGA = 22; */ 585 - {0x08057B, 23}, /* TXVGA = 23; */ 586 - {0x08058B, 24}, /* TXVGA = 24; */ 587 - {0x08059B, 25}, /* TXVGA = 25; */ 588 - {0x0805AB, 26}, /* TXVGA = 26; */ 589 - {0x0805BB, 27}, /* TXVGA = 27; */ 590 - {0x0805CB, 28}, /* TXVGA = 28; */ 591 - {0x0805DB, 29}, /* TXVGA = 29; */ 592 - {0x0805EB, 30}, /* TXVGA = 30; */ 593 - {0x0805FB, 31}, /* TXVGA = 31; */ 594 - {0x08060B, 32}, /* TXVGA = 32; */ 595 - {0x08061B, 33}, /* TXVGA = 33; */ 596 - {0x08062B, 34}, /* TXVGA = 34; */ 597 - {0x08063B, 35}, /* TXVGA = 35; */ 598 - {0x08064B, 36}, /* TXVGA = 36; */ 599 - {0x08065B, 37}, /* TXVGA = 37; */ 600 - {0x08066B, 38}, /* TXVGA = 38; */ 601 - {0x08067B, 39}, /* TXVGA = 39; */ 602 - {0x08068B, 40}, /* TXVGA = 40; */ 603 - {0x08069B, 41}, /* TXVGA = 41; */ 604 - {0x0806AB, 42}, /* TXVGA = 42; */ 605 - {0x0806BB, 43}, /* TXVGA = 43; */ 606 - {0x0806CB, 44}, /* TXVGA = 44; */ 607 - {0x0806DB, 45}, /* TXVGA = 45; */ 608 - {0x0806EB, 46}, /* TXVGA = 46; */ 609 - {0x0806FB, 47}, /* TXVGA = 47; */ 610 - {0x08070B, 48}, /* TXVGA = 48; */ 611 - {0x08071B, 49}, /* TXVGA = 49; */ 612 - {0x08072B, 50}, /* TXVGA = 50; */ 613 - {0x08073B, 51}, /* TXVGA = 51; */ 614 - {0x08074B, 52}, /* TXVGA = 52; */ 615 - {0x08075B, 53}, /* TXVGA = 53; */ 616 - {0x08076B, 54}, /* TXVGA = 54; */ 617 - {0x08077B, 55}, /* TXVGA = 55; */ 618 - {0x08078B, 56}, /* TXVGA = 56; */ 619 - {0x08079B, 57}, /* TXVGA = 57; */ 620 - {0x0807AB, 58}, /* TXVGA = 58; */ 621 - {0x0807BB, 59}, /* TXVGA = 59; */ 622 - {0x0807CB, 60}, /* TXVGA = 60; */ 623 - {0x0807DB, 61}, /* TXVGA = 61; */ 624 - {0x0807EB, 62}, /* TXVGA = 62; */ 625 - {0x0807FB, 63}, /* TXVGA = 63; */ 626 - }; 627 - /* ============================================= */ 628 - 629 - /* 630 - * W89RF242 RFIC SPI programming initial data 631 - * Winbond WLAN 11g RFIC BB-SPI register -- version FA5976A rev 1.3b 632 - */ 633 - static u32 w89rf242_rf_data[] = { 634 - (0x00 << 24) | 0xF86100, /* 3E184; MODA (0x00) -- Normal mode ; calibration off */ 635 - (0x01 << 24) | 0xEFFFC2, /* 3BFFF; MODB (0x01) -- turn off RSSI, and other circuits are turned on */ 636 - (0x02 << 24) | 0x102504, /* 04094; FSET (0x02) -- default 20MHz crystal ; Icmp=1.5mA */ 637 - (0x03 << 24) | 0x026286, /* 0098A; FCHN (0x03) -- default CH7, 2442MHz */ 638 - (0x04 << 24) | 0x000208, /* 02008; FCAL (0x04) -- XTAL Freq Trim=001000 (socket board#1); FA5976AYG_v1.3C */ 639 - (0x05 << 24) | 0x24C60A, /* 09316; GANA (0x05) -- TX VGA default (TXVGA=0x18(12)) & TXGPK=110 ; FA5976A_1.3D */ 640 - (0x06 << 24) | 0x3432CC, /* 0D0CB; GANB (0x06) -- RXDC(DC offset) on; LNA=11; RXVGA=001011(11) ; RXFLSW=11(010001); RXGPK=00; RXGCF=00; -50dBm input */ 641 - (0x07 << 24) | 0x0C68CE, /* 031A3; FILT (0x07) -- TX/RX filter with auto-tuning; TFLBW=011; RFLBW=100 */ 642 - (0x08 << 24) | 0x100010, /* 04000; TCAL (0x08) -- for LO */ 643 - (0x09 << 24) | 0x004012, /* 1B900; RCALA (0x09) -- FASTS=11; HPDE=01 (100nsec); SEHP=1 (select B0 pin=RXHP); RXHP=1 (Turn on RXHP function)(FA5976A_1.3C) */ 644 - (0x0A << 24) | 0x704014, /* 1C100; RCALB (0x0A) */ 645 - (0x0B << 24) | 0x18BDD6, /* 062F7; IQCAL (0x0B) -- Turn on LO phase tuner=0111 & RX-LO phase = 0111; FA5976A_1.3B */ 646 - (0x0C << 24) | 0x575558, /* 15D55 ; IBSA (0x0C) -- IFPre =11 ; TC5376A_v1.3A for corner */ 647 - (0x0D << 24) | 0x55545A, /* 15555 ; IBSB (0x0D) */ 648 - (0x0E << 24) | 0x5557DC, /* 1555F ; IBSC (0x0E) -- IRLNA & IRLNB (PTAT & Const current)=01/01; FA5976B_1.3F */ 649 - (0x10 << 24) | 0x000C20, /* 00030 ; TMODA (0x10) -- LNA_gain_step=0011 ; LNA=15/16dB */ 650 - (0x11 << 24) | 0x0C0022, /* 03000 ; TMODB (0x11) -- Turn ON RX-Q path Test Switch; To improve IQ path group delay (FA5976A_1.3C) */ 651 - (0x12 << 24) | 0x000024 /* TMODC (0x12) -- Turn OFF Temperature sensor */ 652 - }; 653 - 654 - static u32 w89rf242_channel_data_24[][2] = { 655 - {(0x03 << 24) | 0x025B06, (0x04 << 24) | 0x080408}, /* channe1 01 */ 656 - {(0x03 << 24) | 0x025C46, (0x04 << 24) | 0x080408}, /* channe1 02 */ 657 - {(0x03 << 24) | 0x025D86, (0x04 << 24) | 0x080408}, /* channe1 03 */ 658 - {(0x03 << 24) | 0x025EC6, (0x04 << 24) | 0x080408}, /* channe1 04 */ 659 - {(0x03 << 24) | 0x026006, (0x04 << 24) | 0x080408}, /* channe1 05 */ 660 - {(0x03 << 24) | 0x026146, (0x04 << 24) | 0x080408}, /* channe1 06 */ 661 - {(0x03 << 24) | 0x026286, (0x04 << 24) | 0x080408}, /* channe1 07 */ 662 - {(0x03 << 24) | 0x0263C6, (0x04 << 24) | 0x080408}, /* channe1 08 */ 663 - {(0x03 << 24) | 0x026506, (0x04 << 24) | 0x080408}, /* channe1 09 */ 664 - {(0x03 << 24) | 0x026646, (0x04 << 24) | 0x080408}, /* channe1 10 */ 665 - {(0x03 << 24) | 0x026786, (0x04 << 24) | 0x080408}, /* channe1 11 */ 666 - {(0x03 << 24) | 0x0268C6, (0x04 << 24) | 0x080408}, /* channe1 12 */ 667 - {(0x03 << 24) | 0x026A06, (0x04 << 24) | 0x080408}, /* channe1 13 */ 668 - {(0x03 << 24) | 0x026D06, (0x04 << 24) | 0x080408} /* channe1 14 */ 669 - }; 670 - 671 - static u32 w89rf242_txvga_old_mapping[][2] = { 672 - {0, 0} , /* New <-> Old */ 673 - {1, 1} , 674 - {2, 2} , 675 - {3, 3} , 676 - {4, 4} , 677 - {6, 5} , 678 - {8, 6}, 679 - {10, 7}, 680 - {12, 8}, 681 - {14, 9}, 682 - {16, 10}, 683 - {18, 11}, 684 - {20, 12}, 685 - {22, 13}, 686 - {24, 14}, 687 - {26, 15}, 688 - {28, 16}, 689 - {30, 17}, 690 - {32, 18}, 691 - {34, 19}, 692 - }; 693 - 694 - static u32 w89rf242_txvga_data[][5] = { 695 - /* low gain mode */ 696 - {(0x05 << 24) | 0x24C00A, 0, 0x00292315, 0x0800FEFF, 0x52523131}, /* min gain */ 697 - {(0x05 << 24) | 0x24C80A, 1, 0x00292315, 0x0800FEFF, 0x52523131}, 698 - {(0x05 << 24) | 0x24C04A, 2, 0x00292315, 0x0800FEFF, 0x52523131}, /* (default) +14dBm (ANT) */ 699 - {(0x05 << 24) | 0x24C84A, 3, 0x00292315, 0x0800FEFF, 0x52523131}, 700 - 701 - /* TXVGA=0x10 */ 702 - {(0x05 << 24) | 0x24C40A, 4, 0x00292315, 0x0800FEFF, 0x60603838}, 703 - {(0x05 << 24) | 0x24C40A, 5, 0x00262114, 0x0700FEFF, 0x65653B3B}, 704 - 705 - /* TXVGA=0x11 */ 706 - { (0x05 << 24) | 0x24C44A, 6, 0x00241F13, 0x0700FFFF, 0x58583333}, 707 - { (0x05 << 24) | 0x24C44A, 7, 0x00292315, 0x0800FEFF, 0x5E5E3737}, 708 - 709 - /* TXVGA=0x12 */ 710 - {(0x05 << 24) | 0x24C48A, 8, 0x00262114, 0x0700FEFF, 0x53533030}, 711 - {(0x05 << 24) | 0x24C48A, 9, 0x00241F13, 0x0700FFFF, 0x59593434}, 712 - 713 - /* TXVGA=0x13 */ 714 - {(0x05 << 24) | 0x24C4CA, 10, 0x00292315, 0x0800FEFF, 0x52523030}, 715 - {(0x05 << 24) | 0x24C4CA, 11, 0x00262114, 0x0700FEFF, 0x56563232}, 716 - 717 - /* TXVGA=0x14 */ 718 - {(0x05 << 24) | 0x24C50A, 12, 0x00292315, 0x0800FEFF, 0x54543131}, 719 - {(0x05 << 24) | 0x24C50A, 13, 0x00262114, 0x0700FEFF, 0x58583434}, 720 - 721 - /* TXVGA=0x15 */ 722 - {(0x05 << 24) | 0x24C54A, 14, 0x00292315, 0x0800FEFF, 0x54543131}, 723 - {(0x05 << 24) | 0x24C54A, 15, 0x00262114, 0x0700FEFF, 0x59593434}, 724 - 725 - /* TXVGA=0x16 */ 726 - {(0x05 << 24) | 0x24C58A, 16, 0x00292315, 0x0800FEFF, 0x55553131}, 727 - {(0x05 << 24) | 0x24C58A, 17, 0x00292315, 0x0800FEFF, 0x5B5B3535}, 728 - 729 - /* TXVGA=0x17 */ 730 - {(0x05 << 24) | 0x24C5CA, 18, 0x00262114, 0x0700FEFF, 0x51512F2F}, 731 - {(0x05 << 24) | 0x24C5CA, 19, 0x00241F13, 0x0700FFFF, 0x55553131}, 732 - 733 - /* TXVGA=0x18 */ 734 - {(0x05 << 24) | 0x24C60A, 20, 0x00292315, 0x0800FEFF, 0x4F4F2E2E}, 735 - {(0x05 << 24) | 0x24C60A, 21, 0x00262114, 0x0700FEFF, 0x53533030}, 736 - 737 - /* TXVGA=0x19 */ 738 - {(0x05 << 24) | 0x24C64A, 22, 0x00292315, 0x0800FEFF, 0x4E4E2D2D}, 739 - {(0x05 << 24) | 0x24C64A, 23, 0x00262114, 0x0700FEFF, 0x53533030}, 740 - 741 - /* TXVGA=0x1A */ 742 - {(0x05 << 24) | 0x24C68A, 24, 0x00292315, 0x0800FEFF, 0x50502E2E}, 743 - {(0x05 << 24) | 0x24C68A, 25, 0x00262114, 0x0700FEFF, 0x55553131}, 744 - 745 - /* TXVGA=0x1B */ 746 - {(0x05 << 24) | 0x24C6CA, 26, 0x00262114, 0x0700FEFF, 0x53533030}, 747 - {(0x05 << 24) | 0x24C6CA, 27, 0x00292315, 0x0800FEFF, 0x5A5A3434}, 748 - 749 - /* TXVGA=0x1C */ 750 - {(0x05 << 24) | 0x24C70A, 28, 0x00292315, 0x0800FEFF, 0x55553131}, 751 - {(0x05 << 24) | 0x24C70A, 29, 0x00292315, 0x0800FEFF, 0x5D5D3636}, 752 - 753 - /* TXVGA=0x1D */ 754 - {(0x05 << 24) | 0x24C74A, 30, 0x00292315, 0x0800FEFF, 0x5F5F3737}, 755 - {(0x05 << 24) | 0x24C74A, 31, 0x00262114, 0x0700FEFF, 0x65653B3B}, 756 - 757 - /* TXVGA=0x1E */ 758 - {(0x05 << 24) | 0x24C78A, 32, 0x00292315, 0x0800FEFF, 0x66663B3B}, 759 - {(0x05 << 24) | 0x24C78A, 33, 0x00262114, 0x0700FEFF, 0x70704141}, 760 - 761 - /* TXVGA=0x1F */ 762 - {(0x05 << 24) | 0x24C7CA, 34, 0x00292315, 0x0800FEFF, 0x72724242} 763 - }; 764 - 765 - /* ================================================================================================== */ 766 - 767 - 768 - 769 - /* 770 - * ============================================================================================================= 771 - * Uxx_ReadEthernetAddress -- 772 - * 773 - * Routine Description: 774 - * Reads in the Ethernet address from the IC. 775 - * 776 - * Arguments: 777 - * pHwData - The pHwData structure 778 - * 779 - * Return Value: 780 - * 781 - * The address is stored in EthernetIDAddr. 782 - * ============================================================================================================= 783 - */ 784 - void Uxx_ReadEthernetAddress(struct hw_data *pHwData) 785 - { 786 - u32 ltmp; 787 - 788 - /* 789 - * Reading Ethernet address from EEPROM and set into hardware due to MAC address maybe change. 790 - * Only unplug and plug again can make hardware read EEPROM again. 791 - */ 792 - Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08000000); /* Start EEPROM access + Read + address(0x0d) */ 793 - Wb35Reg_ReadSync(pHwData, 0x03b4, &ltmp); 794 - *(u16 *)pHwData->PermanentMacAddress = cpu_to_le16((u16) ltmp); 795 - Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08010000); /* Start EEPROM access + Read + address(0x0d) */ 796 - Wb35Reg_ReadSync(pHwData, 0x03b4, &ltmp); 797 - *(u16 *)(pHwData->PermanentMacAddress + 2) = cpu_to_le16((u16) ltmp); 798 - Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08020000); /* Start EEPROM access + Read + address(0x0d) */ 799 - Wb35Reg_ReadSync(pHwData, 0x03b4, &ltmp); 800 - *(u16 *)(pHwData->PermanentMacAddress + 4) = cpu_to_le16((u16) ltmp); 801 - *(u16 *)(pHwData->PermanentMacAddress + 6) = 0; 802 - Wb35Reg_WriteSync(pHwData, 0x03e8, cpu_to_le32(*(u32 *)pHwData->PermanentMacAddress)); 803 - Wb35Reg_WriteSync(pHwData, 0x03ec, cpu_to_le32(*(u32 *)(pHwData->PermanentMacAddress + 4))); 804 - } 805 - 806 - 807 - /* 808 - * =============================================================================================================== 809 - * CardGetMulticastBit -- 810 - * Description: 811 - * For a given multicast address, returns the byte and bit in the card multicast registers that it hashes to. 812 - * Calls CardComputeCrc() to determine the CRC value. 813 - * Arguments: 814 - * Address - the address 815 - * Byte - the byte that it hashes to 816 - * Value - will have a 1 in the relevant bit 817 - * Return Value: 818 - * None. 819 - * ============================================================================================================== 820 - */ 821 - void CardGetMulticastBit(u8 Address[ETH_ALEN], u8 *Byte, u8 *Value) 822 - { 823 - u32 Crc; 824 - u32 BitNumber; 825 - 826 - /* First compute the CRC. */ 827 - Crc = CardComputeCrc(Address, ETH_ALEN); 828 - 829 - /* The computed CRC is bit0~31 from left to right */ 830 - /* At first we should do right shift 25bits, and read 7bits by using '&', 2^7=128 */ 831 - BitNumber = (u32) ((Crc >> 26) & 0x3f); 832 - 833 - *Byte = (u8) (BitNumber >> 3); /* 900514 original (BitNumber / 8) */ 834 - *Value = (u8) ((u8) 1 << (BitNumber % 8)); 835 - } 836 - 837 - void Uxx_power_on_procedure(struct hw_data *pHwData) 838 - { 839 - u32 ltmp, loop; 840 - 841 - if (pHwData->phy_type <= RF_MAXIM_V1) 842 - Wb35Reg_WriteSync(pHwData, 0x03d4, 0xffffff38); 843 - else { 844 - Wb35Reg_WriteSync(pHwData, 0x03f4, 0xFF5807FF); 845 - Wb35Reg_WriteSync(pHwData, 0x03d4, 0x80); /* regulator on only */ 846 - msleep(10); 847 - Wb35Reg_WriteSync(pHwData, 0x03d4, 0xb8); /* REG_ON RF_RSTN on, and */ 848 - msleep(10); 849 - ltmp = 0x4968; 850 - if ((pHwData->phy_type == RF_WB_242) || 851 - (RF_WB_242_1 == pHwData->phy_type)) 852 - ltmp = 0x4468; 853 - 854 - Wb35Reg_WriteSync(pHwData, 0x03d0, ltmp); 855 - Wb35Reg_WriteSync(pHwData, 0x03d4, 0xa0); /* PLL_PD REF_PD set to 0 */ 856 - 857 - msleep(20); 858 - Wb35Reg_ReadSync(pHwData, 0x03d0, &ltmp); 859 - loop = 500; /* Wait for 5 second */ 860 - while (!(ltmp & 0x20) && loop--) { 861 - msleep(10); 862 - if (!Wb35Reg_ReadSync(pHwData, 0x03d0, &ltmp)) 863 - break; 864 - } 865 - 866 - Wb35Reg_WriteSync(pHwData, 0x03d4, 0xe0); /* MLK_EN */ 867 - } 868 - 869 - Wb35Reg_WriteSync(pHwData, 0x03b0, 1); /* Reset hardware first */ 870 - msleep(10); 871 - 872 - /* Set burst write delay */ 873 - Wb35Reg_WriteSync(pHwData, 0x03f8, 0x7ff); 874 - } 875 - 876 - static void Set_ChanIndep_RfData_al7230_24(struct hw_data *pHwData, u32 *pltmp, 877 - char number) 878 - { 879 - u8 i; 880 - for (i = 0; i < number; i++) { 881 - pHwData->phy_para[i] = al7230_rf_data_24[i]; 882 - pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_24[i] & 0xffffff); 883 - } 884 - } 885 - 886 - static void Set_ChanIndep_RfData_al7230_50(struct hw_data *pHwData, u32 *pltmp, 887 - char number) 888 - { 889 - u8 i; 890 - for (i = 0; i < number; i++) { 891 - pHwData->phy_para[i] = al7230_rf_data_50[i]; 892 - pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_50[i] & 0xffffff); 893 - } 894 - } 895 - 896 - 897 - /* 898 - * ============================================================================================================= 899 - * RFSynthesizer_initial -- 900 - * ============================================================================================================= 901 - */ 902 - void RFSynthesizer_initial(struct hw_data *pHwData) 903 - { 904 - u32 altmp[32]; 905 - u32 *pltmp = altmp; 906 - u32 ltmp; 907 - u8 number = 0x00; /* The number of register vale */ 908 - u8 i; 909 - 910 - /* 911 - * bit[31] SPI Enable. 912 - * 1=perform synthesizer program operation. This bit will 913 - * cleared automatically after the operation is completed. 914 - * bit[30] SPI R/W Control 915 - * 0=write, 1=read 916 - * bit[29:24] SPI Data Format Length 917 - * bit[17:4 ] RF Data bits. 918 - * bit[3 :0 ] RF address. 919 - */ 920 - switch (pHwData->phy_type) { 921 - case RF_MAXIM_2825: 922 - case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */ 923 - number = ARRAY_SIZE(max2825_rf_data); 924 - for (i = 0; i < number; i++) { 925 - pHwData->phy_para[i] = max2825_rf_data[i]; /* Backup Rf parameter */ 926 - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_rf_data[i], 18); 927 - } 928 - break; 929 - case RF_MAXIM_2827: 930 - number = ARRAY_SIZE(max2827_rf_data); 931 - for (i = 0; i < number; i++) { 932 - pHwData->phy_para[i] = max2827_rf_data[i]; 933 - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_rf_data[i], 18); 934 - } 935 - break; 936 - case RF_MAXIM_2828: 937 - number = ARRAY_SIZE(max2828_rf_data); 938 - for (i = 0; i < number; i++) { 939 - pHwData->phy_para[i] = max2828_rf_data[i]; 940 - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_rf_data[i], 18); 941 - } 942 - break; 943 - case RF_MAXIM_2829: 944 - number = ARRAY_SIZE(max2829_rf_data); 945 - for (i = 0; i < number; i++) { 946 - pHwData->phy_para[i] = max2829_rf_data[i]; 947 - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_rf_data[i], 18); 948 - } 949 - break; 950 - case RF_AIROHA_2230: 951 - number = ARRAY_SIZE(al2230_rf_data); 952 - for (i = 0; i < number; i++) { 953 - pHwData->phy_para[i] = al2230_rf_data[i]; 954 - pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_rf_data[i], 20); 955 - } 956 - break; 957 - case RF_AIROHA_2230S: 958 - number = ARRAY_SIZE(al2230s_rf_data); 959 - for (i = 0; i < number; i++) { 960 - pHwData->phy_para[i] = al2230s_rf_data[i]; 961 - pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230s_rf_data[i], 20); 962 - } 963 - break; 964 - case RF_AIROHA_7230: 965 - /* Start to fill RF parameters, PLL_ON should be pulled low. */ 966 - Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000000); 967 - pr_debug("* PLL_ON low\n"); 968 - number = ARRAY_SIZE(al7230_rf_data_24); 969 - Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number); 970 - break; 971 - case RF_WB_242: 972 - case RF_WB_242_1: 973 - number = ARRAY_SIZE(w89rf242_rf_data); 974 - for (i = 0; i < number; i++) { 975 - ltmp = w89rf242_rf_data[i]; 976 - if (i == 4) { /* Update the VCO trim from EEPROM */ 977 - ltmp &= ~0xff0; /* Mask bit4 ~bit11 */ 978 - ltmp |= pHwData->VCO_trim << 4; 979 - } 980 - 981 - pHwData->phy_para[i] = ltmp; 982 - pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(ltmp, 24); 983 - } 984 - break; 985 - } 986 - 987 - pHwData->phy_number = number; 988 - 989 - /* The 16 is the maximum capability of hardware. Here use 12 */ 990 - if (number > 12) { 991 - for (i = 0; i < 12; i++) /* For Al2230 */ 992 - Wb35Reg_WriteSync(pHwData, 0x0864, pltmp[i]); 993 - 994 - pltmp += 12; 995 - number -= 12; 996 - } 997 - 998 - /* Write to register. number must less and equal than 16 */ 999 - for (i = 0; i < number; i++) 1000 - Wb35Reg_WriteSync(pHwData, 0x864, pltmp[i]); 1001 - 1002 - /* Calibration only 1 time */ 1003 - if (pHwData->CalOneTime) 1004 - return; 1005 - pHwData->CalOneTime = 1; 1006 - 1007 - switch (pHwData->phy_type) { 1008 - case RF_AIROHA_2230: 1009 - ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x07 << 20) | 0xE168E, 20); 1010 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1011 - msleep(10); 1012 - ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_rf_data[7], 20); 1013 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1014 - msleep(10); 1015 - case RF_AIROHA_2230S: 1016 - Wb35Reg_WriteSync(pHwData, 0x03d4, 0x80); /* regulator on only */ 1017 - msleep(10); 1018 - Wb35Reg_WriteSync(pHwData, 0x03d4, 0xa0); /* PLL_PD REF_PD set to 0 */ 1019 - msleep(10); 1020 - Wb35Reg_WriteSync(pHwData, 0x03d4, 0xe0); /* MLK_EN */ 1021 - Wb35Reg_WriteSync(pHwData, 0x03b0, 1); /* Reset hardware first */ 1022 - msleep(10); 1023 - /* ========================================================= */ 1024 - 1025 - /* The follow code doesn't use the burst-write mode */ 1026 - ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F<<20) | 0xF01A0, 20); 1027 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1028 - 1029 - ltmp = pHwData->reg.BB5C & 0xfffff000; 1030 - Wb35Reg_WriteSync(pHwData, 0x105c, ltmp); 1031 - pHwData->reg.BB50 |= 0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START) */ 1032 - Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50); 1033 - msleep(5); 1034 - 1035 - ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01B0, 20); 1036 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1037 - msleep(5); 1038 - 1039 - ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01E0, 20); 1040 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1041 - msleep(5); 1042 - 1043 - ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01A0, 20); 1044 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1045 - 1046 - Wb35Reg_WriteSync(pHwData, 0x105c, pHwData->reg.BB5C); 1047 - pHwData->reg.BB50 &= ~0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */ 1048 - Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50); 1049 - break; 1050 - case RF_AIROHA_7230: 1051 - /* RF parameters have filled completely, PLL_ON should be pulled high */ 1052 - Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000080); 1053 - pr_debug("* PLL_ON high\n"); 1054 - 1055 - /* 2.4GHz */ 1056 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F; 1057 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1058 - msleep(5); 1059 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F; 1060 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1061 - msleep(5); 1062 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F; 1063 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1064 - msleep(5); 1065 - 1066 - /* 5GHz */ 1067 - Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000000); 1068 - pr_debug("* PLL_ON low\n"); 1069 - 1070 - number = ARRAY_SIZE(al7230_rf_data_50); 1071 - Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number); 1072 - /* Write to register. number must less and equal than 16 */ 1073 - for (i = 0; i < number; i++) 1074 - Wb35Reg_WriteSync(pHwData, 0x0864, pltmp[i]); 1075 - msleep(5); 1076 - 1077 - Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000080); 1078 - pr_debug("* PLL_ON high\n"); 1079 - 1080 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F; 1081 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1082 - msleep(5); 1083 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F; 1084 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1085 - msleep(5); 1086 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF; 1087 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1088 - msleep(5); 1089 - break; 1090 - case RF_WB_242: 1091 - case RF_WB_242_1: 1092 - /* for FA5976A */ 1093 - ltmp = pHwData->reg.BB5C & 0xfffff000; 1094 - Wb35Reg_WriteSync(pHwData, 0x105c, ltmp); 1095 - Wb35Reg_WriteSync(pHwData, 0x1058, 0); 1096 - pHwData->reg.BB50 |= 0x3; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */ 1097 - Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50); 1098 - 1099 - /* ----- Calibration (1). VCO frequency calibration */ 1100 - /* Calibration (1a.0). Synthesizer reset */ 1101 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00101E, 24); 1102 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1103 - msleep(5); 1104 - /* Calibration (1a). VCO frequency calibration mode ; waiting 2msec VCO calibration time */ 1105 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFE69c0, 24); 1106 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1107 - msleep(2); 1108 - 1109 - /* ----- Calibration (2). TX baseband Gm-C filter auto-tuning */ 1110 - /* Calibration (2a). turn off ENCAL signal */ 1111 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF8EBC0, 24); 1112 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1113 - /* Calibration (2b.0). TX filter auto-tuning BW: TFLBW=101 (TC5376A default) */ 1114 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x07<<24) | 0x0C68CE, 24); 1115 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1116 - /* Calibration (2b). send TX reset signal */ 1117 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00201E, 24); 1118 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1119 - /* Calibration (2c). turn-on TX Gm-C filter auto-tuning */ 1120 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFCEBC0, 24); 1121 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1122 - udelay(150); /* Sleep 150 us */ 1123 - /* turn off ENCAL signal */ 1124 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF8EBC0, 24); 1125 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1126 - 1127 - /* ----- Calibration (3). RX baseband Gm-C filter auto-tuning */ 1128 - /* Calibration (3a). turn off ENCAL signal */ 1129 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24); 1130 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1131 - /* Calibration (3b.0). RX filter auto-tuning BW: RFLBW=100 (TC5376A+corner default;) */ 1132 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x07<<24) | 0x0C68CE, 24); 1133 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1134 - /* Calibration (3b). send RX reset signal */ 1135 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00401E, 24); 1136 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1137 - /* Calibration (3c). turn-on RX Gm-C filter auto-tuning */ 1138 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFEEDC0, 24); 1139 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1140 - udelay(150); /* Sleep 150 us */ 1141 - /* Calibration (3e). turn off ENCAL signal */ 1142 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24); 1143 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1144 - 1145 - /* ----- Calibration (4). TX LO leakage calibration */ 1146 - /* Calibration (4a). TX LO leakage calibration */ 1147 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFD6BC0, 24); 1148 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1149 - udelay(150); /* Sleep 150 us */ 1150 - 1151 - /* ----- Calibration (5). RX DC offset calibration */ 1152 - /* Calibration (5a). turn off ENCAL signal and set to RX SW DC calibration mode */ 1153 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24); 1154 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1155 - /* Calibration (5b). turn off AGC servo-loop & RSSI */ 1156 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x01<<24) | 0xEBFFC2, 24); 1157 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1158 - 1159 - /* for LNA=11 -------- */ 1160 - /* Calibration (5c-h). RX DC offset current bias ON; & LNA=11; RXVGA=111111 */ 1161 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x343FCC, 24); 1162 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1163 - /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */ 1164 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24); 1165 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1166 - msleep(2); 1167 - /* Calibration (5f). turn off ENCAL signal */ 1168 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24); 1169 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1170 - 1171 - /* for LNA=10 -------- */ 1172 - /* Calibration (5c-m). RX DC offset current bias ON; & LNA=10; RXVGA=111111 */ 1173 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x342FCC, 24); 1174 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1175 - /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */ 1176 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24); 1177 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1178 - msleep(2); 1179 - /* Calibration (5f). turn off ENCAL signal */ 1180 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24); 1181 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1182 - 1183 - /* for LNA=01 -------- */ 1184 - /* Calibration (5c-m). RX DC offset current bias ON; & LNA=01; RXVGA=111111 */ 1185 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x341FCC, 24); 1186 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1187 - /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */ 1188 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24); 1189 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1190 - msleep(2); 1191 - /* Calibration (5f). turn off ENCAL signal */ 1192 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24); 1193 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1194 - 1195 - /* for LNA=00 -------- */ 1196 - /* Calibration (5c-l). RX DC offset current bias ON; & LNA=00; RXVGA=111111 */ 1197 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x340FCC, 24); 1198 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1199 - /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */ 1200 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24); 1201 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1202 - msleep(2); 1203 - /* Calibration (5f). turn off ENCAL signal */ 1204 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24); 1205 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1206 - /* Calibration (5g). turn on AGC servo-loop */ 1207 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x01<<24) | 0xEFFFC2, 24); 1208 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1209 - 1210 - /* ----- Calibration (7). Switch RF chip to normal mode */ 1211 - /* 0x00 0xF86100 ; 3E184 ; Switch RF chip to normal mode */ 1212 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF86100, 24); 1213 - Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); 1214 - msleep(5); 1215 - break; 1216 - } 1217 - } 1218 - 1219 - static void BBProcessor_AL7230_2400(struct hw_data *pHwData) 1220 - { 1221 - struct wb35_reg *reg = &pHwData->reg; 1222 - u32 pltmp[12]; 1223 - 1224 - pltmp[0] = 0x16A8337A; /* 0x1000 AGC_Ctrl1 */ 1225 - pltmp[1] = 0x9AFF9AA6; /* 0x1004 AGC_Ctrl2 */ 1226 - pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */ 1227 - pltmp[3] = 0xFFF72031; /* 0x100c AGC_Ctrl4 */ 1228 - reg->BB0C = 0xFFF72031; 1229 - pltmp[4] = 0x0FacDCC5; /* 0x1010 AGC_Ctrl5 */ 1230 - pltmp[5] = 0x00CAA333; /* 0x1014 AGC_Ctrl6 */ 1231 - pltmp[6] = 0xF2211111; /* 0x1018 AGC_Ctrl7 */ 1232 - pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ 1233 - pltmp[8] = 0x06443440; /* 0x1020 AGC_Ctrl9 */ 1234 - pltmp[9] = 0xA8002A79; /* 0x1024 AGC_Ctrl10 */ 1235 - pltmp[10] = 0x40000528; 1236 - pltmp[11] = 0x232D7F30; /* 0x102c A_ACQ_Ctrl */ 1237 - reg->BB2C = 0x232D7F30; 1238 - Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); 1239 - 1240 - pltmp[0] = 0x00002c54; /* 0x1030 B_ACQ_Ctrl */ 1241 - reg->BB30 = 0x00002c54; 1242 - pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ 1243 - pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */ 1244 - pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */ 1245 - reg->BB3C = 0x00000000; 1246 - pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ 1247 - pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ 1248 - pltmp[6] = 0x00332C1B; /* 0x1048 11b TX RC filter */ 1249 - pltmp[7] = 0x0A00FEFF; /* 0x104c 11b TX RC filter */ 1250 - pltmp[8] = 0x2B106208; /* 0x1050 MODE_Ctrl */ 1251 - reg->BB50 = 0x2B106208; 1252 - pltmp[9] = 0; /* 0x1054 */ 1253 - reg->BB54 = 0x00000000; 1254 - pltmp[10] = 0x52524242; /* 0x1058 IQ_Alpha */ 1255 - reg->BB58 = 0x52524242; 1256 - pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */ 1257 - Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); 1258 - } 1259 - 1260 - static void BBProcessor_AL7230_5000(struct hw_data *pHwData) 1261 - { 1262 - struct wb35_reg *reg = &pHwData->reg; 1263 - u32 pltmp[12]; 1264 - 1265 - pltmp[0] = 0x16AA6678; /* 0x1000 AGC_Ctrl1 */ 1266 - pltmp[1] = 0x9AFFA0B2; /* 0x1004 AGC_Ctrl2 */ 1267 - pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */ 1268 - pltmp[3] = 0xEFFF233E; /* 0x100c AGC_Ctrl4 */ 1269 - reg->BB0C = 0xEFFF233E; 1270 - pltmp[4] = 0x0FacDCC5; /* 0x1010 AGC_Ctrl5 */ 1271 - pltmp[5] = 0x00CAA333; /* 0x1014 AGC_Ctrl6 */ 1272 - pltmp[6] = 0xF2432111; /* 0x1018 AGC_Ctrl7 */ 1273 - pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ 1274 - pltmp[8] = 0x05C43440; /* 0x1020 AGC_Ctrl9 */ 1275 - pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */ 1276 - pltmp[10] = 0x40000528; 1277 - pltmp[11] = 0x232FDF30;/* 0x102c A_ACQ_Ctrl */ 1278 - reg->BB2C = 0x232FDF30; 1279 - Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); 1280 - 1281 - pltmp[0] = 0x80002C7C; /* 0x1030 B_ACQ_Ctrl */ 1282 - pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ 1283 - pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */ 1284 - pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */ 1285 - reg->BB3C = 0x00000000; 1286 - pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ 1287 - pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ 1288 - pltmp[6] = 0x00332C1B; /* 0x1048 11b TX RC filter */ 1289 - pltmp[7] = 0x0A00FEFF; /* 0x104c 11b TX RC filter */ 1290 - pltmp[8] = 0x2B107208; /* 0x1050 MODE_Ctrl */ 1291 - reg->BB50 = 0x2B107208; 1292 - pltmp[9] = 0; /* 0x1054 */ 1293 - reg->BB54 = 0x00000000; 1294 - pltmp[10] = 0x52524242; /* 0x1058 IQ_Alpha */ 1295 - reg->BB58 = 0x52524242; 1296 - pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */ 1297 - Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); 1298 - } 1299 - 1300 - /* 1301 - * =========================================================================== 1302 - * BBProcessorPowerupInit -- 1303 - * 1304 - * Description: 1305 - * Initialize the Baseband processor. 1306 - * 1307 - * Arguments: 1308 - * pHwData - Handle of the USB Device. 1309 - * 1310 - * Return values: 1311 - * None. 1312 - *============================================================================ 1313 - */ 1314 - void BBProcessor_initial(struct hw_data *pHwData) 1315 - { 1316 - struct wb35_reg *reg = &pHwData->reg; 1317 - u32 i, pltmp[12]; 1318 - 1319 - switch (pHwData->phy_type) { 1320 - case RF_MAXIM_V1: /* Initializng the Winbond 2nd BB(with Phy board (v1) + Maxim 331) */ 1321 - pltmp[0] = 0x16F47E77; /* 0x1000 AGC_Ctrl1 */ 1322 - pltmp[1] = 0x9AFFAEA4; /* 0x1004 AGC_Ctrl2 */ 1323 - pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */ 1324 - pltmp[3] = 0xEFFF1A34; /* 0x100c AGC_Ctrl4 */ 1325 - reg->BB0C = 0xEFFF1A34; 1326 - pltmp[4] = 0x0FABE0B7; /* 0x1010 AGC_Ctrl5 */ 1327 - pltmp[5] = 0x00CAA332; /* 0x1014 AGC_Ctrl6 */ 1328 - pltmp[6] = 0xF6632111; /* 0x1018 AGC_Ctrl7 */ 1329 - pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ 1330 - pltmp[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */ 1331 - pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */ 1332 - pltmp[10] = (pHwData->phy_type == 3) ? 0x40000a28 : 0x40000228; /* 0x1028 MAXIM_331(b31=0) + WBRF_V1(b11=1) : MAXIM_331(b31=0) + WBRF_V2(b11=0) */ 1333 - pltmp[11] = 0x232FDF30; /* 0x102c A_ACQ_Ctrl */ 1334 - reg->BB2C = 0x232FDF30; /* Modify for 33's 1.0.95.xxx version, antenna 1 */ 1335 - Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); 1336 - 1337 - pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */ 1338 - reg->BB30 = 0x00002C54; 1339 - pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ 1340 - pltmp[2] = 0x5B6C8769; /* 0x1038 B_TXRX_Ctrl */ 1341 - pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */ 1342 - reg->BB3C = 0x00000000; 1343 - pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ 1344 - pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ 1345 - pltmp[6] = 0x00453B24; /* 0x1048 11b TX RC filter */ 1346 - pltmp[7] = 0x0E00FEFF; /* 0x104c 11b TX RC filter */ 1347 - pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */ 1348 - reg->BB50 = 0x27106208; 1349 - pltmp[9] = 0; /* 0x1054 */ 1350 - reg->BB54 = 0x00000000; 1351 - pltmp[10] = 0x64646464; /* 0x1058 IQ_Alpha */ 1352 - reg->BB58 = 0x64646464; 1353 - pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */ 1354 - Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); 1355 - 1356 - Wb35Reg_Write(pHwData, 0x1070, 0x00000045); 1357 - break; 1358 - 1359 - case RF_MAXIM_2825: 1360 - case RF_MAXIM_2827: 1361 - case RF_MAXIM_2828: 1362 - pltmp[0] = 0x16b47e77; /* 0x1000 AGC_Ctrl1 */ 1363 - pltmp[1] = 0x9affaea4; /* 0x1004 AGC_Ctrl2 */ 1364 - pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */ 1365 - pltmp[3] = 0xefff1a34; /* 0x100c AGC_Ctrl4 */ 1366 - reg->BB0C = 0xefff1a34; 1367 - pltmp[4] = 0x0fabe0b7; /* 0x1010 AGC_Ctrl5 */ 1368 - pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */ 1369 - pltmp[6] = 0xf6632111; /* 0x1018 AGC_Ctrl7 */ 1370 - pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ 1371 - pltmp[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */ 1372 - pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */ 1373 - pltmp[10] = 0x40000528; 1374 - pltmp[11] = 0x232fdf30; /* 0x102c A_ACQ_Ctrl */ 1375 - reg->BB2C = 0x232fdf30; /* antenna 1 */ 1376 - Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); 1377 - 1378 - pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */ 1379 - reg->BB30 = 0x00002C54; 1380 - pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ 1381 - pltmp[2] = 0x5B6C8769; /* 0x1038 B_TXRX_Ctrl */ 1382 - pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */ 1383 - reg->BB3C = 0x00000000; 1384 - pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ 1385 - pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ 1386 - pltmp[6] = 0x00453B24; /* 0x1048 11b TX RC filter */ 1387 - pltmp[7] = 0x0D00FDFF; /* 0x104c 11b TX RC filter */ 1388 - pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */ 1389 - reg->BB50 = 0x27106208; 1390 - pltmp[9] = 0; /* 0x1054 */ 1391 - reg->BB54 = 0x00000000; 1392 - pltmp[10] = 0x64646464; /* 0x1058 IQ_Alpha */ 1393 - reg->BB58 = 0x64646464; 1394 - pltmp[11] = 0xAA28C000; /* 0x105c DC_Cancel */ 1395 - Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); 1396 - 1397 - Wb35Reg_Write(pHwData, 0x1070, 0x00000045); 1398 - break; 1399 - 1400 - case RF_MAXIM_2829: 1401 - pltmp[0] = 0x16b47e77; /* 0x1000 AGC_Ctrl1 */ 1402 - pltmp[1] = 0x9affaea4; /* 0x1004 AGC_Ctrl2 */ 1403 - pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */ 1404 - pltmp[3] = 0xf4ff1632; /* 0x100c AGC_Ctrl4 */ 1405 - reg->BB0C = 0xf4ff1632; 1406 - pltmp[4] = 0x0fabe0b7; /* 0x1010 AGC_Ctrl5 */ 1407 - pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */ 1408 - pltmp[6] = 0xf8632112; /* 0x1018 AGC_Ctrl7 */ 1409 - pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ 1410 - pltmp[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */ 1411 - pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */ 1412 - pltmp[10] = 0x40000528; 1413 - pltmp[11] = 0x232fdf30; /* 0x102c A_ACQ_Ctrl */ 1414 - reg->BB2C = 0x232fdf30; /* antenna 1 */ 1415 - Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); 1416 - 1417 - pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */ 1418 - reg->BB30 = 0x00002C54; 1419 - pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ 1420 - pltmp[2] = 0x5b2c8769; /* 0x1038 B_TXRX_Ctrl */ 1421 - pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */ 1422 - reg->BB3C = 0x00000000; 1423 - pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ 1424 - pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ 1425 - pltmp[6] = 0x002c2617; /* 0x1048 11b TX RC filter */ 1426 - pltmp[7] = 0x0800feff; /* 0x104c 11b TX RC filter */ 1427 - pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */ 1428 - reg->BB50 = 0x27106208; 1429 - pltmp[9] = 0; /* 0x1054 */ 1430 - reg->BB54 = 0x00000000; 1431 - pltmp[10] = 0x64644a4a; /* 0x1058 IQ_Alpha */ 1432 - reg->BB58 = 0x64646464; 1433 - pltmp[11] = 0xAA28C000; /* 0x105c DC_Cancel */ 1434 - Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); 1435 - Wb35Reg_Write(pHwData, 0x1070, 0x00000045); 1436 - break; 1437 - case RF_AIROHA_2230: 1438 - pltmp[0] = 0X16764A77; /* 0x1000 AGC_Ctrl1 */ 1439 - pltmp[1] = 0x9affafb2; /* 0x1004 AGC_Ctrl2 */ 1440 - pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */ 1441 - pltmp[3] = 0xFFFd203c; /* 0x100c AGC_Ctrl4 */ 1442 - reg->BB0C = 0xFFFd203c; 1443 - pltmp[4] = 0X0FBFDCc5; /* 0x1010 AGC_Ctrl5 */ 1444 - pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */ 1445 - pltmp[6] = 0XF6632111; /* 0x1018 AGC_Ctrl7 */ 1446 - pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ 1447 - pltmp[8] = 0x04C43640; /* 0x1020 AGC_Ctrl9 */ 1448 - pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */ 1449 - pltmp[10] = 0X40000528; 1450 - pltmp[11] = 0x232dfF30; /* 0x102c A_ACQ_Ctrl */ 1451 - reg->BB2C = 0x232dfF30; /* antenna 1 */ 1452 - Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); 1453 - 1454 - pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */ 1455 - reg->BB30 = 0x00002C54; 1456 - pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ 1457 - pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */ 1458 - pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */ 1459 - reg->BB3C = 0x00000000; 1460 - pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ 1461 - pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ 1462 - pltmp[6] = BB48_DEFAULT_AL2230_11G; /* 0x1048 11b TX RC filter */ 1463 - reg->BB48 = BB48_DEFAULT_AL2230_11G; /* 20051221 ch14 */ 1464 - pltmp[7] = BB4C_DEFAULT_AL2230_11G; /* 0x104c 11b TX RC filter */ 1465 - reg->BB4C = BB4C_DEFAULT_AL2230_11G; 1466 - pltmp[8] = 0x27106200; /* 0x1050 MODE_Ctrl */ 1467 - reg->BB50 = 0x27106200; 1468 - pltmp[9] = 0; /* 0x1054 */ 1469 - reg->BB54 = 0x00000000; 1470 - pltmp[10] = 0x52524242; /* 0x1058 IQ_Alpha */ 1471 - reg->BB58 = 0x52524242; 1472 - pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */ 1473 - Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); 1474 - 1475 - Wb35Reg_Write(pHwData, 0x1070, 0x00000045); 1476 - break; 1477 - case RF_AIROHA_2230S: 1478 - pltmp[0] = 0X16764A77; /* 0x1000 AGC_Ctrl1 */ 1479 - pltmp[1] = 0x9affafb2; /* 0x1004 AGC_Ctrl2 */ 1480 - pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */ 1481 - pltmp[3] = 0xFFFd203c; /* 0x100c AGC_Ctrl4 */ 1482 - reg->BB0C = 0xFFFd203c; 1483 - pltmp[4] = 0X0FBFDCc5; /* 0x1010 AGC_Ctrl5 */ 1484 - pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */ 1485 - pltmp[6] = 0XF6632111; /* 0x1018 AGC_Ctrl7 */ 1486 - pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ 1487 - pltmp[8] = 0x04C43640; /* 0x1020 AGC_Ctrl9 */ 1488 - pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */ 1489 - pltmp[10] = 0X40000528; 1490 - pltmp[11] = 0x232dfF30; /* 0x102c A_ACQ_Ctrl */ 1491 - reg->BB2C = 0x232dfF30; /* antenna 1 */ 1492 - Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); 1493 - 1494 - pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */ 1495 - reg->BB30 = 0x00002C54; 1496 - pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ 1497 - pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */ 1498 - pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */ 1499 - reg->BB3C = 0x00000000; 1500 - pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ 1501 - pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ 1502 - pltmp[6] = BB48_DEFAULT_AL2230_11G; /* 0x1048 11b TX RC filter */ 1503 - reg->BB48 = BB48_DEFAULT_AL2230_11G; /* ch14 */ 1504 - pltmp[7] = BB4C_DEFAULT_AL2230_11G; /* 0x104c 11b TX RC filter */ 1505 - reg->BB4C = BB4C_DEFAULT_AL2230_11G; 1506 - pltmp[8] = 0x27106200; /* 0x1050 MODE_Ctrl */ 1507 - reg->BB50 = 0x27106200; 1508 - pltmp[9] = 0; /* 0x1054 */ 1509 - reg->BB54 = 0x00000000; 1510 - pltmp[10] = 0x52523232; /* 0x1058 IQ_Alpha */ 1511 - reg->BB58 = 0x52523232; 1512 - pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */ 1513 - Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); 1514 - 1515 - Wb35Reg_Write(pHwData, 0x1070, 0x00000045); 1516 - break; 1517 - case RF_AIROHA_7230: 1518 - BBProcessor_AL7230_2400(pHwData); 1519 - 1520 - Wb35Reg_Write(pHwData, 0x1070, 0x00000045); 1521 - break; 1522 - case RF_WB_242: 1523 - case RF_WB_242_1: 1524 - pltmp[0] = 0x16A8525D; /* 0x1000 AGC_Ctrl1 */ 1525 - pltmp[1] = 0x9AFF9ABA; /* 0x1004 AGC_Ctrl2 */ 1526 - pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */ 1527 - pltmp[3] = 0xEEE91C32; /* 0x100c AGC_Ctrl4 */ 1528 - reg->BB0C = 0xEEE91C32; 1529 - pltmp[4] = 0x0FACDCC5; /* 0x1010 AGC_Ctrl5 */ 1530 - pltmp[5] = 0x000AA344; /* 0x1014 AGC_Ctrl6 */ 1531 - pltmp[6] = 0x22222221; /* 0x1018 AGC_Ctrl7 */ 1532 - pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ 1533 - pltmp[8] = 0x04CC3440; /* 0x1020 AGC_Ctrl9 */ 1534 - pltmp[9] = 0xA9002A79; /* 0x1024 AGC_Ctrl10 */ 1535 - pltmp[10] = 0x40000528; /* 0x1028 */ 1536 - pltmp[11] = 0x23457F30; /* 0x102c A_ACQ_Ctrl */ 1537 - reg->BB2C = 0x23457F30; 1538 - Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); 1539 - 1540 - pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */ 1541 - reg->BB30 = 0x00002C54; 1542 - pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ 1543 - pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */ 1544 - pltmp[3] = pHwData->BB3c_cal; /* 0x103c 11a TX LS filter */ 1545 - reg->BB3C = pHwData->BB3c_cal; 1546 - pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ 1547 - pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ 1548 - pltmp[6] = BB48_DEFAULT_WB242_11G; /* 0x1048 11b TX RC filter */ 1549 - reg->BB48 = BB48_DEFAULT_WB242_11G; 1550 - pltmp[7] = BB4C_DEFAULT_WB242_11G; /* 0x104c 11b TX RC filter */ 1551 - reg->BB4C = BB4C_DEFAULT_WB242_11G; 1552 - pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */ 1553 - reg->BB50 = 0x27106208; 1554 - pltmp[9] = pHwData->BB54_cal; /* 0x1054 */ 1555 - reg->BB54 = pHwData->BB54_cal; 1556 - pltmp[10] = 0x52523131; /* 0x1058 IQ_Alpha */ 1557 - reg->BB58 = 0x52523131; 1558 - pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */ 1559 - Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); 1560 - 1561 - Wb35Reg_Write(pHwData, 0x1070, 0x00000045); 1562 - break; 1563 - } 1564 - 1565 - /* Fill the LNA table */ 1566 - reg->LNAValue[0] = (u8) (reg->BB0C & 0xff); 1567 - reg->LNAValue[1] = 0; 1568 - reg->LNAValue[2] = (u8) ((reg->BB0C & 0xff00) >> 8); 1569 - reg->LNAValue[3] = 0; 1570 - 1571 - /* Fill SQ3 table */ 1572 - for (i = 0; i < MAX_SQ3_FILTER_SIZE; i++) 1573 - reg->SQ3_filter[i] = 0x2f; /* half of Bit 0 ~ 6 */ 1574 - } 1575 - 1576 - static inline void set_tx_power_per_channel_max2829(struct hw_data *pHwData, 1577 - struct chan_info Channel) 1578 - { 1579 - RFSynthesizer_SetPowerIndex(pHwData, 100); 1580 - } 1581 - 1582 - static void set_tx_power_per_channel_al2230(struct hw_data *pHwData, 1583 - struct chan_info Channel) 1584 - { 1585 - u8 index = 100; 1586 - if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) 1587 - index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; 1588 - 1589 - RFSynthesizer_SetPowerIndex(pHwData, index); 1590 - } 1591 - 1592 - static void set_tx_power_per_channel_al7230(struct hw_data *pHwData, 1593 - struct chan_info Channel) 1594 - { 1595 - u8 i, index = 100; 1596 - 1597 - switch (Channel.band) { 1598 - case BAND_TYPE_DSSS: 1599 - case BAND_TYPE_OFDM_24: 1600 - if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) 1601 - index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; 1602 - break; 1603 - case BAND_TYPE_OFDM_5: 1604 - for (i = 0; i < 35; i++) { 1605 - if (Channel.ChanNo == pHwData->TxVgaFor50[i].ChanNo) { 1606 - if (pHwData->TxVgaFor50[i].TxVgaValue != 0xff) 1607 - index = pHwData->TxVgaFor50[i].TxVgaValue; 1608 - break; 1609 - } 1610 - } 1611 - break; 1612 - } 1613 - RFSynthesizer_SetPowerIndex(pHwData, index); 1614 - } 1615 - 1616 - static void set_tx_power_per_channel_wb242(struct hw_data *pHwData, 1617 - struct chan_info Channel) 1618 - { 1619 - u8 index = 100; 1620 - 1621 - switch (Channel.band) { 1622 - case BAND_TYPE_DSSS: 1623 - case BAND_TYPE_OFDM_24: 1624 - if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) 1625 - index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; 1626 - break; 1627 - case BAND_TYPE_OFDM_5: 1628 - break; 1629 - } 1630 - RFSynthesizer_SetPowerIndex(pHwData, index); 1631 - } 1632 - 1633 - /* 1634 - * ========================================================================== 1635 - * RFSynthesizer_SwitchingChannel -- 1636 - * 1637 - * Description: 1638 - * Swithch the RF channel. 1639 - * 1640 - * Arguments: 1641 - * pHwData - Handle of the USB Device. 1642 - * Channel - The channel no. 1643 - * 1644 - * Return values: 1645 - * None. 1646 - * =========================================================================== 1647 - */ 1648 - void RFSynthesizer_SwitchingChannel(struct hw_data *pHwData, struct chan_info Channel) 1649 - { 1650 - struct wb35_reg *reg = &pHwData->reg; 1651 - u32 pltmp[16]; /* The 16 is the maximum capability of hardware */ 1652 - u32 count, ltmp; 1653 - u8 i, j, number; 1654 - u8 ChnlTmp; 1655 - 1656 - switch (pHwData->phy_type) { 1657 - case RF_MAXIM_2825: 1658 - case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */ 1659 - 1660 - if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 13 */ 1661 - for (i = 0; i < 3; i++) 1662 - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_channel_data_24[Channel.ChanNo-1][i], 18); 1663 - Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); 1664 - } 1665 - RFSynthesizer_SetPowerIndex(pHwData, 100); 1666 - break; 1667 - case RF_MAXIM_2827: 1668 - if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 13 */ 1669 - for (i = 0; i < 3; i++) 1670 - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_channel_data_24[Channel.ChanNo-1][i], 18); 1671 - Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); 1672 - } else if (Channel.band == BAND_TYPE_OFDM_5) { /* channel 36 ~ 64 */ 1673 - ChnlTmp = (Channel.ChanNo - 36) / 4; 1674 - for (i = 0; i < 3; i++) 1675 - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_channel_data_50[ChnlTmp][i], 18); 1676 - Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); 1677 - } 1678 - RFSynthesizer_SetPowerIndex(pHwData, 100); 1679 - break; 1680 - case RF_MAXIM_2828: 1681 - if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 13 */ 1682 - for (i = 0; i < 3; i++) 1683 - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_channel_data_24[Channel.ChanNo-1][i], 18); 1684 - Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); 1685 - } else if (Channel.band == BAND_TYPE_OFDM_5) { /* channel 36 ~ 64 */ 1686 - ChnlTmp = (Channel.ChanNo - 36) / 4; 1687 - for (i = 0; i < 3; i++) 1688 - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_channel_data_50[ChnlTmp][i], 18); 1689 - Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); 1690 - } 1691 - RFSynthesizer_SetPowerIndex(pHwData, 100); 1692 - break; 1693 - case RF_MAXIM_2829: 1694 - if (Channel.band <= BAND_TYPE_OFDM_24) { 1695 - for (i = 0; i < 3; i++) 1696 - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_channel_data_24[Channel.ChanNo-1][i], 18); 1697 - Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); 1698 - } else if (Channel.band == BAND_TYPE_OFDM_5) { 1699 - count = ARRAY_SIZE(max2829_channel_data_50); 1700 - 1701 - for (i = 0; i < count; i++) { 1702 - if (max2829_channel_data_50[i][0] == Channel.ChanNo) { 1703 - for (j = 0; j < 3; j++) 1704 - pltmp[j] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_channel_data_50[i][j+1], 18); 1705 - Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); 1706 - 1707 - if ((max2829_channel_data_50[i][3] & 0x3FFFF) == 0x2A946) { 1708 - ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse((5 << 18) | 0x2A906, 18); 1709 - Wb35Reg_Write(pHwData, 0x0864, ltmp); 1710 - } else { /* 0x2A9C6 */ 1711 - ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse((5 << 18) | 0x2A986, 18); 1712 - Wb35Reg_Write(pHwData, 0x0864, ltmp); 1713 - } 1714 - } 1715 - } 1716 - } 1717 - set_tx_power_per_channel_max2829(pHwData, Channel); 1718 - break; 1719 - case RF_AIROHA_2230: 1720 - case RF_AIROHA_2230S: 1721 - if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 14 */ 1722 - for (i = 0; i < 2; i++) 1723 - pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_channel_data_24[Channel.ChanNo-1][i], 20); 1724 - Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 2, NO_INCREMENT); 1725 - } 1726 - set_tx_power_per_channel_al2230(pHwData, Channel); 1727 - break; 1728 - case RF_AIROHA_7230: 1729 - /* Channel independent registers */ 1730 - if (Channel.band != pHwData->band) { 1731 - if (Channel.band <= BAND_TYPE_OFDM_24) { 1732 - /* Update BB register */ 1733 - BBProcessor_AL7230_2400(pHwData); 1734 - 1735 - number = ARRAY_SIZE(al7230_rf_data_24); 1736 - Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number); 1737 - } else { 1738 - /* Update BB register */ 1739 - BBProcessor_AL7230_5000(pHwData); 1740 - 1741 - number = ARRAY_SIZE(al7230_rf_data_50); 1742 - Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number); 1743 - } 1744 - 1745 - /* Write to register. number must less and equal than 16 */ 1746 - Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, number, NO_INCREMENT); 1747 - pr_debug("Band changed\n"); 1748 - } 1749 - 1750 - if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 14 */ 1751 - for (i = 0; i < 2; i++) 1752 - pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_24[Channel.ChanNo-1][i]&0xffffff); 1753 - Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 2, NO_INCREMENT); 1754 - } else if (Channel.band == BAND_TYPE_OFDM_5) { 1755 - /* Update Reg12 */ 1756 - if ((Channel.ChanNo > 64) && (Channel.ChanNo <= 165)) { 1757 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00143c; 1758 - Wb35Reg_Write(pHwData, 0x0864, ltmp); 1759 - } else { /* reg12 = 0x00147c at Channel 4920 ~ 5320 */ 1760 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00147c; 1761 - Wb35Reg_Write(pHwData, 0x0864, ltmp); 1762 - } 1763 - 1764 - count = ARRAY_SIZE(al7230_channel_data_5); 1765 - 1766 - for (i = 0; i < count; i++) { 1767 - if (al7230_channel_data_5[i][0] == Channel.ChanNo) { 1768 - for (j = 0; j < 3; j++) 1769 - pltmp[j] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_5[i][j+1] & 0xffffff); 1770 - Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); 1771 - } 1772 - } 1773 - } 1774 - set_tx_power_per_channel_al7230(pHwData, Channel); 1775 - break; 1776 - case RF_WB_242: 1777 - case RF_WB_242_1: 1778 - 1779 - if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 14 */ 1780 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(w89rf242_channel_data_24[Channel.ChanNo-1][0], 24); 1781 - Wb35Reg_Write(pHwData, 0x864, ltmp); 1782 - } 1783 - set_tx_power_per_channel_wb242(pHwData, Channel); 1784 - break; 1785 - } 1786 - 1787 - if (Channel.band <= BAND_TYPE_OFDM_24) { 1788 - /* BB: select 2.4 GHz, bit[12-11]=00 */ 1789 - reg->BB50 &= ~(BIT(11) | BIT(12)); 1790 - Wb35Reg_Write(pHwData, 0x1050, reg->BB50); /* MODE_Ctrl */ 1791 - /* MAC: select 2.4 GHz, bit[5]=0 */ 1792 - reg->M78_ERPInformation &= ~BIT(5); 1793 - Wb35Reg_Write(pHwData, 0x0878, reg->M78_ERPInformation); 1794 - /* enable 11b Baseband */ 1795 - reg->BB30 &= ~BIT(31); 1796 - Wb35Reg_Write(pHwData, 0x1030, reg->BB30); 1797 - } else if (Channel.band == BAND_TYPE_OFDM_5) { 1798 - /* BB: select 5 GHz */ 1799 - reg->BB50 &= ~(BIT(11) | BIT(12)); 1800 - if (Channel.ChanNo <= 64) 1801 - reg->BB50 |= BIT(12); /* 10-5.25GHz */ 1802 - else if ((Channel.ChanNo >= 100) && (Channel.ChanNo <= 124)) 1803 - reg->BB50 |= BIT(11); /* 01-5.48GHz */ 1804 - else if ((Channel.ChanNo >= 128) && (Channel.ChanNo <= 161)) 1805 - reg->BB50 |= (BIT(12) | BIT(11)); /* 11-5.775GHz */ 1806 - else /* Chan 184 ~ 196 will use bit[12-11] = 10 in version sh-src-1.2.25 */ 1807 - reg->BB50 |= BIT(12); 1808 - Wb35Reg_Write(pHwData, 0x1050, reg->BB50); /* MODE_Ctrl */ 1809 - 1810 - /* (1) M78 should alway use 2.4G setting when using RF_AIROHA_7230 */ 1811 - /* (2) BB30 has been updated previously. */ 1812 - if (pHwData->phy_type != RF_AIROHA_7230) { 1813 - /* MAC: select 5 GHz, bit[5]=1 */ 1814 - reg->M78_ERPInformation |= BIT(5); 1815 - Wb35Reg_Write(pHwData, 0x0878, reg->M78_ERPInformation); 1816 - 1817 - /* disable 11b Baseband */ 1818 - reg->BB30 |= BIT(31); 1819 - Wb35Reg_Write(pHwData, 0x1030, reg->BB30); 1820 - } 1821 - } 1822 - } 1823 - 1824 - /* 1825 - * Set the tx power directly from DUT GUI, not from the EEPROM. 1826 - * Return the current setting 1827 - */ 1828 - u8 RFSynthesizer_SetPowerIndex(struct hw_data *pHwData, u8 PowerIndex) 1829 - { 1830 - u32 Band = pHwData->band; 1831 - u8 index = 0; 1832 - 1833 - if (pHwData->power_index == PowerIndex) 1834 - return PowerIndex; 1835 - 1836 - if (RF_MAXIM_2825 == pHwData->phy_type) { 1837 - /* Channel 1 - 13 */ 1838 - index = RFSynthesizer_SetMaxim2825Power(pHwData, PowerIndex); 1839 - } else if (RF_MAXIM_2827 == pHwData->phy_type) { 1840 - if (Band <= BAND_TYPE_OFDM_24) /* Channel 1 - 13 */ 1841 - index = RFSynthesizer_SetMaxim2827_24Power(pHwData, PowerIndex); 1842 - else /* Channel 36 - 64 */ 1843 - index = RFSynthesizer_SetMaxim2827_50Power(pHwData, PowerIndex); 1844 - } else if (RF_MAXIM_2828 == pHwData->phy_type) { 1845 - if (Band <= BAND_TYPE_OFDM_24) /* Channel 1 - 13 */ 1846 - index = RFSynthesizer_SetMaxim2828_24Power(pHwData, PowerIndex); 1847 - else /* Channel 36 - 64 */ 1848 - index = RFSynthesizer_SetMaxim2828_50Power(pHwData, PowerIndex); 1849 - } else if (RF_AIROHA_2230 == pHwData->phy_type) { 1850 - /* Power index: 0 ~ 63 --- Channel 1 - 14 */ 1851 - index = RFSynthesizer_SetAiroha2230Power(pHwData, PowerIndex); 1852 - index = (u8) al2230_txvga_data[index][1]; 1853 - } else if (RF_AIROHA_2230S == pHwData->phy_type) { 1854 - /* Power index: 0 ~ 63 --- Channel 1 - 14 */ 1855 - index = RFSynthesizer_SetAiroha2230Power(pHwData, PowerIndex); 1856 - index = (u8) al2230_txvga_data[index][1]; 1857 - } else if (RF_AIROHA_7230 == pHwData->phy_type) { 1858 - /* Power index: 0 ~ 63 */ 1859 - index = RFSynthesizer_SetAiroha7230Power(pHwData, PowerIndex); 1860 - index = (u8)al7230_txvga_data[index][1]; 1861 - } else if ((RF_WB_242 == pHwData->phy_type) || 1862 - (RF_WB_242_1 == pHwData->phy_type)) { 1863 - /* Power index: 0 ~ 19 for original. New range is 0 ~ 33 */ 1864 - index = RFSynthesizer_SetWinbond242Power(pHwData, PowerIndex); 1865 - index = (u8)w89rf242_txvga_data[index][1]; 1866 - } 1867 - 1868 - pHwData->power_index = index; /* Backup current */ 1869 - return index; 1870 - } 1871 - 1872 - /* -- Sub function */ 1873 - u8 RFSynthesizer_SetMaxim2828_24Power(struct hw_data *pHwData, u8 index) 1874 - { 1875 - u32 PowerData; 1876 - if (index > 1) 1877 - index = 1; 1878 - PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_power_data_24[index], 18); 1879 - Wb35Reg_Write(pHwData, 0x0864, PowerData); 1880 - return index; 1881 - } 1882 - 1883 - u8 RFSynthesizer_SetMaxim2828_50Power(struct hw_data *pHwData, u8 index) 1884 - { 1885 - u32 PowerData; 1886 - if (index > 1) 1887 - index = 1; 1888 - PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_power_data_50[index], 18); 1889 - Wb35Reg_Write(pHwData, 0x0864, PowerData); 1890 - return index; 1891 - } 1892 - 1893 - u8 RFSynthesizer_SetMaxim2827_24Power(struct hw_data *pHwData, u8 index) 1894 - { 1895 - u32 PowerData; 1896 - if (index > 1) 1897 - index = 1; 1898 - PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_power_data_24[index], 18); 1899 - Wb35Reg_Write(pHwData, 0x0864, PowerData); 1900 - return index; 1901 - } 1902 - 1903 - u8 RFSynthesizer_SetMaxim2827_50Power(struct hw_data *pHwData, u8 index) 1904 - { 1905 - u32 PowerData; 1906 - if (index > 1) 1907 - index = 1; 1908 - PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_power_data_50[index], 18); 1909 - Wb35Reg_Write(pHwData, 0x0864, PowerData); 1910 - return index; 1911 - } 1912 - 1913 - u8 RFSynthesizer_SetMaxim2825Power(struct hw_data *pHwData, u8 index) 1914 - { 1915 - u32 PowerData; 1916 - if (index > 1) 1917 - index = 1; 1918 - PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_power_data_24[index], 18); 1919 - Wb35Reg_Write(pHwData, 0x0864, PowerData); 1920 - return index; 1921 - } 1922 - 1923 - u8 RFSynthesizer_SetAiroha2230Power(struct hw_data *pHwData, u8 index) 1924 - { 1925 - u32 PowerData; 1926 - u8 i, count; 1927 - 1928 - count = ARRAY_SIZE(al2230_txvga_data); 1929 - for (i = 0; i < count; i++) { 1930 - if (al2230_txvga_data[i][1] >= index) 1931 - break; 1932 - } 1933 - if (i == count) 1934 - i--; 1935 - 1936 - PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_txvga_data[i][0], 20); 1937 - Wb35Reg_Write(pHwData, 0x0864, PowerData); 1938 - return i; 1939 - } 1940 - 1941 - u8 RFSynthesizer_SetAiroha7230Power(struct hw_data *pHwData, u8 index) 1942 - { 1943 - u32 PowerData; 1944 - u8 i, count; 1945 - 1946 - count = ARRAY_SIZE(al7230_txvga_data); 1947 - for (i = 0; i < count; i++) { 1948 - if (al7230_txvga_data[i][1] >= index) 1949 - break; 1950 - } 1951 - if (i == count) 1952 - i--; 1953 - PowerData = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_txvga_data[i][0] & 0xffffff); 1954 - Wb35Reg_Write(pHwData, 0x0864, PowerData); 1955 - return i; 1956 - } 1957 - 1958 - u8 RFSynthesizer_SetWinbond242Power(struct hw_data *pHwData, u8 index) 1959 - { 1960 - u32 PowerData; 1961 - u8 i, count; 1962 - 1963 - count = ARRAY_SIZE(w89rf242_txvga_data); 1964 - for (i = 0; i < count; i++) { 1965 - if (w89rf242_txvga_data[i][1] >= index) 1966 - break; 1967 - } 1968 - if (i == count) 1969 - i--; 1970 - 1971 - /* Set TxVga into RF */ 1972 - PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(w89rf242_txvga_data[i][0], 24); 1973 - Wb35Reg_Write(pHwData, 0x0864, PowerData); 1974 - 1975 - /* Update BB48 BB4C BB58 for high precision txvga */ 1976 - Wb35Reg_Write(pHwData, 0x1048, w89rf242_txvga_data[i][2]); 1977 - Wb35Reg_Write(pHwData, 0x104c, w89rf242_txvga_data[i][3]); 1978 - Wb35Reg_Write(pHwData, 0x1058, w89rf242_txvga_data[i][4]); 1979 - 1980 - return i; 1981 - } 1982 - 1983 - /* 1984 - * =========================================================================== 1985 - * Dxx_initial -- 1986 - * Mxx_initial -- 1987 - * 1988 - * Routine Description: 1989 - * Initial the hardware setting and module variable 1990 - * =========================================================================== 1991 - */ 1992 - void Dxx_initial(struct hw_data *pHwData) 1993 - { 1994 - struct wb35_reg *reg = &pHwData->reg; 1995 - 1996 - /* 1997 - * Old IC: Single mode only. 1998 - * New IC: operation decide by Software set bit[4]. 1:multiple 0: single 1999 - */ 2000 - reg->D00_DmaControl = 0xc0000004; /* Txon, Rxon, multiple Rx for new 4k DMA */ 2001 - /* Txon, Rxon, single Rx for old 8k ASIC */ 2002 - if (!HAL_USB_MODE_BURST(pHwData)) 2003 - reg->D00_DmaControl = 0xc0000000; /* Txon, Rxon, single Rx for new 4k DMA */ 2004 - 2005 - Wb35Reg_WriteSync(pHwData, 0x0400, reg->D00_DmaControl); 2006 - } 2007 - 2008 - void Mxx_initial(struct hw_data *pHwData) 2009 - { 2010 - struct wb35_reg *reg = &pHwData->reg; 2011 - u32 tmp; 2012 - u32 pltmp[11]; 2013 - u16 i; 2014 - 2015 - 2016 - /* 2017 - * ====================================================== 2018 - * Initial Mxx register 2019 - * ====================================================== 2020 - */ 2021 - 2022 - /* M00 bit set */ 2023 - reg->M00_MacControl = 0x80000000; /* Solve beacon sequence number stop by hardware */ 2024 - 2025 - /* M24 disable enter power save, BB RxOn and enable NAV attack */ 2026 - reg->M24_MacControl = 0x08040042; 2027 - pltmp[0] = reg->M24_MacControl; 2028 - 2029 - pltmp[1] = 0; /* Skip M28, because no initialize value is required. */ 2030 - 2031 - /* M2C CWmin and CWmax setting */ 2032 - pHwData->cwmin = DEFAULT_CWMIN; 2033 - pHwData->cwmax = DEFAULT_CWMAX; 2034 - reg->M2C_MacControl = DEFAULT_CWMIN << 10; 2035 - reg->M2C_MacControl |= DEFAULT_CWMAX; 2036 - pltmp[2] = reg->M2C_MacControl; 2037 - 2038 - /* M30 BSSID */ 2039 - pltmp[3] = *(u32 *)pHwData->bssid; 2040 - 2041 - /* M34 */ 2042 - pHwData->AID = DEFAULT_AID; 2043 - tmp = *(u16 *) (pHwData->bssid + 4); 2044 - tmp |= DEFAULT_AID << 16; 2045 - pltmp[4] = tmp; 2046 - 2047 - /* M38 */ 2048 - reg->M38_MacControl = (DEFAULT_RATE_RETRY_LIMIT << 8) | (DEFAULT_LONG_RETRY_LIMIT << 4) | DEFAULT_SHORT_RETRY_LIMIT; 2049 - pltmp[5] = reg->M38_MacControl; 2050 - 2051 - /* M3C */ 2052 - tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST; 2053 - reg->M3C_MacControl = tmp; 2054 - pltmp[6] = tmp; 2055 - 2056 - /* M40 */ 2057 - pHwData->slot_time_select = DEFAULT_SLOT_TIME; 2058 - tmp = (DEFAULT_ATIMWD << 16) | DEFAULT_SLOT_TIME; 2059 - reg->M40_MacControl = tmp; 2060 - pltmp[7] = tmp; 2061 - 2062 - /* M44 */ 2063 - tmp = DEFAULT_MAX_TX_MSDU_LIFE_TIME << 10; /* *1024 */ 2064 - reg->M44_MacControl = tmp; 2065 - pltmp[8] = tmp; 2066 - 2067 - /* M48 */ 2068 - pHwData->BeaconPeriod = DEFAULT_BEACON_INTERVAL; 2069 - pHwData->ProbeDelay = DEFAULT_PROBE_DELAY_TIME; 2070 - tmp = (DEFAULT_BEACON_INTERVAL << 16) | DEFAULT_PROBE_DELAY_TIME; 2071 - reg->M48_MacControl = tmp; 2072 - pltmp[9] = tmp; 2073 - 2074 - /* M4C */ 2075 - reg->M4C_MacStatus = (DEFAULT_PROTOCOL_VERSION << 30) | (DEFAULT_MAC_POWER_STATE << 28) | (DEFAULT_DTIM_ALERT_TIME << 24); 2076 - pltmp[10] = reg->M4C_MacStatus; 2077 - 2078 - for (i = 0; i < 11; i++) 2079 - Wb35Reg_WriteSync(pHwData, 0x0824 + i * 4, pltmp[i]); 2080 - 2081 - /* M60 */ 2082 - Wb35Reg_WriteSync(pHwData, 0x0860, 0x12481248); 2083 - reg->M60_MacControl = 0x12481248; 2084 - 2085 - /* M68 */ 2086 - Wb35Reg_WriteSync(pHwData, 0x0868, 0x00050900); 2087 - reg->M68_MacControl = 0x00050900; 2088 - 2089 - /* M98 */ 2090 - Wb35Reg_WriteSync(pHwData, 0x0898, 0xffff8888); 2091 - reg->M98_MacControl = 0xffff8888; 2092 - } 2093 - 2094 - 2095 - void Uxx_power_off_procedure(struct hw_data *pHwData) 2096 - { 2097 - /* SW, PMU reset and turn off clock */ 2098 - Wb35Reg_WriteSync(pHwData, 0x03b0, 3); 2099 - Wb35Reg_WriteSync(pHwData, 0x03f0, 0xf9); 2100 - } 2101 - 2102 - /*Decide the TxVga of every channel */ 2103 - void GetTxVgaFromEEPROM(struct hw_data *pHwData) 2104 - { 2105 - u32 i, j, ltmp; 2106 - u16 Value[MAX_TXVGA_EEPROM]; 2107 - u8 *pctmp; 2108 - u8 ctmp = 0; 2109 - 2110 - /* Get the entire TxVga setting in EEPROM */ 2111 - for (i = 0; i < MAX_TXVGA_EEPROM; i++) { 2112 - Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08100000 + 0x00010000 * i); 2113 - Wb35Reg_ReadSync(pHwData, 0x03b4, &ltmp); 2114 - Value[i] = (u16) (ltmp & 0xffff); /* Get 16 bit available */ 2115 - Value[i] = cpu_to_le16(Value[i]); /* [7:0]2412 [7:0]2417 .... */ 2116 - } 2117 - 2118 - /* Adjust the filed which fills with reserved value. */ 2119 - pctmp = (u8 *) Value; 2120 - for (i = 0; i < (MAX_TXVGA_EEPROM * 2); i++) { 2121 - if (pctmp[i] != 0xff) 2122 - ctmp = pctmp[i]; 2123 - else 2124 - pctmp[i] = ctmp; 2125 - } 2126 - 2127 - /* Adjust WB_242 to WB_242_1 TxVga scale */ 2128 - if (pHwData->phy_type == RF_WB_242) { 2129 - for (i = 0; i < 4; i++) { /* Only 2412 2437 2462 2484 case must be modified */ 2130 - for (j = 0; j < ARRAY_SIZE(w89rf242_txvga_old_mapping); j++) { 2131 - if (pctmp[i] < (u8) w89rf242_txvga_old_mapping[j][1]) { 2132 - pctmp[i] = (u8) w89rf242_txvga_old_mapping[j][0]; 2133 - break; 2134 - } 2135 - } 2136 - 2137 - if (j == ARRAY_SIZE(w89rf242_txvga_old_mapping)) 2138 - pctmp[i] = (u8)w89rf242_txvga_old_mapping[j-1][0]; 2139 - } 2140 - } 2141 - 2142 - memcpy(pHwData->TxVgaSettingInEEPROM, pctmp, MAX_TXVGA_EEPROM * 2); /* MAX_TXVGA_EEPROM is u16 count */ 2143 - EEPROMTxVgaAdjust(pHwData); 2144 - } 2145 - 2146 - /* 2147 - * This function will affect the TxVga parameter in HAL. If hal_set_current_channel 2148 - * or RFSynthesizer_SetPowerIndex be called, new TxVga will take effect. 2149 - * TxVgaSettingInEEPROM of sHwData is an u8 array point to EEPROM contain for IS89C35 2150 - * This function will use default TxVgaSettingInEEPROM data to calculate new TxVga. 2151 - */ 2152 - void EEPROMTxVgaAdjust(struct hw_data *pHwData) 2153 - { 2154 - u8 *pTxVga = pHwData->TxVgaSettingInEEPROM; 2155 - s16 i, stmp; 2156 - 2157 - /* -- 2.4G -- */ 2158 - /* channel 1 ~ 5 */ 2159 - stmp = pTxVga[1] - pTxVga[0]; 2160 - for (i = 0; i < 5; i++) 2161 - pHwData->TxVgaFor24[i] = pTxVga[0] + stmp * i / 4; 2162 - /* channel 6 ~ 10 */ 2163 - stmp = pTxVga[2] - pTxVga[1]; 2164 - for (i = 5; i < 10; i++) 2165 - pHwData->TxVgaFor24[i] = pTxVga[1] + stmp * (i - 5) / 4; 2166 - /* channel 11 ~ 13 */ 2167 - stmp = pTxVga[3] - pTxVga[2]; 2168 - for (i = 10; i < 13; i++) 2169 - pHwData->TxVgaFor24[i] = pTxVga[2] + stmp * (i - 10) / 2; 2170 - /* channel 14 */ 2171 - pHwData->TxVgaFor24[13] = pTxVga[3]; 2172 - 2173 - /* -- 5G -- */ 2174 - if (pHwData->phy_type == RF_AIROHA_7230) { 2175 - /* channel 184 */ 2176 - pHwData->TxVgaFor50[0].ChanNo = 184; 2177 - pHwData->TxVgaFor50[0].TxVgaValue = pTxVga[4]; 2178 - /* channel 196 */ 2179 - pHwData->TxVgaFor50[3].ChanNo = 196; 2180 - pHwData->TxVgaFor50[3].TxVgaValue = pTxVga[5]; 2181 - /* interpolate */ 2182 - pHwData->TxVgaFor50[1].ChanNo = 188; 2183 - pHwData->TxVgaFor50[2].ChanNo = 192; 2184 - stmp = pTxVga[5] - pTxVga[4]; 2185 - pHwData->TxVgaFor50[2].TxVgaValue = pTxVga[5] - stmp / 3; 2186 - pHwData->TxVgaFor50[1].TxVgaValue = pTxVga[5] - stmp * 2 / 3; 2187 - 2188 - /* channel 16 */ 2189 - pHwData->TxVgaFor50[6].ChanNo = 16; 2190 - pHwData->TxVgaFor50[6].TxVgaValue = pTxVga[6]; 2191 - pHwData->TxVgaFor50[4].ChanNo = 8; 2192 - pHwData->TxVgaFor50[4].TxVgaValue = pTxVga[6]; 2193 - pHwData->TxVgaFor50[5].ChanNo = 12; 2194 - pHwData->TxVgaFor50[5].TxVgaValue = pTxVga[6]; 2195 - 2196 - /* channel 36 */ 2197 - pHwData->TxVgaFor50[8].ChanNo = 36; 2198 - pHwData->TxVgaFor50[8].TxVgaValue = pTxVga[7]; 2199 - pHwData->TxVgaFor50[7].ChanNo = 34; 2200 - pHwData->TxVgaFor50[7].TxVgaValue = pTxVga[7]; 2201 - pHwData->TxVgaFor50[9].ChanNo = 38; 2202 - pHwData->TxVgaFor50[9].TxVgaValue = pTxVga[7]; 2203 - 2204 - /* channel 40 */ 2205 - pHwData->TxVgaFor50[10].ChanNo = 40; 2206 - pHwData->TxVgaFor50[10].TxVgaValue = pTxVga[8]; 2207 - /* channel 48 */ 2208 - pHwData->TxVgaFor50[14].ChanNo = 48; 2209 - pHwData->TxVgaFor50[14].TxVgaValue = pTxVga[9]; 2210 - /* interpolate */ 2211 - pHwData->TxVgaFor50[11].ChanNo = 42; 2212 - pHwData->TxVgaFor50[12].ChanNo = 44; 2213 - pHwData->TxVgaFor50[13].ChanNo = 46; 2214 - stmp = pTxVga[9] - pTxVga[8]; 2215 - pHwData->TxVgaFor50[13].TxVgaValue = pTxVga[9] - stmp / 4; 2216 - pHwData->TxVgaFor50[12].TxVgaValue = pTxVga[9] - stmp * 2 / 4; 2217 - pHwData->TxVgaFor50[11].TxVgaValue = pTxVga[9] - stmp * 3 / 4; 2218 - 2219 - /* channel 52 */ 2220 - pHwData->TxVgaFor50[15].ChanNo = 52; 2221 - pHwData->TxVgaFor50[15].TxVgaValue = pTxVga[10]; 2222 - /* channel 64 */ 2223 - pHwData->TxVgaFor50[18].ChanNo = 64; 2224 - pHwData->TxVgaFor50[18].TxVgaValue = pTxVga[11]; 2225 - /* interpolate */ 2226 - pHwData->TxVgaFor50[16].ChanNo = 56; 2227 - pHwData->TxVgaFor50[17].ChanNo = 60; 2228 - stmp = pTxVga[11] - pTxVga[10]; 2229 - pHwData->TxVgaFor50[17].TxVgaValue = pTxVga[11] - stmp / 3; 2230 - pHwData->TxVgaFor50[16].TxVgaValue = pTxVga[11] - stmp * 2 / 3; 2231 - 2232 - /* channel 100 */ 2233 - pHwData->TxVgaFor50[19].ChanNo = 100; 2234 - pHwData->TxVgaFor50[19].TxVgaValue = pTxVga[12]; 2235 - /* channel 112 */ 2236 - pHwData->TxVgaFor50[22].ChanNo = 112; 2237 - pHwData->TxVgaFor50[22].TxVgaValue = pTxVga[13]; 2238 - /* interpolate */ 2239 - pHwData->TxVgaFor50[20].ChanNo = 104; 2240 - pHwData->TxVgaFor50[21].ChanNo = 108; 2241 - stmp = pTxVga[13] - pTxVga[12]; 2242 - pHwData->TxVgaFor50[21].TxVgaValue = pTxVga[13] - stmp / 3; 2243 - pHwData->TxVgaFor50[20].TxVgaValue = pTxVga[13] - stmp * 2 / 3; 2244 - 2245 - /* channel 128 */ 2246 - pHwData->TxVgaFor50[26].ChanNo = 128; 2247 - pHwData->TxVgaFor50[26].TxVgaValue = pTxVga[14]; 2248 - /* interpolate */ 2249 - pHwData->TxVgaFor50[23].ChanNo = 116; 2250 - pHwData->TxVgaFor50[24].ChanNo = 120; 2251 - pHwData->TxVgaFor50[25].ChanNo = 124; 2252 - stmp = pTxVga[14] - pTxVga[13]; 2253 - pHwData->TxVgaFor50[25].TxVgaValue = pTxVga[14] - stmp / 4; 2254 - pHwData->TxVgaFor50[24].TxVgaValue = pTxVga[14] - stmp * 2 / 4; 2255 - pHwData->TxVgaFor50[23].TxVgaValue = pTxVga[14] - stmp * 3 / 4; 2256 - 2257 - /* channel 140 */ 2258 - pHwData->TxVgaFor50[29].ChanNo = 140; 2259 - pHwData->TxVgaFor50[29].TxVgaValue = pTxVga[15]; 2260 - /* interpolate */ 2261 - pHwData->TxVgaFor50[27].ChanNo = 132; 2262 - pHwData->TxVgaFor50[28].ChanNo = 136; 2263 - stmp = pTxVga[15] - pTxVga[14]; 2264 - pHwData->TxVgaFor50[28].TxVgaValue = pTxVga[15] - stmp / 3; 2265 - pHwData->TxVgaFor50[27].TxVgaValue = pTxVga[15] - stmp * 2 / 3; 2266 - 2267 - /* channel 149 */ 2268 - pHwData->TxVgaFor50[30].ChanNo = 149; 2269 - pHwData->TxVgaFor50[30].TxVgaValue = pTxVga[16]; 2270 - /* channel 165 */ 2271 - pHwData->TxVgaFor50[34].ChanNo = 165; 2272 - pHwData->TxVgaFor50[34].TxVgaValue = pTxVga[17]; 2273 - /* interpolate */ 2274 - pHwData->TxVgaFor50[31].ChanNo = 153; 2275 - pHwData->TxVgaFor50[32].ChanNo = 157; 2276 - pHwData->TxVgaFor50[33].ChanNo = 161; 2277 - stmp = pTxVga[17] - pTxVga[16]; 2278 - pHwData->TxVgaFor50[33].TxVgaValue = pTxVga[17] - stmp / 4; 2279 - pHwData->TxVgaFor50[32].TxVgaValue = pTxVga[17] - stmp * 2 / 4; 2280 - pHwData->TxVgaFor50[31].TxVgaValue = pTxVga[17] - stmp * 3 / 4; 2281 - } 2282 - } 2283 - 2284 - void BBProcessor_RateChanging(struct hw_data *pHwData, u8 rate) 2285 - { 2286 - struct wb35_reg *reg = &pHwData->reg; 2287 - unsigned char Is11bRate; 2288 - 2289 - Is11bRate = (rate % 6) ? 1 : 0; 2290 - switch (pHwData->phy_type) { 2291 - case RF_AIROHA_2230: 2292 - case RF_AIROHA_2230S: 2293 - if (Is11bRate) { 2294 - if ((reg->BB48 != BB48_DEFAULT_AL2230_11B) && 2295 - (reg->BB4C != BB4C_DEFAULT_AL2230_11B)) { 2296 - Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_AL2230_11B); 2297 - Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_AL2230_11B); 2298 - } 2299 - } else { 2300 - if ((reg->BB48 != BB48_DEFAULT_AL2230_11G) && 2301 - (reg->BB4C != BB4C_DEFAULT_AL2230_11G)) { 2302 - Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_AL2230_11G); 2303 - Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_AL2230_11G); 2304 - } 2305 - } 2306 - break; 2307 - case RF_WB_242: 2308 - if (Is11bRate) { 2309 - if ((reg->BB48 != BB48_DEFAULT_WB242_11B) && 2310 - (reg->BB4C != BB4C_DEFAULT_WB242_11B)) { 2311 - reg->BB48 = BB48_DEFAULT_WB242_11B; 2312 - reg->BB4C = BB4C_DEFAULT_WB242_11B; 2313 - Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_WB242_11B); 2314 - Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_WB242_11B); 2315 - } 2316 - } else { 2317 - if ((reg->BB48 != BB48_DEFAULT_WB242_11G) && 2318 - (reg->BB4C != BB4C_DEFAULT_WB242_11G)) { 2319 - reg->BB48 = BB48_DEFAULT_WB242_11G; 2320 - reg->BB4C = BB4C_DEFAULT_WB242_11G; 2321 - Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_WB242_11G); 2322 - Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_WB242_11G); 2323 - } 2324 - } 2325 - break; 2326 - } 2327 - } 2328 -
-191
drivers/staging/winbond/sme_api.h
··· 1 - /* 2 - * sme_api.h 3 - * 4 - * Copyright(C) 2002 Winbond Electronics Corp. 5 - */ 6 - 7 - #ifndef __SME_API_H__ 8 - #define __SME_API_H__ 9 - 10 - #include <linux/types.h> 11 - 12 - #include "localpara.h" 13 - 14 - /****************** CONSTANT AND MACRO SECTION ******************************/ 15 - 16 - #define MEDIA_STATE_DISCONNECTED 0 17 - #define MEDIA_STATE_CONNECTED 1 18 - 19 - /* ARRAY CHECK */ 20 - #define MAX_POWER_TO_DB 32 21 - 22 - /****************** TYPE DEFINITION SECTION *********************************/ 23 - 24 - /****************** EXPORTED FUNCTION DECLARATION SECTION *******************/ 25 - 26 - /* OID_802_11_BSSID */ 27 - s8 sme_get_bssid(void *pcore_data, u8 *pbssid); 28 - s8 sme_get_desired_bssid(void *pcore_data, u8 *pbssid); /* Unused */ 29 - s8 sme_set_desired_bssid(void *pcore_data, u8 *pbssid); 30 - 31 - /* OID_802_11_SSID */ 32 - s8 sme_get_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len); 33 - s8 sme_get_desired_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len);/* Unused */ 34 - s8 sme_set_desired_ssid(void *pcore_data, u8 *pssid, u8 ssid_len); 35 - 36 - /* OID_802_11_INFRASTRUCTURE_MODE */ 37 - s8 sme_get_bss_type(void *pcore_data, u8 *pbss_type); 38 - s8 sme_get_desired_bss_type(void *pcore_data, u8 *pbss_type); /* Unused */ 39 - s8 sme_set_desired_bss_type(void *pcore_data, u8 bss_type); 40 - 41 - /* OID_802_11_FRAGMENTATION_THRESHOLD */ 42 - s8 sme_get_fragment_threshold(void *pcore_data, u32 *pthreshold); 43 - s8 sme_set_fragment_threshold(void *pcore_data, u32 threshold); 44 - 45 - /* OID_802_11_RTS_THRESHOLD */ 46 - s8 sme_get_rts_threshold(void *pcore_data, u32 *pthreshold); 47 - s8 sme_set_rts_threshold(void *pcore_data, u32 threshold); 48 - 49 - /* OID_802_11_CONFIGURATION */ 50 - s8 sme_get_beacon_period(void *pcore_data, u16 *pbeacon_period); 51 - s8 sme_set_beacon_period(void *pcore_data, u16 beacon_period); 52 - 53 - s8 sme_get_atim_window(void *pcore_data, u16 *patim_window); 54 - s8 sme_set_atim_window(void *pcore_data, u16 atim_window); 55 - 56 - s8 sme_get_current_channel(void *pcore_data, u8 *pcurrent_channel); 57 - s8 sme_get_current_band(void *pcore_data, u8 *pcurrent_band); 58 - s8 sme_set_current_channel(void *pcore_data, u8 current_channel); 59 - 60 - /* OID_802_11_BSSID_LIST */ 61 - s8 sme_get_scan_bss_count(void *pcore_data, u8 *pcount); 62 - s8 sme_get_scan_bss(void *pcore_data, u8 index, void **ppbss); 63 - 64 - s8 sme_get_connected_bss(void *pcore_data, void **ppbss_now); 65 - 66 - /* OID_802_11_AUTHENTICATION_MODE */ 67 - s8 sme_get_auth_mode(void *pcore_data, u8 *pauth_mode); 68 - s8 sme_set_auth_mode(void *pcore_data, u8 auth_mode); 69 - 70 - /* OID_802_11_WEP_STATUS / OID_802_11_ENCRYPTION_STATUS */ 71 - s8 sme_get_wep_mode(void *pcore_data, u8 *pwep_mode); 72 - s8 sme_set_wep_mode(void *pcore_data, u8 wep_mode); 73 - 74 - /* OID_GEN_VENDOR_ID */ 75 - /* OID_802_3_PERMANENT_ADDRESS */ 76 - s8 sme_get_permanent_mac_addr(void *pcore_data, u8 *pmac_addr); 77 - 78 - /* OID_802_3_CURRENT_ADDRESS */ 79 - s8 sme_get_current_mac_addr(void *pcore_data, u8 *pmac_addr); 80 - 81 - /* OID_802_11_NETWORK_TYPE_IN_USE */ 82 - s8 sme_get_network_type_in_use(void *pcore_data, u8 *ptype); 83 - s8 sme_set_network_type_in_use(void *pcore_data, u8 type); 84 - 85 - /* OID_802_11_SUPPORTED_RATES */ 86 - s8 sme_get_supported_rate(void *pcore_data, u8 *prates); 87 - 88 - /* OID_802_11_ADD_WEP */ 89 - s8 sme_set_add_wep(void *pcore_data, u32 key_index, u32 key_len, 90 - u8 *Address, u8 *key); 91 - 92 - /* OID_802_11_REMOVE_WEP */ 93 - s8 sme_set_remove_wep(void *pcre_data, u32 key_index); 94 - 95 - /* OID_802_11_DISASSOCIATE */ 96 - s8 sme_set_disassociate(void *pcore_data); 97 - 98 - /* OID_802_11_POWER_MODE */ 99 - s8 sme_get_power_mode(void *pcore_data, u8 *pmode); 100 - s8 sme_set_power_mode(void *pcore_data, u8 mode); 101 - 102 - /* OID_802_11_BSSID_LIST_SCAN */ 103 - s8 sme_set_bssid_list_scan(void *pcore_data, void *pscan_para); 104 - 105 - /* OID_802_11_RELOAD_DEFAULTS */ 106 - s8 sme_set_reload_defaults(void *pcore_data, u8 reload_type); 107 - 108 - 109 - /*------------------------- non-standard ----------------------------------*/ 110 - s8 sme_get_connect_status(void *pcore_data, u8 *pstatus); 111 - /*--------------------------------------------------------------------------*/ 112 - 113 - void sme_get_encryption_status(void *pcore_data, u8 *EncryptStatus); 114 - void sme_set_encryption_status(void *pcore_data, u8 EncryptStatus); 115 - s8 sme_add_key(void *pcore_data, 116 - u32 key_index, 117 - u8 key_len, 118 - u8 key_type, 119 - u8 *key_bssid, 120 - u8 *ptx_tsc, 121 - u8 *prx_tsc, 122 - u8 *key_material); 123 - void sme_remove_default_key(void *pcore_data, int index); 124 - void sme_remove_mapping_key(void *pcore_data, u8 *pmac_addr); 125 - void sme_clear_all_mapping_key(void *pcore_data); 126 - void sme_clear_all_default_key(void *pcore_data); 127 - 128 - 129 - 130 - s8 sme_set_preamble_mode(void *pcore_data, u8 mode); 131 - s8 sme_get_preamble_mode(void *pcore_data, u8 *mode); 132 - s8 sme_get_preamble_type(void *pcore_data, u8 *type); 133 - s8 sme_set_slottime_mode(void *pcore_data, u8 mode); 134 - s8 sme_get_slottime_mode(void *pcore_data, u8 *mode); 135 - s8 sme_get_slottime_type(void *pcore_data, u8 *type); 136 - s8 sme_set_txrate_policy(void *pcore_data, u8 policy); 137 - s8 sme_get_txrate_policy(void *pcore_data, u8 *policy); 138 - s8 sme_get_cwmin_value(void *pcore_data, u8 *cwmin); 139 - s8 sme_get_cwmax_value(void *pcore_data, u16 *cwmax); 140 - s8 sme_get_ms_radio_mode(void *pcore_data, u8 *pMsRadioOff); 141 - s8 sme_set_ms_radio_mode(void *pcore_data, u8 boMsRadioOff); 142 - 143 - void sme_get_tx_power_level(void *pcore_data, u32 *TxPower); 144 - u8 sme_set_tx_power_level(void *pcore_data, u32 TxPower); 145 - void sme_get_antenna_count(void *pcore_data, u32 *AntennaCount); 146 - void sme_get_rx_antenna(void *pcore_data, u32 *RxAntenna); 147 - u8 sme_set_rx_antenna(void *pcore_data, u32 RxAntenna); 148 - void sme_get_tx_antenna(void *pcore_data, u32 *TxAntenna); 149 - s8 sme_set_tx_antenna(void *pcore_data, u32 TxAntenna); 150 - s8 sme_set_IBSS_chan(void *pcore_data, struct chan_info chan); 151 - s8 sme_set_IE_append(void *pcore_data, u8 *buffer, u16 buf_len); 152 - 153 - /* ================== Local functions ====================== */ 154 - static const u32 PowerDbToMw[] = { 155 - 56, /* mW, MAX - 0, 17.5 dbm */ 156 - 40, /* mW, MAX - 1, 16.0 dbm */ 157 - 30, /* mW, MAX - 2, 14.8 dbm */ 158 - 20, /* mW, MAX - 3, 13.0 dbm */ 159 - 15, /* mW, MAX - 4, 11.8 dbm */ 160 - 12, /* mW, MAX - 5, 10.6 dbm */ 161 - 9, /* mW, MAX - 6, 9.4 dbm */ 162 - 7, /* mW, MAX - 7, 8.3 dbm */ 163 - 5, /* mW, MAX - 8, 6.4 dbm */ 164 - 4, /* mW, MAX - 9, 5.3 dbm */ 165 - 3, /* mW, MAX - 10, 4.0 dbm */ 166 - 2, /* mW, MAX - 11, ? dbm */ 167 - 2, /* mW, MAX - 12, ? dbm */ 168 - 2, /* mW, MAX - 13, ? dbm */ 169 - 2, /* mW, MAX - 14, ? dbm */ 170 - 2, /* mW, MAX - 15, ? dbm */ 171 - 2, /* mW, MAX - 16, ? dbm */ 172 - 2, /* mW, MAX - 17, ? dbm */ 173 - 2, /* mW, MAX - 18, ? dbm */ 174 - 1, /* mW, MAX - 19, ? dbm */ 175 - 1, /* mW, MAX - 20, ? dbm */ 176 - 1, /* mW, MAX - 21, ? dbm */ 177 - 1, /* mW, MAX - 22, ? dbm */ 178 - 1, /* mW, MAX - 23, ? dbm */ 179 - 1, /* mW, MAX - 24, ? dbm */ 180 - 1, /* mW, MAX - 25, ? dbm */ 181 - 1, /* mW, MAX - 26, ? dbm */ 182 - 1, /* mW, MAX - 27, ? dbm */ 183 - 1, /* mW, MAX - 28, ? dbm */ 184 - 1, /* mW, MAX - 29, ? dbm */ 185 - 1, /* mW, MAX - 30, ? dbm */ 186 - 1 /* mW, MAX - 31, ? dbm */ 187 - }; 188 - 189 - #endif /* __SME_API_H__ */ 190 - 191 -
-806
drivers/staging/winbond/wb35reg.c
··· 1 - #include "wb35reg_f.h" 2 - #include "phy_calibration.h" 3 - 4 - #include <linux/usb.h> 5 - #include <linux/slab.h> 6 - 7 - /* 8 - * true : read command process successfully 9 - * false : register not support 10 - * RegisterNo : start base 11 - * pRegisterData : data point 12 - * NumberOfData : number of register data 13 - * Flag : AUTO_INCREMENT - RegisterNo will auto increment 4 14 - * NO_INCREMENT - Function will write data into the same register 15 - */ 16 - unsigned char Wb35Reg_BurstWrite(struct hw_data *pHwData, u16 RegisterNo, 17 - u32 *pRegisterData, u8 NumberOfData, u8 Flag) 18 - { 19 - struct wb35_reg *reg = &pHwData->reg; 20 - struct urb *urb = NULL; 21 - struct wb35_reg_queue *reg_queue = NULL; 22 - u16 UrbSize; 23 - struct usb_ctrlrequest *dr; 24 - u16 i, DataSize = NumberOfData * 4; 25 - 26 - /* Module shutdown */ 27 - if (pHwData->SurpriseRemove) 28 - return false; 29 - 30 - /* Trying to use burst write function if use new hardware */ 31 - UrbSize = sizeof(struct wb35_reg_queue) + DataSize + sizeof(struct usb_ctrlrequest); 32 - reg_queue = kzalloc(UrbSize, GFP_ATOMIC); 33 - if (reg_queue == NULL) 34 - return false; 35 - 36 - urb = usb_alloc_urb(0, GFP_ATOMIC); 37 - if (urb == NULL) { 38 - kfree(reg_queue); 39 - return false; 40 - } 41 - 42 - reg_queue->DIRECT = 2; /* burst write register */ 43 - reg_queue->INDEX = RegisterNo; 44 - reg_queue->pBuffer = (u32 *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); 45 - memcpy(reg_queue->pBuffer, pRegisterData, DataSize); 46 - /* the function for reversing register data from little endian to big endian */ 47 - for (i = 0; i < NumberOfData; i++) 48 - reg_queue->pBuffer[i] = cpu_to_le32(reg_queue->pBuffer[i]); 49 - 50 - dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue) + DataSize); 51 - dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE; 52 - dr->bRequest = 0x04; /* USB or vendor-defined request code, burst mode */ 53 - dr->wValue = cpu_to_le16(Flag); /* 0: Register number auto-increment, 1: No auto increment */ 54 - dr->wIndex = cpu_to_le16(RegisterNo); 55 - dr->wLength = cpu_to_le16(DataSize); 56 - reg_queue->Next = NULL; 57 - reg_queue->pUsbReq = dr; 58 - reg_queue->urb = urb; 59 - 60 - spin_lock_irq(&reg->EP0VM_spin_lock); 61 - if (reg->reg_first == NULL) 62 - reg->reg_first = reg_queue; 63 - else 64 - reg->reg_last->Next = reg_queue; 65 - reg->reg_last = reg_queue; 66 - 67 - spin_unlock_irq(&reg->EP0VM_spin_lock); 68 - 69 - /* Start EP0VM */ 70 - Wb35Reg_EP0VM_start(pHwData); 71 - 72 - return true; 73 - } 74 - 75 - void Wb35Reg_Update(struct hw_data *pHwData, u16 RegisterNo, u32 RegisterValue) 76 - { 77 - struct wb35_reg *reg = &pHwData->reg; 78 - switch (RegisterNo) { 79 - case 0x3b0: 80 - reg->U1B0 = RegisterValue; 81 - break; 82 - case 0x3bc: 83 - reg->U1BC_LEDConfigure = RegisterValue; 84 - break; 85 - case 0x400: 86 - reg->D00_DmaControl = RegisterValue; 87 - break; 88 - case 0x800: 89 - reg->M00_MacControl = RegisterValue; 90 - break; 91 - case 0x804: 92 - reg->M04_MulticastAddress1 = RegisterValue; 93 - break; 94 - case 0x808: 95 - reg->M08_MulticastAddress2 = RegisterValue; 96 - break; 97 - case 0x824: 98 - reg->M24_MacControl = RegisterValue; 99 - break; 100 - case 0x828: 101 - reg->M28_MacControl = RegisterValue; 102 - break; 103 - case 0x82c: 104 - reg->M2C_MacControl = RegisterValue; 105 - break; 106 - case 0x838: 107 - reg->M38_MacControl = RegisterValue; 108 - break; 109 - case 0x840: 110 - reg->M40_MacControl = RegisterValue; 111 - break; 112 - case 0x844: 113 - reg->M44_MacControl = RegisterValue; 114 - break; 115 - case 0x848: 116 - reg->M48_MacControl = RegisterValue; 117 - break; 118 - case 0x84c: 119 - reg->M4C_MacStatus = RegisterValue; 120 - break; 121 - case 0x860: 122 - reg->M60_MacControl = RegisterValue; 123 - break; 124 - case 0x868: 125 - reg->M68_MacControl = RegisterValue; 126 - break; 127 - case 0x870: 128 - reg->M70_MacControl = RegisterValue; 129 - break; 130 - case 0x874: 131 - reg->M74_MacControl = RegisterValue; 132 - break; 133 - case 0x878: 134 - reg->M78_ERPInformation = RegisterValue; 135 - break; 136 - case 0x87C: 137 - reg->M7C_MacControl = RegisterValue; 138 - break; 139 - case 0x880: 140 - reg->M80_MacControl = RegisterValue; 141 - break; 142 - case 0x884: 143 - reg->M84_MacControl = RegisterValue; 144 - break; 145 - case 0x888: 146 - reg->M88_MacControl = RegisterValue; 147 - break; 148 - case 0x898: 149 - reg->M98_MacControl = RegisterValue; 150 - break; 151 - case 0x100c: 152 - reg->BB0C = RegisterValue; 153 - break; 154 - case 0x102c: 155 - reg->BB2C = RegisterValue; 156 - break; 157 - case 0x1030: 158 - reg->BB30 = RegisterValue; 159 - break; 160 - case 0x103c: 161 - reg->BB3C = RegisterValue; 162 - break; 163 - case 0x1048: 164 - reg->BB48 = RegisterValue; 165 - break; 166 - case 0x104c: 167 - reg->BB4C = RegisterValue; 168 - break; 169 - case 0x1050: 170 - reg->BB50 = RegisterValue; 171 - break; 172 - case 0x1054: 173 - reg->BB54 = RegisterValue; 174 - break; 175 - case 0x1058: 176 - reg->BB58 = RegisterValue; 177 - break; 178 - case 0x105c: 179 - reg->BB5C = RegisterValue; 180 - break; 181 - case 0x1060: 182 - reg->BB60 = RegisterValue; 183 - break; 184 - } 185 - } 186 - 187 - /* 188 - * true : read command process successfully 189 - * false : register not support 190 - */ 191 - unsigned char Wb35Reg_WriteSync(struct hw_data *pHwData, u16 RegisterNo, 192 - u32 RegisterValue) 193 - { 194 - struct wb35_reg *reg = &pHwData->reg; 195 - int ret = -1; 196 - 197 - /* Module shutdown */ 198 - if (pHwData->SurpriseRemove) 199 - return false; 200 - 201 - RegisterValue = cpu_to_le32(RegisterValue); 202 - 203 - /* update the register by send usb message */ 204 - reg->SyncIoPause = 1; 205 - 206 - /* Wait until EP0VM stop */ 207 - while (reg->EP0vm_state != VM_STOP) 208 - msleep(10); 209 - 210 - /* Sync IoCallDriver */ 211 - reg->EP0vm_state = VM_RUNNING; 212 - ret = usb_control_msg(pHwData->udev, 213 - usb_sndctrlpipe(pHwData->udev, 0), 214 - 0x03, 215 - USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT, 216 - 0x0, RegisterNo, &RegisterValue, 4, HZ * 100); 217 - reg->EP0vm_state = VM_STOP; 218 - reg->SyncIoPause = 0; 219 - 220 - Wb35Reg_EP0VM_start(pHwData); 221 - 222 - if (ret < 0) { 223 - pr_debug("EP0 Write register usb message sending error\n"); 224 - pHwData->SurpriseRemove = 1; 225 - return false; 226 - } 227 - return true; 228 - } 229 - 230 - /* 231 - * true : read command process successfully 232 - * false : register not support 233 - */ 234 - unsigned char Wb35Reg_Write(struct hw_data *pHwData, u16 RegisterNo, 235 - u32 RegisterValue) 236 - { 237 - struct wb35_reg *reg = &pHwData->reg; 238 - struct usb_ctrlrequest *dr; 239 - struct urb *urb = NULL; 240 - struct wb35_reg_queue *reg_queue = NULL; 241 - u16 UrbSize; 242 - 243 - /* Module shutdown */ 244 - if (pHwData->SurpriseRemove) 245 - return false; 246 - 247 - /* update the register by send urb request */ 248 - UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest); 249 - reg_queue = kzalloc(UrbSize, GFP_ATOMIC); 250 - if (reg_queue == NULL) 251 - return false; 252 - 253 - urb = usb_alloc_urb(0, GFP_ATOMIC); 254 - if (urb == NULL) { 255 - kfree(reg_queue); 256 - return false; 257 - } 258 - 259 - reg_queue->DIRECT = 1; /* burst write register */ 260 - reg_queue->INDEX = RegisterNo; 261 - reg_queue->VALUE = cpu_to_le32(RegisterValue); 262 - reg_queue->RESERVED_VALID = false; 263 - dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); 264 - dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE; 265 - dr->bRequest = 0x03; /* USB or vendor-defined request code, burst mode */ 266 - dr->wValue = cpu_to_le16(0x0); 267 - dr->wIndex = cpu_to_le16(RegisterNo); 268 - dr->wLength = cpu_to_le16(4); 269 - 270 - /* Enter the sending queue */ 271 - reg_queue->Next = NULL; 272 - reg_queue->pUsbReq = dr; 273 - reg_queue->urb = urb; 274 - 275 - spin_lock_irq(&reg->EP0VM_spin_lock); 276 - if (reg->reg_first == NULL) 277 - reg->reg_first = reg_queue; 278 - else 279 - reg->reg_last->Next = reg_queue; 280 - reg->reg_last = reg_queue; 281 - 282 - spin_unlock_irq(&reg->EP0VM_spin_lock); 283 - 284 - /* Start EP0VM */ 285 - Wb35Reg_EP0VM_start(pHwData); 286 - 287 - return true; 288 - } 289 - 290 - /* 291 - * This command will be executed with a user defined value. When it completes, 292 - * this value is useful. For example, hal_set_current_channel will use it. 293 - * true : read command process successfully 294 - * false : register not supported 295 - */ 296 - unsigned char Wb35Reg_WriteWithCallbackValue(struct hw_data *pHwData, 297 - u16 RegisterNo, 298 - u32 RegisterValue, 299 - s8 *pValue, 300 - s8 Len) 301 - { 302 - struct wb35_reg *reg = &pHwData->reg; 303 - struct usb_ctrlrequest *dr; 304 - struct urb *urb = NULL; 305 - struct wb35_reg_queue *reg_queue = NULL; 306 - u16 UrbSize; 307 - 308 - /* Module shutdown */ 309 - if (pHwData->SurpriseRemove) 310 - return false; 311 - 312 - /* update the register by send urb request */ 313 - UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest); 314 - reg_queue = kzalloc(UrbSize, GFP_ATOMIC); 315 - if (reg_queue == NULL) 316 - return false; 317 - 318 - urb = usb_alloc_urb(0, GFP_ATOMIC); 319 - if (urb == NULL) { 320 - kfree(reg_queue); 321 - return false; 322 - } 323 - 324 - reg_queue->DIRECT = 1; /* burst write register */ 325 - reg_queue->INDEX = RegisterNo; 326 - reg_queue->VALUE = cpu_to_le32(RegisterValue); 327 - /* NOTE : Users must guarantee the size of value will not exceed the buffer size. */ 328 - memcpy(reg_queue->RESERVED, pValue, Len); 329 - reg_queue->RESERVED_VALID = true; 330 - dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); 331 - dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE; 332 - dr->bRequest = 0x03; /* USB or vendor-defined request code, burst mode */ 333 - dr->wValue = cpu_to_le16(0x0); 334 - dr->wIndex = cpu_to_le16(RegisterNo); 335 - dr->wLength = cpu_to_le16(4); 336 - 337 - /* Enter the sending queue */ 338 - reg_queue->Next = NULL; 339 - reg_queue->pUsbReq = dr; 340 - reg_queue->urb = urb; 341 - spin_lock_irq(&reg->EP0VM_spin_lock); 342 - if (reg->reg_first == NULL) 343 - reg->reg_first = reg_queue; 344 - else 345 - reg->reg_last->Next = reg_queue; 346 - reg->reg_last = reg_queue; 347 - 348 - spin_unlock_irq(&reg->EP0VM_spin_lock); 349 - 350 - /* Start EP0VM */ 351 - Wb35Reg_EP0VM_start(pHwData); 352 - 353 - return true; 354 - } 355 - 356 - /* 357 - * true : read command process successfully 358 - * false : register not support 359 - * pRegisterValue : It must be a resident buffer due to 360 - * asynchronous read register. 361 - */ 362 - unsigned char Wb35Reg_ReadSync(struct hw_data *pHwData, u16 RegisterNo, 363 - u32 *pRegisterValue) 364 - { 365 - struct wb35_reg *reg = &pHwData->reg; 366 - u32 *pltmp = pRegisterValue; 367 - int ret = -1; 368 - 369 - /* Module shutdown */ 370 - if (pHwData->SurpriseRemove) 371 - return false; 372 - 373 - /* Read the register by send usb message */ 374 - reg->SyncIoPause = 1; 375 - 376 - /* Wait until EP0VM stop */ 377 - while (reg->EP0vm_state != VM_STOP) 378 - msleep(10); 379 - 380 - reg->EP0vm_state = VM_RUNNING; 381 - ret = usb_control_msg(pHwData->udev, 382 - usb_rcvctrlpipe(pHwData->udev, 0), 383 - 0x01, 384 - USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN, 385 - 0x0, RegisterNo, pltmp, 4, HZ * 100); 386 - 387 - *pRegisterValue = cpu_to_le32(*pltmp); 388 - 389 - reg->EP0vm_state = VM_STOP; 390 - 391 - Wb35Reg_Update(pHwData, RegisterNo, *pRegisterValue); 392 - reg->SyncIoPause = 0; 393 - 394 - Wb35Reg_EP0VM_start(pHwData); 395 - 396 - if (ret < 0) { 397 - pr_debug("EP0 Read register usb message sending error\n"); 398 - pHwData->SurpriseRemove = 1; 399 - return false; 400 - } 401 - return true; 402 - } 403 - 404 - /* 405 - * true : read command process successfully 406 - * false : register not support 407 - * pRegisterValue : It must be a resident buffer due to 408 - * asynchronous read register. 409 - */ 410 - unsigned char Wb35Reg_Read(struct hw_data *pHwData, u16 RegisterNo, 411 - u32 *pRegisterValue) 412 - { 413 - struct wb35_reg *reg = &pHwData->reg; 414 - struct usb_ctrlrequest *dr; 415 - struct urb *urb; 416 - struct wb35_reg_queue *reg_queue; 417 - u16 UrbSize; 418 - 419 - /* Module shutdown */ 420 - if (pHwData->SurpriseRemove) 421 - return false; 422 - 423 - /* update the variable by send Urb to read register */ 424 - UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest); 425 - reg_queue = kzalloc(UrbSize, GFP_ATOMIC); 426 - if (reg_queue == NULL) 427 - return false; 428 - 429 - urb = usb_alloc_urb(0, GFP_ATOMIC); 430 - if (urb == NULL) { 431 - kfree(reg_queue); 432 - return false; 433 - } 434 - reg_queue->DIRECT = 0; /* read register */ 435 - reg_queue->INDEX = RegisterNo; 436 - reg_queue->pBuffer = pRegisterValue; 437 - dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); 438 - dr->bRequestType = USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN; 439 - dr->bRequest = 0x01; /* USB or vendor-defined request code, burst mode */ 440 - dr->wValue = cpu_to_le16(0x0); 441 - dr->wIndex = cpu_to_le16(RegisterNo); 442 - dr->wLength = cpu_to_le16(4); 443 - 444 - /* Enter the sending queue */ 445 - reg_queue->Next = NULL; 446 - reg_queue->pUsbReq = dr; 447 - reg_queue->urb = urb; 448 - spin_lock_irq(&reg->EP0VM_spin_lock); 449 - if (reg->reg_first == NULL) 450 - reg->reg_first = reg_queue; 451 - else 452 - reg->reg_last->Next = reg_queue; 453 - reg->reg_last = reg_queue; 454 - 455 - spin_unlock_irq(&reg->EP0VM_spin_lock); 456 - 457 - /* Start EP0VM */ 458 - Wb35Reg_EP0VM_start(pHwData); 459 - 460 - return true; 461 - } 462 - 463 - 464 - void Wb35Reg_EP0VM_start(struct hw_data *pHwData) 465 - { 466 - struct wb35_reg *reg = &pHwData->reg; 467 - 468 - if (atomic_inc_return(&reg->RegFireCount) == 1) { 469 - reg->EP0vm_state = VM_RUNNING; 470 - Wb35Reg_EP0VM(pHwData); 471 - } else 472 - atomic_dec(&reg->RegFireCount); 473 - } 474 - 475 - void Wb35Reg_EP0VM(struct hw_data *pHwData) 476 - { 477 - struct wb35_reg *reg = &pHwData->reg; 478 - struct urb *urb; 479 - struct usb_ctrlrequest *dr; 480 - u32 *pBuffer; 481 - int ret = -1; 482 - struct wb35_reg_queue *reg_queue; 483 - 484 - 485 - if (reg->SyncIoPause) 486 - goto cleanup; 487 - 488 - if (pHwData->SurpriseRemove) 489 - goto cleanup; 490 - 491 - /* Get the register data and send to USB through Irp */ 492 - spin_lock_irq(&reg->EP0VM_spin_lock); 493 - reg_queue = reg->reg_first; 494 - spin_unlock_irq(&reg->EP0VM_spin_lock); 495 - 496 - if (!reg_queue) 497 - goto cleanup; 498 - 499 - /* Get an Urb, send it */ 500 - urb = (struct urb *)reg_queue->urb; 501 - 502 - dr = reg_queue->pUsbReq; 503 - urb = reg_queue->urb; 504 - pBuffer = reg_queue->pBuffer; 505 - if (reg_queue->DIRECT == 1) /* output */ 506 - pBuffer = &reg_queue->VALUE; 507 - 508 - usb_fill_control_urb(urb, pHwData->udev, 509 - REG_DIRECTION(pHwData->udev, reg_queue), 510 - (u8 *)dr, pBuffer, cpu_to_le16(dr->wLength), 511 - Wb35Reg_EP0VM_complete, (void *)pHwData); 512 - 513 - reg->EP0vm_state = VM_RUNNING; 514 - 515 - ret = usb_submit_urb(urb, GFP_ATOMIC); 516 - 517 - if (ret < 0) { 518 - pr_debug("EP0 Irp sending error\n"); 519 - goto cleanup; 520 - } 521 - return; 522 - 523 - cleanup: 524 - reg->EP0vm_state = VM_STOP; 525 - atomic_dec(&reg->RegFireCount); 526 - } 527 - 528 - 529 - void Wb35Reg_EP0VM_complete(struct urb *urb) 530 - { 531 - struct hw_data *pHwData = (struct hw_data *)urb->context; 532 - struct wb35_reg *reg = &pHwData->reg; 533 - struct wb35_reg_queue *reg_queue; 534 - 535 - 536 - /* Variable setting */ 537 - reg->EP0vm_state = VM_COMPLETED; 538 - reg->EP0VM_status = urb->status; 539 - 540 - if (pHwData->SurpriseRemove) { /* Let WbWlanHalt to handle surprise remove */ 541 - reg->EP0vm_state = VM_STOP; 542 - atomic_dec(&reg->RegFireCount); 543 - } else { 544 - /* Complete to send, remove the URB from the first */ 545 - spin_lock_irq(&reg->EP0VM_spin_lock); 546 - reg_queue = reg->reg_first; 547 - if (reg_queue == reg->reg_last) 548 - reg->reg_last = NULL; 549 - reg->reg_first = reg->reg_first->Next; 550 - spin_unlock_irq(&reg->EP0VM_spin_lock); 551 - 552 - if (reg->EP0VM_status) { 553 - pr_debug("EP0 IoCompleteRoutine return error\n"); 554 - reg->EP0vm_state = VM_STOP; 555 - pHwData->SurpriseRemove = 1; 556 - } else { 557 - /* Success. Update the result */ 558 - 559 - /* Start the next send */ 560 - Wb35Reg_EP0VM(pHwData); 561 - } 562 - 563 - kfree(reg_queue); 564 - } 565 - 566 - usb_free_urb(urb); 567 - } 568 - 569 - 570 - void Wb35Reg_destroy(struct hw_data *pHwData) 571 - { 572 - struct wb35_reg *reg = &pHwData->reg; 573 - struct urb *urb; 574 - struct wb35_reg_queue *reg_queue; 575 - 576 - Uxx_power_off_procedure(pHwData); 577 - 578 - /* Wait for Reg operation completed */ 579 - do { 580 - msleep(10); /* Delay for waiting function enter */ 581 - } while (reg->EP0vm_state != VM_STOP); 582 - msleep(10); /* Delay for waiting function enter */ 583 - 584 - /* Release all the data in RegQueue */ 585 - spin_lock_irq(&reg->EP0VM_spin_lock); 586 - reg_queue = reg->reg_first; 587 - while (reg_queue) { 588 - if (reg_queue == reg->reg_last) 589 - reg->reg_last = NULL; 590 - reg->reg_first = reg->reg_first->Next; 591 - 592 - urb = reg_queue->urb; 593 - spin_unlock_irq(&reg->EP0VM_spin_lock); 594 - if (urb) { 595 - usb_free_urb(urb); 596 - kfree(reg_queue); 597 - } else { 598 - pr_debug("EP0 queue release error\n"); 599 - } 600 - spin_lock_irq(&reg->EP0VM_spin_lock); 601 - 602 - reg_queue = reg->reg_first; 603 - } 604 - spin_unlock_irq(&reg->EP0VM_spin_lock); 605 - } 606 - 607 - /* 608 - * ======================================================================= 609 - * The function can be run in passive-level only. 610 - * ========================================================================= 611 - */ 612 - unsigned char Wb35Reg_initial(struct hw_data *pHwData) 613 - { 614 - struct wb35_reg *reg = &pHwData->reg; 615 - u32 ltmp; 616 - u32 SoftwareSet, VCO_trim, TxVga, Region_ScanInterval; 617 - 618 - /* Spin lock is acquired for read and write IRP command */ 619 - spin_lock_init(&reg->EP0VM_spin_lock); 620 - 621 - /* Getting RF module type from EEPROM */ 622 - Wb35Reg_WriteSync(pHwData, 0x03b4, 0x080d0000); /* Start EEPROM access + Read + address(0x0d) */ 623 - Wb35Reg_ReadSync(pHwData, 0x03b4, &ltmp); 624 - 625 - /* Update RF module type and determine the PHY type by inf or EEPROM */ 626 - reg->EEPROMPhyType = (u8)(ltmp & 0xff); 627 - /* 628 - * 0 V MAX2825, 1 V MAX2827, 2 V MAX2828, 3 V MAX2829 629 - * 16V AL2230, 17 - AL7230, 18 - AL2230S 630 - * 32 Reserved 631 - * 33 - W89RF242(TxVGA 0~19), 34 - W89RF242(TxVGA 0~34) 632 - */ 633 - if (reg->EEPROMPhyType != RF_DECIDE_BY_INF) { 634 - if ((reg->EEPROMPhyType == RF_MAXIM_2825) || 635 - (reg->EEPROMPhyType == RF_MAXIM_2827) || 636 - (reg->EEPROMPhyType == RF_MAXIM_2828) || 637 - (reg->EEPROMPhyType == RF_MAXIM_2829) || 638 - (reg->EEPROMPhyType == RF_MAXIM_V1) || 639 - (reg->EEPROMPhyType == RF_AIROHA_2230) || 640 - (reg->EEPROMPhyType == RF_AIROHA_2230S) || 641 - (reg->EEPROMPhyType == RF_AIROHA_7230) || 642 - (reg->EEPROMPhyType == RF_WB_242) || 643 - (reg->EEPROMPhyType == RF_WB_242_1)) 644 - pHwData->phy_type = reg->EEPROMPhyType; 645 - } 646 - 647 - /* Power On procedure running. The relative parameter will be set according to phy_type */ 648 - Uxx_power_on_procedure(pHwData); 649 - 650 - /* Reading MAC address */ 651 - Uxx_ReadEthernetAddress(pHwData); 652 - 653 - /* Read VCO trim for RF parameter */ 654 - Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08200000); 655 - Wb35Reg_ReadSync(pHwData, 0x03b4, &VCO_trim); 656 - 657 - /* Read Antenna On/Off of software flag */ 658 - Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08210000); 659 - Wb35Reg_ReadSync(pHwData, 0x03b4, &SoftwareSet); 660 - 661 - /* Read TXVGA */ 662 - Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08100000); 663 - Wb35Reg_ReadSync(pHwData, 0x03b4, &TxVga); 664 - 665 - /* Get Scan interval setting from EEPROM offset 0x1c */ 666 - Wb35Reg_WriteSync(pHwData, 0x03b4, 0x081d0000); 667 - Wb35Reg_ReadSync(pHwData, 0x03b4, &Region_ScanInterval); 668 - 669 - /* Update Ethernet address */ 670 - memcpy(pHwData->CurrentMacAddress, pHwData->PermanentMacAddress, ETH_ALEN); 671 - 672 - /* Update software variable */ 673 - pHwData->SoftwareSet = (u16)(SoftwareSet & 0xffff); 674 - TxVga &= 0x000000ff; 675 - pHwData->PowerIndexFromEEPROM = (u8)TxVga; 676 - pHwData->VCO_trim = (u8)VCO_trim & 0xff; 677 - if (pHwData->VCO_trim == 0xff) 678 - pHwData->VCO_trim = 0x28; 679 - 680 - reg->EEPROMRegion = (u8)(Region_ScanInterval >> 8); 681 - if (reg->EEPROMRegion < 1 || reg->EEPROMRegion > 6) 682 - reg->EEPROMRegion = REGION_AUTO; 683 - 684 - /* For Get Tx VGA from EEPROM */ 685 - GetTxVgaFromEEPROM(pHwData); 686 - 687 - /* Set Scan Interval */ 688 - pHwData->Scan_Interval = (u8)(Region_ScanInterval & 0xff) * 10; 689 - if ((pHwData->Scan_Interval == 2550) || (pHwData->Scan_Interval < 10)) /* Is default setting 0xff * 10 */ 690 - pHwData->Scan_Interval = SCAN_MAX_CHNL_TIME; 691 - 692 - /* Initial register */ 693 - RFSynthesizer_initial(pHwData); 694 - 695 - BBProcessor_initial(pHwData); /* Async write, must wait until complete */ 696 - 697 - Wb35Reg_phy_calibration(pHwData); 698 - 699 - Mxx_initial(pHwData); 700 - Dxx_initial(pHwData); 701 - 702 - if (pHwData->SurpriseRemove) 703 - return false; 704 - else 705 - return true; /* Initial fail */ 706 - } 707 - 708 - /* 709 - * ================================================================ 710 - * CardComputeCrc -- 711 - * 712 - * Description: 713 - * Runs the AUTODIN II CRC algorithm on the buffers Buffer length. 714 - * 715 - * Arguments: 716 - * Buffer - the input buffer 717 - * Length - the length of Buffer 718 - * 719 - * Return Value: 720 - * The 32-bit CRC value. 721 - * =================================================================== 722 - */ 723 - u32 CardComputeCrc(u8 *Buffer, u32 Length) 724 - { 725 - u32 Crc, Carry; 726 - u32 i, j; 727 - u8 CurByte; 728 - 729 - Crc = 0xffffffff; 730 - 731 - for (i = 0; i < Length; i++) { 732 - CurByte = Buffer[i]; 733 - for (j = 0; j < 8; j++) { 734 - Carry = ((Crc & 0x80000000) ? 1 : 0) ^ (CurByte & 0x01); 735 - Crc <<= 1; 736 - CurByte >>= 1; 737 - if (Carry) 738 - Crc = (Crc ^ 0x04c11db6) | Carry; 739 - } 740 - } 741 - return Crc; 742 - } 743 - 744 - 745 - /* 746 - * ================================================================== 747 - * BitReverse -- 748 - * Reverse the bits in the input argument, dwData, which is 749 - * regarded as a string of bits with the length, DataLength. 750 - * 751 - * Arguments: 752 - * dwData : 753 - * DataLength : 754 - * 755 - * Return: 756 - * The converted value. 757 - * ================================================================== 758 - */ 759 - u32 BitReverse(u32 dwData, u32 DataLength) 760 - { 761 - u32 HalfLength, i, j; 762 - u32 BitA, BitB; 763 - 764 - if (DataLength <= 0) 765 - return 0; /* No conversion is done. */ 766 - dwData = dwData & (0xffffffff >> (32 - DataLength)); 767 - 768 - HalfLength = DataLength / 2; 769 - for (i = 0, j = DataLength - 1; i < HalfLength; i++, j--) { 770 - BitA = GetBit(dwData, i); 771 - BitB = GetBit(dwData, j); 772 - if (BitA && !BitB) { 773 - dwData = ClearBit(dwData, i); 774 - dwData = SetBit(dwData, j); 775 - } else if (!BitA && BitB) { 776 - dwData = SetBit(dwData, i); 777 - dwData = ClearBit(dwData, j); 778 - } else { 779 - /* Do nothing since these two bits are of the save values. */ 780 - } 781 - } 782 - return dwData; 783 - } 784 - 785 - void Wb35Reg_phy_calibration(struct hw_data *pHwData) 786 - { 787 - u32 BB3c, BB54; 788 - 789 - if ((pHwData->phy_type == RF_WB_242) || 790 - (pHwData->phy_type == RF_WB_242_1)) { 791 - phy_calibration_winbond(pHwData, 2412); /* Sync operation */ 792 - Wb35Reg_ReadSync(pHwData, 0x103c, &BB3c); 793 - Wb35Reg_ReadSync(pHwData, 0x1054, &BB54); 794 - 795 - pHwData->BB3c_cal = BB3c; 796 - pHwData->BB54_cal = BB54; 797 - 798 - RFSynthesizer_initial(pHwData); 799 - BBProcessor_initial(pHwData); /* Async operation */ 800 - 801 - Wb35Reg_WriteSync(pHwData, 0x103c, BB3c); 802 - Wb35Reg_WriteSync(pHwData, 0x1054, BB54); 803 - } 804 - } 805 - 806 -
-65
drivers/staging/winbond/wb35reg_f.h
··· 1 - #ifndef __WINBOND_WB35REG_F_H 2 - #define __WINBOND_WB35REG_F_H 3 - 4 - #include "wbhal.h" 5 - 6 - /* 7 - * ==================================== 8 - * Interface function declare 9 - * ==================================== 10 - */ 11 - unsigned char Wb35Reg_initial(struct hw_data *hw_data); 12 - void Uxx_power_on_procedure(struct hw_data *hw_data); 13 - void Uxx_power_off_procedure(struct hw_data *hw_data); 14 - void Uxx_ReadEthernetAddress(struct hw_data *hw_data); 15 - void Dxx_initial(struct hw_data *hw_data); 16 - void Mxx_initial(struct hw_data *hw_data); 17 - void RFSynthesizer_initial(struct hw_data *hw_data); 18 - void RFSynthesizer_SwitchingChannel(struct hw_data *hw_data, struct chan_info channel); 19 - void BBProcessor_initial(struct hw_data *hw_data); 20 - void BBProcessor_RateChanging(struct hw_data *hw_data, u8 rate); 21 - u8 RFSynthesizer_SetPowerIndex(struct hw_data *hw_data, u8 power_index); 22 - u8 RFSynthesizer_SetMaxim2828_24Power(struct hw_data *, u8 index); 23 - u8 RFSynthesizer_SetMaxim2828_50Power(struct hw_data *, u8 index); 24 - u8 RFSynthesizer_SetMaxim2827_24Power(struct hw_data *, u8 index); 25 - u8 RFSynthesizer_SetMaxim2827_50Power(struct hw_data *, u8 index); 26 - u8 RFSynthesizer_SetMaxim2825Power(struct hw_data *, u8 index); 27 - u8 RFSynthesizer_SetAiroha2230Power(struct hw_data *, u8 index); 28 - u8 RFSynthesizer_SetAiroha7230Power(struct hw_data *, u8 index); 29 - u8 RFSynthesizer_SetWinbond242Power(struct hw_data *, u8 index); 30 - void GetTxVgaFromEEPROM(struct hw_data *hw_data); 31 - void EEPROMTxVgaAdjust(struct hw_data *hw_data); 32 - 33 - #define RFWriteControlData(_A, _V) Wb35Reg_Write(_A, 0x0864, _V) 34 - 35 - void Wb35Reg_destroy(struct hw_data *hw_data); 36 - 37 - unsigned char Wb35Reg_Read(struct hw_data *hw_data, u16 register_no, u32 *register_value); 38 - unsigned char Wb35Reg_ReadSync(struct hw_data *hw_data, u16 register_no, u32 *register_value); 39 - unsigned char Wb35Reg_Write(struct hw_data *hw_data, u16 register_no, u32 register_value); 40 - unsigned char Wb35Reg_WriteSync(struct hw_data *hw_data, u16 register_no, u32 register_value); 41 - unsigned char Wb35Reg_WriteWithCallbackValue(struct hw_data *hw_data, 42 - u16 register_no, 43 - u32 register_value, 44 - s8 *value, 45 - s8 len); 46 - unsigned char Wb35Reg_BurstWrite(struct hw_data *hw_data, 47 - u16 register_no, 48 - u32 *register_data, 49 - u8 number_of_data, 50 - u8 flag); 51 - 52 - void Wb35Reg_EP0VM(struct hw_data *hw_data); 53 - void Wb35Reg_EP0VM_start(struct hw_data *hw_data); 54 - void Wb35Reg_EP0VM_complete(struct urb *urb); 55 - 56 - u32 BitReverse(u32 data, u32 data_length); 57 - 58 - void CardGetMulticastBit(u8 address[MAC_ADDR_LENGTH], u8 *byte, u8 *value); 59 - u32 CardComputeCrc(u8 *buffer, u32 length); 60 - 61 - void Wb35Reg_phy_calibration(struct hw_data *hw_data); 62 - void Wb35Reg_Update(struct hw_data *hw_data, u16 register_no, u32 register_value); 63 - unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *hw_data); 64 - 65 - #endif
-240
drivers/staging/winbond/wb35reg_s.h
··· 1 - #ifndef __WINBOND_WB35REG_S_H 2 - #define __WINBOND_WB35REG_S_H 3 - 4 - #include <linux/spinlock.h> 5 - #include <linux/types.h> 6 - #include <linux/atomic.h> 7 - 8 - struct hw_data; 9 - 10 - /* ========================================================================= 11 - * 12 - * HAL setting function 13 - * 14 - * ======================================== 15 - * |Uxx| |Dxx| |Mxx| |BB| |RF| 16 - * ======================================== 17 - * | | 18 - * Wb35Reg_Read Wb35Reg_Write 19 - * 20 - * ---------------------------------------- 21 - * WbUsb_CallUSBDASync supplied By WbUsb module 22 - * ========================================================================== 23 - */ 24 - #define GetBit(dwData, i) (dwData & (0x00000001 << i)) 25 - #define SetBit(dwData, i) (dwData | (0x00000001 << i)) 26 - #define ClearBit(dwData, i) (dwData & ~(0x00000001 << i)) 27 - 28 - #define IGNORE_INCREMENT 0 29 - #define AUTO_INCREMENT 0 30 - #define NO_INCREMENT 1 31 - #define REG_DIRECTION(_x, _y) ((_y)->DIRECT == 0 ? usb_rcvctrlpipe(_x, 0) : usb_sndctrlpipe(_x, 0)) 32 - #define REG_BUF_SIZE(_x) ((_x)->bRequest == 0x04 ? cpu_to_le16((_x)->wLength) : 4) 33 - 34 - #define BB48_DEFAULT_AL2230_11B 0x0033447c 35 - #define BB4C_DEFAULT_AL2230_11B 0x0A00FEFF 36 - #define BB48_DEFAULT_AL2230_11G 0x00332C1B 37 - #define BB4C_DEFAULT_AL2230_11G 0x0A00FEFF 38 - 39 - 40 - #define BB48_DEFAULT_WB242_11B 0x00292315 /* backoff 2dB */ 41 - #define BB4C_DEFAULT_WB242_11B 0x0800FEFF /* backoff 2dB */ 42 - #define BB48_DEFAULT_WB242_11G 0x00453B24 43 - #define BB4C_DEFAULT_WB242_11G 0x0E00FEFF 44 - 45 - /* 46 - * ==================================== 47 - * Default setting for Mxx 48 - * ==================================== 49 - */ 50 - #define DEFAULT_CWMIN 31 /* (M2C) CWmin. Its value is in the range 0-31. */ 51 - #define DEFAULT_CWMAX 1023 /* (M2C) CWmax. Its value is in the range 0-1023. */ 52 - #define DEFAULT_AID 1 /* (M34) AID. Its value is in the range 1-2007. */ 53 - 54 - #define DEFAULT_RATE_RETRY_LIMIT 2 /* (M38) as named */ 55 - 56 - #define DEFAULT_LONG_RETRY_LIMIT 7 /* (M38) LongRetryLimit. Its value is in the range 0-15. */ 57 - #define DEFAULT_SHORT_RETRY_LIMIT 7 /* (M38) ShortRetryLimit. Its value is in the range 0-15. */ 58 - #define DEFAULT_PIFST 25 /* (M3C) PIFS Time. Its value is in the range 0-65535. */ 59 - #define DEFAULT_EIFST 354 /* (M3C) EIFS Time. Its value is in the range 0-1048575. */ 60 - #define DEFAULT_DIFST 45 /* (M3C) DIFS Time. Its value is in the range 0-65535. */ 61 - #define DEFAULT_SIFST 5 /* (M3C) SIFS Time. Its value is in the range 0-65535. */ 62 - #define DEFAULT_OSIFST 10 /* (M3C) Original SIFS Time. Its value is in the range 0-15. */ 63 - #define DEFAULT_ATIMWD 0 /* (M40) ATIM Window. Its value is in the range 0-65535. */ 64 - #define DEFAULT_SLOT_TIME 20 /* (M40) ($) SlotTime. Its value is in the range 0-255. */ 65 - #define DEFAULT_MAX_TX_MSDU_LIFE_TIME 512 /* (M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295. */ 66 - #define DEFAULT_BEACON_INTERVAL 500 /* (M48) Beacon Interval. Its value is in the range 0-65535. */ 67 - #define DEFAULT_PROBE_DELAY_TIME 200 /* (M48) Probe Delay Time. Its value is in the range 0-65535. */ 68 - #define DEFAULT_PROTOCOL_VERSION 0 /* (M4C) */ 69 - #define DEFAULT_MAC_POWER_STATE 2 /* (M4C) 2: MAC at power active */ 70 - #define DEFAULT_DTIM_ALERT_TIME 0 71 - 72 - 73 - struct wb35_reg_queue { 74 - struct urb *urb; 75 - void *pUsbReq; 76 - void *Next; 77 - union { 78 - u32 VALUE; 79 - u32 *pBuffer; 80 - }; 81 - u8 RESERVED[4]; /* space reserved for communication */ 82 - u16 INDEX; /* For storing the register index */ 83 - u8 RESERVED_VALID; /* Indicate whether the RESERVED space is valid at this command. */ 84 - u8 DIRECT; /* 0:In 1:Out */ 85 - }; 86 - 87 - /* 88 - * ==================================== 89 - * Internal variable for module 90 - * ==================================== 91 - */ 92 - #define MAX_SQ3_FILTER_SIZE 5 93 - struct wb35_reg { 94 - /* 95 - * ============================ 96 - * Register Bank backup 97 - * ============================ 98 - */ 99 - u32 U1B0; /* bit16 record the h/w radio on/off status */ 100 - u32 U1BC_LEDConfigure; 101 - u32 D00_DmaControl; 102 - u32 M00_MacControl; 103 - union { 104 - struct { 105 - u32 M04_MulticastAddress1; 106 - u32 M08_MulticastAddress2; 107 - }; 108 - u8 Multicast[8]; /* contents of card multicast registers */ 109 - }; 110 - 111 - u32 M24_MacControl; 112 - u32 M28_MacControl; 113 - u32 M2C_MacControl; 114 - u32 M38_MacControl; 115 - u32 M3C_MacControl; 116 - u32 M40_MacControl; 117 - u32 M44_MacControl; 118 - u32 M48_MacControl; 119 - u32 M4C_MacStatus; 120 - u32 M60_MacControl; 121 - u32 M68_MacControl; 122 - u32 M70_MacControl; 123 - u32 M74_MacControl; 124 - u32 M78_ERPInformation; 125 - u32 M7C_MacControl; 126 - u32 M80_MacControl; 127 - u32 M84_MacControl; 128 - u32 M88_MacControl; 129 - u32 M98_MacControl; 130 - 131 - /* Baseband register */ 132 - u32 BB0C; /* Used for LNA calculation */ 133 - u32 BB2C; 134 - u32 BB30; /* 11b acquisition control register */ 135 - u32 BB3C; 136 - u32 BB48; 137 - u32 BB4C; 138 - u32 BB50; /* mode control register */ 139 - u32 BB54; 140 - u32 BB58; /* IQ_ALPHA */ 141 - u32 BB5C; /* For test */ 142 - u32 BB60; /* for WTO read value */ 143 - 144 - /* VM */ 145 - spinlock_t EP0VM_spin_lock; /* 4B */ 146 - u32 EP0VM_status; /* $$ */ 147 - struct wb35_reg_queue *reg_first; 148 - struct wb35_reg_queue *reg_last; 149 - atomic_t RegFireCount; 150 - 151 - /* Hardware status */ 152 - u8 EP0vm_state; 153 - u8 mac_power_save; 154 - u8 EEPROMPhyType; /* 155 - * 0 ~ 15 for Maxim (0 ĄV MAX2825, 1 ĄV MAX2827, 2 ĄV MAX2828, 3 ĄV MAX2829), 156 - * 16 ~ 31 for Airoha (16 ĄV AL2230, 11 - AL7230) 157 - * 32 ~ Reserved 158 - * 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step) 159 - * 48 ~ 255 ARE RESERVED. 160 - */ 161 - u8 EEPROMRegion; /* Region setting in EEPROM */ 162 - 163 - u32 SyncIoPause; /* If user use the Sync Io to access Hw, then pause the async access */ 164 - 165 - u8 LNAValue[4]; /* Table for speed up running */ 166 - u32 SQ3_filter[MAX_SQ3_FILTER_SIZE]; 167 - u32 SQ3_index; 168 - }; 169 - 170 - /* ===================================================================== 171 - * Function declaration 172 - * ===================================================================== 173 - */ 174 - void hal_remove_mapping_key(struct hw_data *hw_data, u8 *mac_addr); 175 - void hal_remove_default_key(struct hw_data *hw_data, u32 index); 176 - unsigned char hal_set_mapping_key(struct hw_data *adapter, u8 *mac_addr, 177 - u8 null_key, u8 wep_on, u8 *tx_tsc, 178 - u8 *rx_tsc, u8 key_type, u8 key_len, 179 - u8 *key_data); 180 - unsigned char hal_set_default_key(struct hw_data *adapter, u8 index, 181 - u8 null_key, u8 wep_on, u8 *tx_tsc, 182 - u8 *rx_tsc, u8 key_type, u8 key_len, 183 - u8 *key_data); 184 - void hal_clear_all_default_key(struct hw_data *hw_data); 185 - void hal_clear_all_group_key(struct hw_data *hw_data); 186 - void hal_clear_all_mapping_key(struct hw_data *hw_data); 187 - void hal_clear_all_key(struct hw_data *hw_data); 188 - void hal_set_power_save_mode(struct hw_data *hw_data, unsigned char power_save, 189 - unsigned char wakeup, unsigned char dtim); 190 - void hal_get_power_save_mode(struct hw_data *hw_data, u8 *in_pwr_save); 191 - void hal_set_slot_time(struct hw_data *hw_data, u8 type); 192 - 193 - #define hal_set_atim_window(_A, _ATM) 194 - 195 - void hal_start_bss(struct hw_data *hw_data, u8 mac_op_mode); 196 - 197 - /* 0:BSS STA 1:IBSS STA */ 198 - void hal_join_request(struct hw_data *hw_data, u8 bss_type); 199 - 200 - void hal_stop_sync_bss(struct hw_data *hw_data); 201 - void hal_resume_sync_bss(struct hw_data *hw_data); 202 - void hal_set_aid(struct hw_data *hw_data, u16 aid); 203 - void hal_set_bssid(struct hw_data *hw_data, u8 *bssid); 204 - void hal_get_bssid(struct hw_data *hw_data, u8 *bssid); 205 - void hal_set_listen_interval(struct hw_data *hw_data, u16 listen_interval); 206 - void hal_set_cap_info(struct hw_data *hw_data, u16 capability_info); 207 - void hal_set_ssid(struct hw_data *hw_data, u8 *ssid, u8 ssid_len); 208 - void hal_start_tx0(struct hw_data *hw_data); 209 - 210 - #define hal_get_cwmin(_A) ((_A)->cwmin) 211 - 212 - void hal_set_cwmax(struct hw_data *hw_data, u16 cwin_max); 213 - 214 - #define hal_get_cwmax(_A) ((_A)->cwmax) 215 - 216 - void hal_set_rsn_wpa(struct hw_data *hw_data, u32 *rsn_ie_bitmap, 217 - u32 *rsn_oui_type , unsigned char desired_auth_mode); 218 - void hal_set_connect_info(struct hw_data *hw_data, unsigned char bo_connect); 219 - u8 hal_get_est_sq3(struct hw_data *hw_data, u8 count); 220 - void hal_descriptor_indicate(struct hw_data *hw_data, 221 - struct wb35_descriptor *des); 222 - u8 hal_get_antenna_number(struct hw_data *hw_data); 223 - u32 hal_get_bss_pk_cnt(struct hw_data *hw_data); 224 - 225 - #define hal_get_region_from_EEPROM(_A) ((_A)->reg.EEPROMRegion) 226 - #define hal_get_tx_buffer(_A, _B) Wb35Tx_get_tx_buffer(_A, _B) 227 - #define hal_software_set(_A) (_A->SoftwareSet) 228 - #define hal_driver_init_OK(_A) (_A->IsInitOK) 229 - #define hal_rssi_boundary_high(_A) (_A->RSSI_high) 230 - #define hal_rssi_boundary_low(_A) (_A->RSSI_low) 231 - #define hal_scan_interval(_A) (_A->Scan_Interval) 232 - 233 - #define PHY_DEBUG(msg, args...) 234 - 235 - /* return 100ms count */ 236 - #define hal_get_time_count(_P) (_P->time_count / 10) 237 - 238 - #define hal_ibss_disconnect(_A) (hal_stop_sync_bss(_A)) 239 - 240 - #endif
-358
drivers/staging/winbond/wb35rx.c
··· 1 - /* 2 - * ============================================================================ 3 - * Copyright (c) 1996-2002 Winbond Electronic Corporation 4 - * 5 - * Module Name: 6 - * Wb35Rx.c 7 - * 8 - * Abstract: 9 - * Processing the Rx message from down layer 10 - * 11 - * ============================================================================ 12 - */ 13 - #include <linux/usb.h> 14 - #include <linux/slab.h> 15 - 16 - #include "core.h" 17 - #include "wb35rx_f.h" 18 - 19 - static void packet_came(struct ieee80211_hw *hw, char *pRxBufferAddress, 20 - int PacketSize) 21 - { 22 - struct wbsoft_priv *priv = hw->priv; 23 - struct sk_buff *skb; 24 - struct ieee80211_rx_status rx_status = {0}; 25 - 26 - if (!priv->enabled) 27 - return; 28 - 29 - skb = dev_alloc_skb(PacketSize); 30 - if (!skb) { 31 - printk("Not enough memory for packet, FIXME\n"); 32 - return; 33 - } 34 - 35 - memcpy(skb_put(skb, PacketSize), pRxBufferAddress, PacketSize); 36 - 37 - memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status)); 38 - ieee80211_rx_irqsafe(hw, skb); 39 - } 40 - 41 - static void Wb35Rx_adjust(struct wb35_descriptor *pRxDes) 42 - { 43 - u32 *pRxBufferAddress; 44 - u32 DecryptionMethod; 45 - u32 i; 46 - u16 BufferSize; 47 - 48 - DecryptionMethod = pRxDes->R01.R01_decryption_method; 49 - pRxBufferAddress = pRxDes->buffer_address[0]; 50 - BufferSize = pRxDes->buffer_size[0]; 51 - 52 - /* Adjust the last part of data. Only data left */ 53 - BufferSize -= 4; /* For CRC-32 */ 54 - if (DecryptionMethod) 55 - BufferSize -= 4; 56 - if (DecryptionMethod == 3) /* For CCMP */ 57 - BufferSize -= 4; 58 - 59 - /* Adjust the IV field which after 802.11 header and ICV field. */ 60 - if (DecryptionMethod == 1) { /* For WEP */ 61 - for (i = 6; i > 0; i--) 62 - pRxBufferAddress[i] = pRxBufferAddress[i - 1]; 63 - pRxDes->buffer_address[0] = pRxBufferAddress + 1; 64 - BufferSize -= 4; /* 4 byte for IV */ 65 - } else if (DecryptionMethod) { /* For TKIP and CCMP */ 66 - for (i = 7; i > 1; i--) 67 - pRxBufferAddress[i] = pRxBufferAddress[i - 2]; 68 - /* Update the descriptor, shift 8 byte */ 69 - pRxDes->buffer_address[0] = pRxBufferAddress + 2; 70 - BufferSize -= 8; /* 8 byte for IV + ICV */ 71 - } 72 - pRxDes->buffer_size[0] = BufferSize; 73 - } 74 - 75 - static u16 Wb35Rx_indicate(struct ieee80211_hw *hw) 76 - { 77 - struct wbsoft_priv *priv = hw->priv; 78 - struct hw_data *pHwData = &priv->sHwData; 79 - struct wb35_descriptor RxDes; 80 - struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; 81 - u8 *pRxBufferAddress; 82 - u16 PacketSize; 83 - u16 stmp, BufferSize, stmp2 = 0; 84 - u32 RxBufferId; 85 - 86 - /* Only one thread be allowed to run into the following */ 87 - do { 88 - RxBufferId = pWb35Rx->RxProcessIndex; 89 - if (pWb35Rx->RxOwner[RxBufferId]) /* Owner by VM */ 90 - break; 91 - 92 - pWb35Rx->RxProcessIndex++; 93 - pWb35Rx->RxProcessIndex %= MAX_USB_RX_BUFFER_NUMBER; 94 - 95 - pRxBufferAddress = pWb35Rx->pDRx; 96 - BufferSize = pWb35Rx->RxBufferSize[RxBufferId]; 97 - 98 - /* Parse the bulkin buffer */ 99 - while (BufferSize >= 4) { 100 - /* Is ending? */ 101 - if ((cpu_to_le32(*(u32 *)pRxBufferAddress) & 0x0fffffff) == 102 - RX_END_TAG) 103 - break; 104 - 105 - /* Get the R00 R01 first */ 106 - RxDes.R00.value = le32_to_cpu(*(u32 *)pRxBufferAddress); 107 - PacketSize = (u16)RxDes.R00.R00_receive_byte_count; 108 - RxDes.R01.value = le32_to_cpu(*((u32 *)(pRxBufferAddress + 4))); 109 - /* For new DMA 4k */ 110 - if ((PacketSize & 0x03) > 0) 111 - PacketSize -= 4; 112 - 113 - /* Basic check for Rx length. Is length valid? */ 114 - if (PacketSize > MAX_PACKET_SIZE) { 115 - pr_debug("Serious ERROR : Rx data size too long, size =%d\n", 116 - PacketSize); 117 - pWb35Rx->EP3vm_state = VM_STOP; 118 - pWb35Rx->Ep3ErrorCount2++; 119 - break; 120 - } 121 - 122 - /* 123 - * Wb35Rx_indicate() is called synchronously so it isn't 124 - * necessary to set "RxDes.Desctriptor_ID = RxBufferID;" 125 - */ 126 - /* subtract 8 byte for 35's USB header length */ 127 - BufferSize -= 8; 128 - pRxBufferAddress += 8; 129 - 130 - RxDes.buffer_address[0] = pRxBufferAddress; 131 - RxDes.buffer_size[0] = PacketSize; 132 - RxDes.buffer_number = 1; 133 - RxDes.buffer_start_index = 0; 134 - RxDes.buffer_total_size = RxDes.buffer_size[0]; 135 - Wb35Rx_adjust(&RxDes); 136 - 137 - packet_came(hw, pRxBufferAddress, PacketSize); 138 - 139 - /* Move RxBuffer point to the next */ 140 - stmp = PacketSize + 3; 141 - stmp &= ~0x03; /* 4n alignment */ 142 - pRxBufferAddress += stmp; 143 - BufferSize -= stmp; 144 - stmp2 += stmp; 145 - } 146 - 147 - /* Reclaim resource */ 148 - pWb35Rx->RxOwner[RxBufferId] = 1; 149 - } while (true); 150 - return stmp2; 151 - } 152 - 153 - static void Wb35Rx(struct ieee80211_hw *hw); 154 - 155 - static void Wb35Rx_Complete(struct urb *urb) 156 - { 157 - struct ieee80211_hw *hw = urb->context; 158 - struct wbsoft_priv *priv = hw->priv; 159 - struct hw_data *pHwData = &priv->sHwData; 160 - struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; 161 - u8 *pRxBufferAddress; 162 - u32 SizeCheck; 163 - u16 BulkLength; 164 - u32 RxBufferId; 165 - struct R00_descriptor R00; 166 - 167 - /* Variable setting */ 168 - pWb35Rx->EP3vm_state = VM_COMPLETED; 169 - pWb35Rx->EP3VM_status = urb->status; /* Store the last result of Irp */ 170 - 171 - RxBufferId = pWb35Rx->CurrentRxBufferId; 172 - 173 - pRxBufferAddress = pWb35Rx->pDRx; 174 - BulkLength = (u16)urb->actual_length; 175 - 176 - /* The IRP is completed */ 177 - pWb35Rx->EP3vm_state = VM_COMPLETED; 178 - 179 - if (pHwData->SurpriseRemove) /* Must be here, or RxBufferId is invalid */ 180 - goto error; 181 - 182 - if (pWb35Rx->rx_halt) 183 - goto error; 184 - 185 - /* Start to process the data only in successful condition */ 186 - pWb35Rx->RxOwner[RxBufferId] = 0; /* Set the owner to driver */ 187 - R00.value = le32_to_cpu(*(u32 *)pRxBufferAddress); 188 - 189 - /* The URB is completed, check the result */ 190 - if (pWb35Rx->EP3VM_status != 0) { 191 - pr_debug("EP3 IoCompleteRoutine return error\n"); 192 - pWb35Rx->EP3vm_state = VM_STOP; 193 - goto error; 194 - } 195 - 196 - /* For recovering. check if operating in single USB mode */ 197 - if (!HAL_USB_MODE_BURST(pHwData)) { 198 - SizeCheck = R00.R00_receive_byte_count; 199 - if ((SizeCheck & 0x03) > 0) 200 - SizeCheck -= 4; 201 - SizeCheck = (SizeCheck + 3) & ~0x03; 202 - SizeCheck += 12; /* 8 + 4 badbeef */ 203 - if ((BulkLength > 1600) || 204 - (SizeCheck > 1600) || 205 - (BulkLength != SizeCheck) || 206 - (BulkLength == 0)) { /* Add for fail Urb */ 207 - pWb35Rx->EP3vm_state = VM_STOP; 208 - pWb35Rx->Ep3ErrorCount2++; 209 - } 210 - } 211 - 212 - /* Indicating the receiving data */ 213 - pWb35Rx->ByteReceived += BulkLength; 214 - pWb35Rx->RxBufferSize[RxBufferId] = BulkLength; 215 - 216 - if (!pWb35Rx->RxOwner[RxBufferId]) 217 - Wb35Rx_indicate(hw); 218 - 219 - kfree(pWb35Rx->pDRx); 220 - /* Do the next receive */ 221 - Wb35Rx(hw); 222 - return; 223 - 224 - error: 225 - pWb35Rx->RxOwner[RxBufferId] = 1; /* Set the owner to hardware */ 226 - atomic_dec(&pWb35Rx->RxFireCounter); 227 - pWb35Rx->EP3vm_state = VM_STOP; 228 - } 229 - 230 - /* This function cannot reentrain */ 231 - static void Wb35Rx(struct ieee80211_hw *hw) 232 - { 233 - struct wbsoft_priv *priv = hw->priv; 234 - struct hw_data *pHwData = &priv->sHwData; 235 - struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; 236 - u8 *pRxBufferAddress; 237 - struct urb *urb = pWb35Rx->RxUrb; 238 - int retv; 239 - u32 RxBufferId; 240 - 241 - /* Issuing URB */ 242 - if (pHwData->SurpriseRemove) 243 - goto error; 244 - 245 - if (pWb35Rx->rx_halt) 246 - goto error; 247 - 248 - /* Get RxBuffer's ID */ 249 - RxBufferId = pWb35Rx->RxBufferId; 250 - if (!pWb35Rx->RxOwner[RxBufferId]) { 251 - /* It's impossible to run here. */ 252 - pr_debug("Rx driver fifo unavailable\n"); 253 - goto error; 254 - } 255 - 256 - /* Update buffer point, then start to bulkin the data from USB */ 257 - pWb35Rx->RxBufferId++; 258 - pWb35Rx->RxBufferId %= MAX_USB_RX_BUFFER_NUMBER; 259 - 260 - pWb35Rx->CurrentRxBufferId = RxBufferId; 261 - 262 - pWb35Rx->pDRx = kzalloc(MAX_USB_RX_BUFFER, GFP_ATOMIC); 263 - if (!pWb35Rx->pDRx) { 264 - dev_info(&hw->wiphy->dev, "w35und: Rx memory alloc failed\n"); 265 - goto error; 266 - } 267 - pRxBufferAddress = pWb35Rx->pDRx; 268 - 269 - usb_fill_bulk_urb(urb, pHwData->udev, 270 - usb_rcvbulkpipe(pHwData->udev, 3), 271 - pRxBufferAddress, MAX_USB_RX_BUFFER, 272 - Wb35Rx_Complete, hw); 273 - 274 - pWb35Rx->EP3vm_state = VM_RUNNING; 275 - 276 - retv = usb_submit_urb(urb, GFP_ATOMIC); 277 - 278 - if (retv != 0) { 279 - dev_info(&hw->wiphy->dev, "Rx URB sending error\n"); 280 - goto error; 281 - } 282 - return; 283 - 284 - error: 285 - /* VM stop */ 286 - pWb35Rx->EP3vm_state = VM_STOP; 287 - atomic_dec(&pWb35Rx->RxFireCounter); 288 - } 289 - 290 - void Wb35Rx_start(struct ieee80211_hw *hw) 291 - { 292 - struct wbsoft_priv *priv = hw->priv; 293 - struct hw_data *pHwData = &priv->sHwData; 294 - struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; 295 - 296 - /* Allow only one thread to run into the Wb35Rx() function */ 297 - if (atomic_inc_return(&pWb35Rx->RxFireCounter) == 1) { 298 - pWb35Rx->EP3vm_state = VM_RUNNING; 299 - Wb35Rx(hw); 300 - } else 301 - atomic_dec(&pWb35Rx->RxFireCounter); 302 - } 303 - 304 - static void Wb35Rx_reset_descriptor(struct hw_data *pHwData) 305 - { 306 - struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; 307 - u32 i; 308 - 309 - pWb35Rx->ByteReceived = 0; 310 - pWb35Rx->RxProcessIndex = 0; 311 - pWb35Rx->RxBufferId = 0; 312 - pWb35Rx->EP3vm_state = VM_STOP; 313 - pWb35Rx->rx_halt = 0; 314 - 315 - /* Initial the Queue. The last buffer is reserved for used 316 - * if the Rx resource is unavailable. 317 - */ 318 - for (i = 0; i < MAX_USB_RX_BUFFER_NUMBER; i++) 319 - pWb35Rx->RxOwner[i] = 1; 320 - } 321 - 322 - unsigned char Wb35Rx_initial(struct hw_data *pHwData) 323 - { 324 - struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; 325 - 326 - /* Initial the Buffer Queue */ 327 - Wb35Rx_reset_descriptor(pHwData); 328 - 329 - pWb35Rx->RxUrb = usb_alloc_urb(0, GFP_ATOMIC); 330 - return !!pWb35Rx->RxUrb; 331 - } 332 - 333 - void Wb35Rx_stop(struct hw_data *pHwData) 334 - { 335 - struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; 336 - 337 - /* Canceling the Irp if already sends it out. */ 338 - if (pWb35Rx->EP3vm_state == VM_RUNNING) { 339 - /* Only use unlink, let Wb35Rx_destroy to free them */ 340 - usb_unlink_urb(pWb35Rx->RxUrb); 341 - pr_debug("EP3 Rx stop\n"); 342 - } 343 - } 344 - 345 - /* Needs process context */ 346 - void Wb35Rx_destroy(struct hw_data *pHwData) 347 - { 348 - struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; 349 - 350 - do { 351 - msleep(10); /* Delay for waiting function enter */ 352 - } while (pWb35Rx->EP3vm_state != VM_STOP); 353 - msleep(10); /* Delay for waiting function exit */ 354 - 355 - usb_free_urb(pWb35Rx->RxUrb); 356 - pr_debug("Wb35Rx_destroy OK\n"); 357 - } 358 -
-15
drivers/staging/winbond/wb35rx_f.h
··· 1 - #ifndef __WINBOND_WB35RX_F_H 2 - #define __WINBOND_WB35RX_F_H 3 - 4 - #include <net/mac80211.h> 5 - #include "wbhal.h" 6 - 7 - /* 8 - * Interface function declaration 9 - */ 10 - unsigned char Wb35Rx_initial(struct hw_data *pHwData); 11 - void Wb35Rx_destroy(struct hw_data *pHwData); 12 - void Wb35Rx_stop(struct hw_data *pHwData); 13 - void Wb35Rx_start(struct ieee80211_hw *hw); 14 - 15 - #endif
-44
drivers/staging/winbond/wb35rx_s.h
··· 1 - #ifndef __WINBOND_35RX_S_H 2 - #define __WINBOND_35RX_S_H 3 - 4 - /* Definition for this module used */ 5 - #define MAX_USB_RX_BUFFER 4096 /* This parameter must be 4096 931130.4.f */ 6 - #define MAX_USB_RX_BUFFER_NUMBER ETHERNET_RX_DESCRIPTORS /* Maximum 254, 255 is RESERVED ID */ 7 - #define RX_INTERFACE 0 /* Interface 1 */ 8 - #define RX_PIPE 2 /* Pipe 3 */ 9 - #define MAX_PACKET_SIZE 1600 /* 1568 = 8 + 1532 + 4 + 24(IV EIV MIC ICV CRC) for check DMA data 931130.4.g */ 10 - #define RX_END_TAG 0x0badbeef 11 - 12 - 13 - /* 14 - * Internal variable for module 15 - */ 16 - struct wb35_rx { 17 - u32 ByteReceived; /* For calculating throughput of BulkIn */ 18 - atomic_t RxFireCounter;/* Does Wb35Rx module fire? */ 19 - 20 - u8 RxBuffer[MAX_USB_RX_BUFFER_NUMBER][((MAX_USB_RX_BUFFER+3) & ~0x03)]; 21 - u16 RxBufferSize[((MAX_USB_RX_BUFFER_NUMBER+1) & ~0x01)]; 22 - u8 RxOwner[((MAX_USB_RX_BUFFER_NUMBER+3) & ~0x03)]; /* Ownership of buffer 0:SW 1:HW */ 23 - 24 - u32 RxProcessIndex; /* The next index to process */ 25 - u32 RxBufferId; 26 - u32 EP3vm_state; 27 - 28 - u32 rx_halt; /* For VM stopping */ 29 - 30 - u16 MoreDataSize; 31 - u16 PacketSize; 32 - 33 - u32 CurrentRxBufferId; /* For complete routine usage */ 34 - u32 Rx3UrbCancel; 35 - 36 - u32 LastR1; /* For RSSI reporting */ 37 - struct urb *RxUrb; 38 - u32 Ep3ErrorCount2; /* 20060625.1 Usbd for Rx DMA error count */ 39 - 40 - int EP3VM_status; 41 - u8 *pDRx; 42 - }; 43 - 44 - #endif /* __WINBOND_35RX_S_H */
-290
drivers/staging/winbond/wb35tx.c
··· 1 - /* 2 - * Copyright (c) 1996-2002 Winbond Electronic Corporation 3 - * 4 - * Module Name: 5 - * Wb35Tx.c 6 - * 7 - * Abstract: 8 - * Processing the Tx message and put into down layer 9 - * 10 - */ 11 - #include <linux/usb.h> 12 - #include <linux/gfp.h> 13 - 14 - #include "wb35tx_f.h" 15 - #include "mds_f.h" 16 - 17 - unsigned char 18 - Wb35Tx_get_tx_buffer(struct hw_data *pHwData, u8 **pBuffer) 19 - { 20 - struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; 21 - 22 - *pBuffer = pWb35Tx->TxBuffer[0]; 23 - return true; 24 - } 25 - 26 - static void Wb35Tx(struct wbsoft_priv *adapter); 27 - 28 - static void Wb35Tx_complete(struct urb *pUrb) 29 - { 30 - struct wbsoft_priv *adapter = pUrb->context; 31 - struct hw_data *pHwData = &adapter->sHwData; 32 - struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; 33 - struct wb35_mds *pMds = &adapter->Mds; 34 - 35 - printk("wb35: tx complete\n"); 36 - /* Variable setting */ 37 - pWb35Tx->EP4vm_state = VM_COMPLETED; 38 - pWb35Tx->EP4VM_status = pUrb->status; /* Store the last result of Irp */ 39 - /* Set the owner. Free the owner bit always. */ 40 - pMds->TxOwner[pWb35Tx->TxSendIndex] = 0; 41 - pWb35Tx->TxSendIndex++; 42 - pWb35Tx->TxSendIndex %= MAX_USB_TX_BUFFER_NUMBER; 43 - 44 - if (pHwData->SurpriseRemove) /* Let WbWlanHalt handle surprise remove */ 45 - goto error; 46 - 47 - if (pWb35Tx->tx_halt) 48 - goto error; 49 - 50 - /* The URB is completed, check the result */ 51 - if (pWb35Tx->EP4VM_status != 0) { 52 - dev_err(&pUrb->dev->dev, "URB submission failed\n"); 53 - pWb35Tx->EP4vm_state = VM_STOP; 54 - goto error; 55 - } 56 - 57 - Mds_Tx(adapter); 58 - Wb35Tx(adapter); 59 - return; 60 - 61 - error: 62 - atomic_dec(&pWb35Tx->TxFireCounter); 63 - pWb35Tx->EP4vm_state = VM_STOP; 64 - } 65 - 66 - static void Wb35Tx(struct wbsoft_priv *adapter) 67 - { 68 - struct hw_data *pHwData = &adapter->sHwData; 69 - struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; 70 - u8 *pTxBufferAddress; 71 - struct wb35_mds *pMds = &adapter->Mds; 72 - struct urb *pUrb = (struct urb *)pWb35Tx->Tx4Urb; 73 - int retv; 74 - u32 SendIndex; 75 - 76 - if (pHwData->SurpriseRemove) 77 - goto cleanup; 78 - 79 - if (pWb35Tx->tx_halt) 80 - goto cleanup; 81 - 82 - /* Ownership checking */ 83 - SendIndex = pWb35Tx->TxSendIndex; 84 - /* No more data need to be sent, return immediately */ 85 - if (!pMds->TxOwner[SendIndex]) 86 - goto cleanup; 87 - 88 - pTxBufferAddress = pWb35Tx->TxBuffer[SendIndex]; 89 - 90 - /* Issuing URB */ 91 - usb_fill_bulk_urb(pUrb, pHwData->udev, 92 - usb_sndbulkpipe(pHwData->udev, 4), 93 - pTxBufferAddress, pMds->TxBufferSize[SendIndex], 94 - Wb35Tx_complete, adapter); 95 - 96 - pWb35Tx->EP4vm_state = VM_RUNNING; 97 - retv = usb_submit_urb(pUrb, GFP_ATOMIC); 98 - if (retv < 0) { 99 - dev_err(&pUrb->dev->dev, "EP4 Tx Irp sending error\n"); 100 - goto cleanup; 101 - } 102 - 103 - /* Check if driver needs issue Irp for EP2 */ 104 - pWb35Tx->TxFillCount += pMds->TxCountInBuffer[SendIndex]; 105 - if (pWb35Tx->TxFillCount > 12) 106 - Wb35Tx_EP2VM_start(adapter); 107 - 108 - pWb35Tx->ByteTransfer += pMds->TxBufferSize[SendIndex]; 109 - return; 110 - 111 - cleanup: 112 - pWb35Tx->EP4vm_state = VM_STOP; 113 - atomic_dec(&pWb35Tx->TxFireCounter); 114 - } 115 - 116 - void Wb35Tx_start(struct wbsoft_priv *adapter) 117 - { 118 - struct hw_data *pHwData = &adapter->sHwData; 119 - struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; 120 - 121 - /* Allow only one thread to run into function */ 122 - if (atomic_inc_return(&pWb35Tx->TxFireCounter) == 1) { 123 - pWb35Tx->EP4vm_state = VM_RUNNING; 124 - Wb35Tx(adapter); 125 - } else 126 - atomic_dec(&pWb35Tx->TxFireCounter); 127 - } 128 - 129 - unsigned char Wb35Tx_initial(struct hw_data *pHwData) 130 - { 131 - struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; 132 - 133 - pWb35Tx->Tx4Urb = usb_alloc_urb(0, GFP_ATOMIC); 134 - if (!pWb35Tx->Tx4Urb) 135 - return false; 136 - 137 - pWb35Tx->Tx2Urb = usb_alloc_urb(0, GFP_ATOMIC); 138 - if (!pWb35Tx->Tx2Urb) { 139 - usb_free_urb(pWb35Tx->Tx4Urb); 140 - return false; 141 - } 142 - 143 - return true; 144 - } 145 - 146 - void Wb35Tx_stop(struct hw_data *pHwData) 147 - { 148 - struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; 149 - 150 - /* Try to cancel the Trp of EP2 */ 151 - if (pWb35Tx->EP2vm_state == VM_RUNNING) 152 - /* Only use unlink, let Wb35Tx_destroy free them */ 153 - usb_unlink_urb(pWb35Tx->Tx2Urb); 154 - pr_debug("EP2 Tx stop\n"); 155 - 156 - /* Try to cancel the Irp of EP4 */ 157 - if (pWb35Tx->EP4vm_state == VM_RUNNING) 158 - /* Only use unlink, let Wb35Tx_destroy free them */ 159 - usb_unlink_urb(pWb35Tx->Tx4Urb); 160 - pr_debug("EP4 Tx stop\n"); 161 - } 162 - 163 - void Wb35Tx_destroy(struct hw_data *pHwData) 164 - { 165 - struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; 166 - 167 - /* Wait for VM stop */ 168 - do { 169 - msleep(10); /* Delay for waiting function enter 940623.1.a */ 170 - } while ((pWb35Tx->EP2vm_state != VM_STOP) && (pWb35Tx->EP4vm_state != VM_STOP)); 171 - msleep(10); /* Delay for waiting function enter 940623.1.b */ 172 - 173 - usb_free_urb(pWb35Tx->Tx4Urb); 174 - usb_free_urb(pWb35Tx->Tx2Urb); 175 - 176 - pr_debug("Wb35Tx_destroy OK\n"); 177 - } 178 - 179 - void Wb35Tx_CurrentTime(struct wbsoft_priv *adapter, u32 TimeCount) 180 - { 181 - struct hw_data *pHwData = &adapter->sHwData; 182 - struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; 183 - bool Trigger = false; 184 - 185 - if (pWb35Tx->TxTimer > TimeCount) 186 - Trigger = true; 187 - else if (TimeCount > (pWb35Tx->TxTimer+500)) 188 - Trigger = true; 189 - 190 - if (Trigger) { 191 - pWb35Tx->TxTimer = TimeCount; 192 - Wb35Tx_EP2VM_start(adapter); 193 - } 194 - } 195 - 196 - static void Wb35Tx_EP2VM(struct wbsoft_priv *adapter); 197 - 198 - static void Wb35Tx_EP2VM_complete(struct urb *pUrb) 199 - { 200 - struct wbsoft_priv *adapter = pUrb->context; 201 - struct hw_data *pHwData = &adapter->sHwData; 202 - struct T02_descriptor T02, TSTATUS; 203 - struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; 204 - u32 *pltmp = (u32 *)pWb35Tx->EP2_buf; 205 - u32 i; 206 - u16 InterruptInLength; 207 - 208 - /* Variable setting */ 209 - pWb35Tx->EP2vm_state = VM_COMPLETED; 210 - pWb35Tx->EP2VM_status = pUrb->status; 211 - 212 - /* For Linux 2.4. Interrupt will always trigger */ 213 - if (pHwData->SurpriseRemove) /* Let WbWlanHalt handle surprise remove */ 214 - goto error; 215 - 216 - if (pWb35Tx->tx_halt) 217 - goto error; 218 - 219 - /* The Urb is completed, check the result */ 220 - if (pWb35Tx->EP2VM_status != 0) { 221 - dev_err(&pUrb->dev->dev, "EP2 IoCompleteRoutine return error\n"); 222 - pWb35Tx->EP2vm_state = VM_STOP; 223 - goto error; 224 - } 225 - 226 - /* Update the Tx result */ 227 - InterruptInLength = pUrb->actual_length; 228 - /* Modify for minimum memory access and DWORD alignment. */ 229 - T02.value = cpu_to_le32(pltmp[0]) >> 8; /* [31:8] -> [24:0] */ 230 - InterruptInLength -= 1; /* 20051221.1.c Modify the follow for more stable */ 231 - InterruptInLength >>= 2; /* InterruptInLength/4 */ 232 - for (i = 1; i <= InterruptInLength; i++) { 233 - T02.value |= ((cpu_to_le32(pltmp[i]) & 0xff) << 24); 234 - 235 - TSTATUS.value = T02.value; /* 20061009 anson's endian */ 236 - Mds_SendComplete(adapter, &TSTATUS); 237 - T02.value = cpu_to_le32(pltmp[i]) >> 8; 238 - } 239 - 240 - return; 241 - error: 242 - atomic_dec(&pWb35Tx->TxResultCount); 243 - pWb35Tx->EP2vm_state = VM_STOP; 244 - } 245 - 246 - static void Wb35Tx_EP2VM(struct wbsoft_priv *adapter) 247 - { 248 - struct hw_data *pHwData = &adapter->sHwData; 249 - struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; 250 - struct urb *pUrb = (struct urb *)pWb35Tx->Tx2Urb; 251 - u32 *pltmp = (u32 *)pWb35Tx->EP2_buf; 252 - int retv; 253 - 254 - if (pHwData->SurpriseRemove) 255 - goto error; 256 - 257 - if (pWb35Tx->tx_halt) 258 - goto error; 259 - 260 - /* Issuing URB */ 261 - usb_fill_int_urb(pUrb, pHwData->udev, usb_rcvintpipe(pHwData->udev, 2), 262 - pltmp, MAX_INTERRUPT_LENGTH, Wb35Tx_EP2VM_complete, 263 - adapter, 32); 264 - 265 - pWb35Tx->EP2vm_state = VM_RUNNING; 266 - retv = usb_submit_urb(pUrb, GFP_ATOMIC); 267 - 268 - if (retv < 0) { 269 - pr_debug("EP2 Tx Irp sending error\n"); 270 - goto error; 271 - } 272 - 273 - return; 274 - error: 275 - pWb35Tx->EP2vm_state = VM_STOP; 276 - atomic_dec(&pWb35Tx->TxResultCount); 277 - } 278 - 279 - void Wb35Tx_EP2VM_start(struct wbsoft_priv *adapter) 280 - { 281 - struct hw_data *pHwData = &adapter->sHwData; 282 - struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx; 283 - 284 - /* Allow only one thread to run into function */ 285 - if (atomic_inc_return(&pWb35Tx->TxResultCount) == 1) { 286 - pWb35Tx->EP2vm_state = VM_RUNNING; 287 - Wb35Tx_EP2VM(adapter); 288 - } else 289 - atomic_dec(&pWb35Tx->TxResultCount); 290 - }
-22
drivers/staging/winbond/wb35tx_f.h
··· 1 - #ifndef __WINBOND_WB35TX_F_H 2 - #define __WINBOND_WB35TX_F_H 3 - 4 - #include "core.h" 5 - 6 - /* 7 - * ==================================== 8 - * Interface function declare 9 - * ==================================== 10 - */ 11 - unsigned char Wb35Tx_initial(struct hw_data *hw_data); 12 - void Wb35Tx_destroy(struct hw_data *hw_data); 13 - unsigned char Wb35Tx_get_tx_buffer(struct hw_data *hw_data, u8 **buffer); 14 - 15 - void Wb35Tx_EP2VM_start(struct wbsoft_priv *adapter); 16 - 17 - void Wb35Tx_start(struct wbsoft_priv *adapter); 18 - void Wb35Tx_stop(struct hw_data *hw_data); 19 - 20 - void Wb35Tx_CurrentTime(struct wbsoft_priv *adapter, u32 time_count); 21 - 22 - #endif
-39
drivers/staging/winbond/wb35tx_s.h
··· 1 - #ifndef __WINBOND_WB35_TX_S_H 2 - #define __WINBOND_WB35_TX_S_H 3 - 4 - #include "mds_s.h" 5 - 6 - /* IS89C35 Tx related definition */ 7 - #define TX_INTERFACE 0 /* Interface 1 */ 8 - #define TX_PIPE 3 /* Endpoint 4 */ 9 - #define TX_INTERRUPT 1 /* Endpoint 2 */ 10 - #define MAX_INTERRUPT_LENGTH 64 /* It must be 64 for EP2 hardware */ 11 - 12 - /* Internal variable for module */ 13 - struct wb35_tx { 14 - /* For Tx buffer */ 15 - u8 TxBuffer[MAX_USB_TX_BUFFER_NUMBER][MAX_USB_TX_BUFFER]; 16 - 17 - /* For Interrupt pipe */ 18 - u8 EP2_buf[MAX_INTERRUPT_LENGTH]; 19 - 20 - atomic_t TxResultCount; /* For thread control of EP2 931130.4.m */ 21 - atomic_t TxFireCounter; /* For thread control of EP4 931130.4.n */ 22 - u32 ByteTransfer; 23 - 24 - u32 TxSendIndex; /* The next index of Mds array to be sent */ 25 - u32 EP2vm_state; /* for EP2vm state */ 26 - u32 EP4vm_state; /* for EP4vm state */ 27 - u32 tx_halt; /* Stopping VM */ 28 - 29 - struct urb *Tx4Urb; 30 - struct urb *Tx2Urb; 31 - 32 - int EP2VM_status; 33 - int EP4VM_status; 34 - 35 - u32 TxFillCount; /* 20060928 */ 36 - u32 TxTimer; /* 20060928 Add if sending packet is greater than 13 */ 37 - }; 38 - 39 - #endif
-513
drivers/staging/winbond/wbhal.h
··· 1 - #ifndef __WINBOND_WBHAL_S_H 2 - #define __WINBOND_WBHAL_S_H 3 - 4 - #include <linux/types.h> 5 - #include <linux/if_ether.h> /* for ETH_ALEN */ 6 - 7 - #define HAL_LED_SET_MASK 0x001c 8 - #define HAL_LED_SET_SHIFT 2 9 - 10 - /* supported RF type */ 11 - #define RF_MAXIM_2825 0 12 - #define RF_MAXIM_2827 1 13 - #define RF_MAXIM_2828 2 14 - #define RF_MAXIM_2829 3 15 - #define RF_MAXIM_V1 15 16 - #define RF_AIROHA_2230 16 17 - #define RF_AIROHA_7230 17 18 - #define RF_AIROHA_2230S 18 19 - #define RF_WB_242 33 20 - #define RF_WB_242_1 34 21 - #define RF_DECIDE_BY_INF 255 22 - 23 - /* 24 - * ---------------------------------------------------------------- 25 - * The follow define connect to upper layer 26 - * User must modify for connection between HAL and upper layer 27 - * ---------------------------------------------------------------- 28 - */ 29 - 30 - /* 31 - * ============================== 32 - * Common define 33 - * ============================== 34 - */ 35 - /* Bit 5 */ 36 - #define HAL_USB_MODE_BURST(_H) (_H->SoftwareSet & 0x20) 37 - 38 - /* Scan interval */ 39 - #define SCAN_MAX_CHNL_TIME (50) 40 - 41 - /* For TxL2 Frame typr recognise */ 42 - #define FRAME_TYPE_802_3_DATA 0 43 - #define FRAME_TYPE_802_11_MANAGEMENT 1 44 - #define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE 2 45 - #define FRAME_TYPE_802_11_CONTROL 3 46 - #define FRAME_TYPE_802_11_DATA 4 47 - #define FRAME_TYPE_PROMISCUOUS 5 48 - 49 - /* The follow definition is used for convert the frame------------ */ 50 - #define DOT_11_SEQUENCE_OFFSET 22 /* Sequence control offset */ 51 - #define DOT_3_TYPE_OFFSET 12 52 - #define DOT_11_MAC_HEADER_SIZE 24 53 - #define DOT_11_SNAP_SIZE 6 54 - #define DOT_11_TYPE_OFFSET 30 /* The start offset of 802.11 Frame. Type encapsulation. */ 55 - #define DEFAULT_SIFSTIME 10 56 - #define DEFAULT_FRAGMENT_THRESHOLD 2346 /* No fragment */ 57 - #define DEFAULT_MSDU_LIFE_TIME 0xffff 58 - 59 - #define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME (144 + 48) 60 - #define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME (72 + 24) 61 - #define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION (16 + 4 + 6) 62 - #define Tsym 4 63 - 64 - /* Frame Type of Bits (2, 3)----------------------------------- */ 65 - #define MAC_TYPE_MANAGEMENT 0x00 66 - #define MAC_TYPE_CONTROL 0x04 67 - #define MAC_TYPE_DATA 0x08 68 - #define MASK_FRAGMENT_NUMBER 0x000F 69 - #define SEQUENCE_NUMBER_SHIFT 4 70 - 71 - #define HAL_WOL_TYPE_WAKEUP_FRAME 0x01 72 - #define HAL_WOL_TYPE_MAGIC_PACKET 0x02 73 - 74 - #define HAL_KEYTYPE_WEP40 0 75 - #define HAL_KEYTYPE_WEP104 1 76 - #define HAL_KEYTYPE_TKIP 2 /* 128 bit key */ 77 - #define HAL_KEYTYPE_AES_CCMP 3 /* 128 bit key */ 78 - 79 - /* For VM state */ 80 - enum { 81 - VM_STOP = 0, 82 - VM_RUNNING, 83 - VM_COMPLETED 84 - }; 85 - 86 - /* 87 - * ================================ 88 - * Normal Key table format 89 - * ================================ 90 - */ 91 - 92 - /* The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX */ 93 - #define MAX_KEY_TABLE 24 /* 24 entry for storing key data */ 94 - #define GROUP_KEY_START_INDEX 4 95 - #define MAPPING_KEY_START_INDEX 8 96 - 97 - /* 98 - * ========================================= 99 - * Descriptor 100 - * ========================================= 101 - */ 102 - #define MAX_DESCRIPTOR_BUFFER_INDEX 8 /* Have to multiple of 2 */ 103 - #define FLAG_ERROR_TX_MASK 0x000000bf 104 - #define FLAG_ERROR_RX_MASK 0x0000083f 105 - 106 - #define FLAG_BAND_RX_MASK 0x10000000 /* Bit 28 */ 107 - 108 - struct R00_descriptor { 109 - union { 110 - u32 value; 111 - #ifdef _BIG_ENDIAN_ 112 - struct { 113 - u32 R00_packet_or_buffer_status:1; 114 - u32 R00_packet_in_fifo:1; 115 - u32 R00_RESERVED:2; 116 - u32 R00_receive_byte_count:12; 117 - u32 R00_receive_time_index:16; 118 - }; 119 - #else 120 - struct { 121 - u32 R00_receive_time_index:16; 122 - u32 R00_receive_byte_count:12; 123 - u32 R00_RESERVED:2; 124 - u32 R00_packet_in_fifo:1; 125 - u32 R00_packet_or_buffer_status:1; 126 - }; 127 - #endif 128 - }; 129 - }; 130 - 131 - struct T00_descriptor { 132 - union { 133 - u32 value; 134 - #ifdef _BIG_ENDIAN_ 135 - struct { 136 - u32 T00_first_mpdu:1; /* for hardware use */ 137 - u32 T00_last_mpdu:1; /* for hardware use */ 138 - u32 T00_IsLastMpdu:1;/* 0:not 1:Yes for software used */ 139 - u32 T00_IgnoreResult:1;/* The same mechanism with T00 setting. */ 140 - u32 T00_RESERVED_ID:2;/* 3 bit ID reserved */ 141 - u32 T00_tx_packet_id:4; 142 - u32 T00_RESERVED:4; 143 - u32 T00_header_length:6; 144 - u32 T00_frame_length:12; 145 - }; 146 - #else 147 - struct { 148 - u32 T00_frame_length:12; 149 - u32 T00_header_length:6; 150 - u32 T00_RESERVED:4; 151 - u32 T00_tx_packet_id:4; 152 - u32 T00_RESERVED_ID:2; /* 3 bit ID reserved */ 153 - u32 T00_IgnoreResult:1; /* The same mechanism with T00 setting. */ 154 - u32 T00_IsLastMpdu:1; /* 0:not 1:Yes for software used */ 155 - u32 T00_last_mpdu:1; /* for hardware use */ 156 - u32 T00_first_mpdu:1; /* for hardware use */ 157 - }; 158 - #endif 159 - }; 160 - }; 161 - 162 - struct R01_descriptor { 163 - union { 164 - u32 value; 165 - #ifdef _BIG_ENDIAN_ 166 - struct { 167 - u32 R01_RESERVED:3; 168 - u32 R01_mod_type:1; 169 - u32 R01_pre_type:1; 170 - u32 R01_data_rate:3; 171 - u32 R01_AGC_state:8; 172 - u32 R01_LNA_state:2; 173 - u32 R01_decryption_method:2; 174 - u32 R01_mic_error:1; 175 - u32 R01_replay:1; 176 - u32 R01_broadcast_frame:1; 177 - u32 R01_multicast_frame:1; 178 - u32 R01_directed_frame:1; 179 - u32 R01_receive_frame_antenna_selection:1; 180 - u32 R01_frame_receive_during_atim_window:1; 181 - u32 R01_protocol_version_error:1; 182 - u32 R01_authentication_frame_icv_error:1; 183 - u32 R01_null_key_to_authentication_frame:1; 184 - u32 R01_icv_error:1; 185 - u32 R01_crc_error:1; 186 - }; 187 - #else 188 - struct { 189 - u32 R01_crc_error:1; 190 - u32 R01_icv_error:1; 191 - u32 R01_null_key_to_authentication_frame:1; 192 - u32 R01_authentication_frame_icv_error:1; 193 - u32 R01_protocol_version_error:1; 194 - u32 R01_frame_receive_during_atim_window:1; 195 - u32 R01_receive_frame_antenna_selection:1; 196 - u32 R01_directed_frame:1; 197 - u32 R01_multicast_frame:1; 198 - u32 R01_broadcast_frame:1; 199 - u32 R01_replay:1; 200 - u32 R01_mic_error:1; 201 - u32 R01_decryption_method:2; 202 - u32 R01_LNA_state:2; 203 - u32 R01_AGC_state:8; 204 - u32 R01_data_rate:3; 205 - u32 R01_pre_type:1; 206 - u32 R01_mod_type:1; 207 - u32 R01_RESERVED:3; 208 - }; 209 - #endif 210 - }; 211 - }; 212 - 213 - struct T01_descriptor { 214 - union { 215 - u32 value; 216 - #ifdef _BIG_ENDIAN_ 217 - struct { 218 - u32 T01_rts_cts_duration:16; 219 - u32 T01_fall_back_rate:3; 220 - u32 T01_add_rts:1; 221 - u32 T01_add_cts:1; 222 - u32 T01_modulation_type:1; 223 - u32 T01_plcp_header_length:1; 224 - u32 T01_transmit_rate:3; 225 - u32 T01_wep_id:2; 226 - u32 T01_add_challenge_text:1; 227 - u32 T01_inhibit_crc:1; 228 - u32 T01_loop_back_wep_mode:1; 229 - u32 T01_retry_abort_enable:1; 230 - }; 231 - #else 232 - struct { 233 - u32 T01_retry_abort_enable:1; 234 - u32 T01_loop_back_wep_mode:1; 235 - u32 T01_inhibit_crc:1; 236 - u32 T01_add_challenge_text:1; 237 - u32 T01_wep_id:2; 238 - u32 T01_transmit_rate:3; 239 - u32 T01_plcp_header_length:1; 240 - u32 T01_modulation_type:1; 241 - u32 T01_add_cts:1; 242 - u32 T01_add_rts:1; 243 - u32 T01_fall_back_rate:3; 244 - u32 T01_rts_cts_duration:16; 245 - }; 246 - #endif 247 - }; 248 - }; 249 - 250 - struct T02_descriptor { 251 - union { 252 - u32 value; 253 - #ifdef _BIG_ENDIAN_ 254 - struct { 255 - u32 T02_IsLastMpdu:1; /* The same mechanism with T00 setting */ 256 - u32 T02_IgnoreResult:1; /* The same mechanism with T00 setting. */ 257 - u32 T02_RESERVED_ID:2; /* The same mechanism with T00 setting */ 258 - u32 T02_Tx_PktID:4; 259 - u32 T02_MPDU_Cnt:4; 260 - u32 T02_RTS_Cnt:4; 261 - u32 T02_RESERVED:7; 262 - u32 T02_transmit_complete:1; 263 - u32 T02_transmit_abort_due_to_TBTT:1; 264 - u32 T02_effective_transmission_rate:1; 265 - u32 T02_transmit_without_encryption_due_to_wep_on_false:1; 266 - u32 T02_discard_due_to_null_wep_key:1; 267 - u32 T02_RESERVED_1:1; 268 - u32 T02_out_of_MaxTxMSDULiftTime:1; 269 - u32 T02_transmit_abort:1; 270 - u32 T02_transmit_fail:1; 271 - }; 272 - #else 273 - struct { 274 - u32 T02_transmit_fail:1; 275 - u32 T02_transmit_abort:1; 276 - u32 T02_out_of_MaxTxMSDULiftTime:1; 277 - u32 T02_RESERVED_1:1; 278 - u32 T02_discard_due_to_null_wep_key:1; 279 - u32 T02_transmit_without_encryption_due_to_wep_on_false:1; 280 - u32 T02_effective_transmission_rate:1; 281 - u32 T02_transmit_abort_due_to_TBTT:1; 282 - u32 T02_transmit_complete:1; 283 - u32 T02_RESERVED:7; 284 - u32 T02_RTS_Cnt:4; 285 - u32 T02_MPDU_Cnt:4; 286 - u32 T02_Tx_PktID:4; 287 - u32 T02_RESERVED_ID:2; /* The same mechanism with T00 setting */ 288 - u32 T02_IgnoreResult:1; /* The same mechanism with T00 setting. */ 289 - u32 T02_IsLastMpdu:1; /* The same mechanism with T00 setting */ 290 - }; 291 - #endif 292 - }; 293 - }; 294 - 295 - struct wb35_descriptor { /* Skip length = 8 DWORD */ 296 - /* ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition */ 297 - u8 Descriptor_ID; 298 - /* ----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------ */ 299 - u8 RESERVED[3]; 300 - 301 - u16 FragmentThreshold; 302 - u8 InternalUsed; /* Only can be used by operation of descriptor definition */ 303 - u8 Type; /* 0: 802.3 1:802.11 data frame 2:802.11 management frame */ 304 - 305 - u8 PreambleMode;/* 0: short 1:long */ 306 - u8 TxRate; 307 - u8 FragmentCount; 308 - u8 EapFix; /* For speed up key install */ 309 - 310 - /* For R00 and T00 ------------------------------ */ 311 - union { 312 - struct R00_descriptor R00; 313 - struct T00_descriptor T00; 314 - }; 315 - 316 - /* For R01 and T01 ------------------------------ */ 317 - union { 318 - struct R01_descriptor R01; 319 - struct T01_descriptor T01; 320 - }; 321 - 322 - /* For R02 and T02 ------------------------------ */ 323 - union { 324 - u32 R02; 325 - struct T02_descriptor T02; 326 - }; 327 - 328 - /* For R03 and T03 ------------------------------ */ 329 - /* For software used */ 330 - union { 331 - u32 R03; 332 - u32 T03; 333 - struct { 334 - u8 buffer_number; 335 - u8 buffer_start_index; 336 - u16 buffer_total_size; 337 - }; 338 - }; 339 - 340 - /* For storing the buffer */ 341 - u16 buffer_size[MAX_DESCRIPTOR_BUFFER_INDEX]; 342 - void *buffer_address[MAX_DESCRIPTOR_BUFFER_INDEX]; 343 - }; 344 - 345 - #define MAX_TXVGA_EEPROM 9 /* How many word(u16) of EEPROM will be used for TxVGA */ 346 - #define MAX_RF_PARAMETER 32 347 - 348 - struct txvga_for_50 { 349 - u8 ChanNo; 350 - u8 TxVgaValue; 351 - }; 352 - 353 - /* 354 - * ============================================== 355 - * Device related include 356 - * ============================================== 357 - */ 358 - 359 - #include "wb35reg_s.h" 360 - #include "wb35tx_s.h" 361 - #include "wb35rx_s.h" 362 - 363 - /* For Hal using ============================================ */ 364 - struct hw_data { 365 - /* For compatible with 33 */ 366 - u32 revision; 367 - u32 BB3c_cal; /* The value for Tx calibration comes from EEPROM */ 368 - u32 BB54_cal; /* The value for Rx calibration comes from EEPROM */ 369 - 370 - /* For surprise remove */ 371 - u32 SurpriseRemove; /* 0: Normal 1: Surprise remove */ 372 - u8 IsKeyPreSet; 373 - u8 CalOneTime; 374 - 375 - u8 VCO_trim; 376 - 377 - u32 FragCount; 378 - u32 DMAFix; /* V1_DMA_FIX The variable can be removed if driver want to save mem space for V2. */ 379 - 380 - /* 381 - * =============================================== 382 - * Definition for MAC address 383 - * =============================================== 384 - */ 385 - u8 PermanentMacAddress[ETH_ALEN + 2]; /* The Ethernet addr that are stored in EEPROM. + 2 to 8-byte alignment */ 386 - u8 CurrentMacAddress[ETH_ALEN + 2]; /* The Enthernet addr that are in used. + 2 to 8-byte alignment */ 387 - 388 - /* 389 - * ========================================= 390 - * Definition for 802.11 391 - * ========================================= 392 - */ 393 - u8 *bssid_pointer; /* Used by hal_get_bssid for return value */ 394 - u8 bssid[8]; /* Only 6 byte will be used. 8 byte is required for read buffer */ 395 - u8 ssid[32]; /* maximum ssid length is 32 byte */ 396 - 397 - u16 AID; 398 - u8 ssid_length; 399 - u8 Channel; 400 - 401 - u16 ListenInterval; 402 - u16 CapabilityInformation; 403 - 404 - u16 BeaconPeriod; 405 - u16 ProbeDelay; 406 - 407 - u8 bss_type;/* 0: IBSS_NET or 1:ESS_NET */ 408 - u8 preamble;/* 0: short preamble, 1: long preamble */ 409 - u8 slot_time_select; /* 9 or 20 value */ 410 - u8 phy_type; /* Phy select */ 411 - 412 - u32 phy_para[MAX_RF_PARAMETER]; 413 - u32 phy_number; 414 - 415 - u32 CurrentRadioSw; /* 0:On 1:Off */ 416 - u32 CurrentRadioHw; /* 0:On 1:Off */ 417 - 418 - u8 *power_save_point; /* Used by hal_get_power_save_mode for return value */ 419 - u8 cwmin; 420 - u8 desired_power_save; 421 - u8 dtim; /* Is running dtim */ 422 - u8 mapping_key_replace_index; /* In Key table, the next index be replaced */ 423 - 424 - u16 MaxReceiveLifeTime; 425 - u16 FragmentThreshold; 426 - u16 FragmentThreshold_tmp; 427 - u16 cwmax; 428 - 429 - u8 Key_slot[MAX_KEY_TABLE][8]; /* Ownership record for key slot. For Alignment */ 430 - u32 Key_content[MAX_KEY_TABLE][12]; /* 10DW for each entry + 2 for burst command (Off and On valid bit) */ 431 - u8 CurrentDefaultKeyIndex; 432 - u32 CurrentDefaultKeyLength; 433 - 434 - /* 435 - * ================================================== 436 - * Variable for each module 437 - * ================================================== 438 - */ 439 - struct usb_device *udev; 440 - struct wb35_reg reg; /* Need Wb35Reg.h */ 441 - struct wb35_tx Wb35Tx; /* Need Wb35Tx.h */ 442 - struct wb35_rx Wb35Rx; /* Need Wb35Rx.h */ 443 - 444 - struct timer_list LEDTimer; /* For LED */ 445 - 446 - u32 LEDpoint; /* For LED */ 447 - 448 - u32 dto_tx_retry_count; 449 - u32 dto_tx_frag_count; 450 - u32 rx_ok_count[13]; /* index=0: total rx ok */ 451 - u32 rx_err_count[13]; /* index=0: total rx err */ 452 - 453 - /* for Tx debug */ 454 - u32 tx_TBTT_start_count; 455 - u32 tx_ETR_count; 456 - u32 tx_WepOn_false_count; 457 - u32 tx_Null_key_count; 458 - u32 tx_retry_count[8]; 459 - 460 - u8 PowerIndexFromEEPROM; /* For 2412MHz */ 461 - u8 power_index; 462 - u8 IsWaitJoinComplete; /* TRUE: set join request */ 463 - u8 band; 464 - 465 - u16 SoftwareSet; 466 - u16 Reserved_s; 467 - 468 - u32 IsInitOK; /* 0: Driver starting 1: Driver init OK */ 469 - 470 - /* For Phy calibration */ 471 - s32 iq_rsdl_gain_tx_d2; 472 - s32 iq_rsdl_phase_tx_d2; 473 - u32 txvga_setting_for_cal; 474 - 475 - u8 TxVgaSettingInEEPROM[(((MAX_TXVGA_EEPROM * 2) + 3) & ~0x03)]; /* For EEPROM value */ 476 - u8 TxVgaFor24[16]; /* Max is 14, 2 for alignment */ 477 - struct txvga_for_50 TxVgaFor50[36]; /* 35 channels in 5G. 35x2 = 70 byte. 2 for alignments */ 478 - 479 - u16 Scan_Interval; 480 - u16 RESERVED6; 481 - 482 - /* LED control */ 483 - u32 LED_control; 484 - /* 485 - * LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0] 486 - * Gray_Led 487 - * For Led gray setting 488 - * Led 489 - * 0: normal control, 490 - * LED behavior will decide by EEPROM setting 491 - * 1: Turn off specific LED 492 - * 2: Always on specific LED 493 - * 3: slow blinking specific LED 494 - * 4: fast blinking specific LED 495 - * 5: WPS led control is set. Led0 is Red, Led1 id Green 496 - * 497 - * Led[1] is parameter for WPS LED mode 498 - * 1:InProgress 499 - * 2: Error 500 - * 3: Session overlap 501 - * 4: Success control 502 - */ 503 - u32 LED_LinkOn; /* Turn LED on control */ 504 - u32 LED_Scanning; /* Let LED in scan process control */ 505 - u32 LED_Blinking; /* Temp variable for shining */ 506 - u32 RxByteCountLast; 507 - u32 TxByteCountLast; 508 - 509 - /* For global timer */ 510 - u32 time_count; /* TICK_TIME_100ms 1 = 100ms */ 511 - }; 512 - 513 - #endif
-853
drivers/staging/winbond/wbusb.c
··· 1 - /* 2 - * Copyright 2008 Pavel Machek <pavel@ucw.cz> 3 - * 4 - * Distribute under GPLv2. 5 - * 6 - * The original driver was written by: 7 - * Jeff Lee <YY_Lee@issc.com.tw> 8 - * 9 - * and was adapted to the 2.6 kernel by: 10 - * Costantino Leandro (Rxart Desktop) <le_costantino@pixartargentina.com.ar> 11 - */ 12 - #include <net/mac80211.h> 13 - #include <linux/usb.h> 14 - #include <linux/module.h> 15 - 16 - #include "core.h" 17 - #include "mds_f.h" 18 - #include "mto.h" 19 - #include "wbhal.h" 20 - #include "wb35reg_f.h" 21 - #include "wb35tx_f.h" 22 - #include "wb35rx_f.h" 23 - 24 - MODULE_DESCRIPTION("IS89C35 802.11bg WLAN USB Driver"); 25 - MODULE_LICENSE("GPL"); 26 - MODULE_VERSION("0.1"); 27 - 28 - static const struct usb_device_id wb35_table[] = { 29 - { USB_DEVICE(0x0416, 0x0035) }, 30 - { USB_DEVICE(0x18E8, 0x6201) }, 31 - { USB_DEVICE(0x18E8, 0x6206) }, 32 - { USB_DEVICE(0x18E8, 0x6217) }, 33 - { USB_DEVICE(0x18E8, 0x6230) }, 34 - { USB_DEVICE(0x18E8, 0x6233) }, 35 - { USB_DEVICE(0x1131, 0x2035) }, 36 - { 0, } 37 - }; 38 - 39 - MODULE_DEVICE_TABLE(usb, wb35_table); 40 - 41 - static struct ieee80211_rate wbsoft_rates[] = { 42 - { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 43 - }; 44 - 45 - static struct ieee80211_channel wbsoft_channels[] = { 46 - { .center_freq = 2412 }, 47 - }; 48 - 49 - static struct ieee80211_supported_band wbsoft_band_2GHz = { 50 - .channels = wbsoft_channels, 51 - .n_channels = ARRAY_SIZE(wbsoft_channels), 52 - .bitrates = wbsoft_rates, 53 - .n_bitrates = ARRAY_SIZE(wbsoft_rates), 54 - }; 55 - 56 - static void hal_set_beacon_period(struct hw_data *pHwData, u16 beacon_period) 57 - { 58 - u32 tmp; 59 - 60 - if (pHwData->SurpriseRemove) 61 - return; 62 - 63 - pHwData->BeaconPeriod = beacon_period; 64 - tmp = pHwData->BeaconPeriod << 16; 65 - tmp |= pHwData->ProbeDelay; 66 - Wb35Reg_Write(pHwData, 0x0848, tmp); 67 - } 68 - 69 - static int wbsoft_add_interface(struct ieee80211_hw *dev, 70 - struct ieee80211_vif *vif) 71 - { 72 - struct wbsoft_priv *priv = dev->priv; 73 - 74 - hal_set_beacon_period(&priv->sHwData, vif->bss_conf.beacon_int); 75 - 76 - return 0; 77 - } 78 - 79 - static void wbsoft_remove_interface(struct ieee80211_hw *dev, 80 - struct ieee80211_vif *vif) 81 - { 82 - } 83 - 84 - static void wbsoft_stop(struct ieee80211_hw *hw) 85 - { 86 - } 87 - 88 - static int wbsoft_get_stats(struct ieee80211_hw *hw, 89 - struct ieee80211_low_level_stats *stats) 90 - { 91 - return 0; 92 - } 93 - 94 - static u64 wbsoft_prepare_multicast(struct ieee80211_hw *hw, 95 - struct netdev_hw_addr_list *mc_list) 96 - { 97 - return netdev_hw_addr_list_count(mc_list); 98 - } 99 - 100 - static void wbsoft_configure_filter(struct ieee80211_hw *dev, 101 - unsigned int changed_flags, 102 - unsigned int *total_flags, 103 - u64 multicast) 104 - { 105 - unsigned int new_flags; 106 - 107 - new_flags = 0; 108 - 109 - if (*total_flags & FIF_PROMISC_IN_BSS) 110 - new_flags |= FIF_PROMISC_IN_BSS; 111 - else if ((*total_flags & FIF_ALLMULTI) || (multicast > 32)) 112 - new_flags |= FIF_ALLMULTI; 113 - 114 - dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS; 115 - 116 - *total_flags = new_flags; 117 - } 118 - 119 - static void wbsoft_tx(struct ieee80211_hw *dev, 120 - struct ieee80211_tx_control *control, 121 - struct sk_buff *skb) 122 - { 123 - struct wbsoft_priv *priv = dev->priv; 124 - 125 - if (priv->sMlmeFrame.is_in_used != PACKET_FREE_TO_USE) { 126 - priv->sMlmeFrame.wNumTxMMPDUDiscarded++; 127 - kfree_skb(skb); 128 - return; 129 - } 130 - 131 - priv->sMlmeFrame.is_in_used = PACKET_COME_FROM_MLME; 132 - 133 - priv->sMlmeFrame.pMMPDU = skb->data; 134 - priv->sMlmeFrame.data_type = FRAME_TYPE_802_11_MANAGEMENT; 135 - priv->sMlmeFrame.len = skb->len; 136 - priv->sMlmeFrame.wNumTxMMPDU++; 137 - 138 - /* 139 - * H/W will enter power save by set the register. S/W don't send null 140 - * frame with PWRMgt bit enbled to enter power save now. 141 - */ 142 - 143 - Mds_Tx(priv); 144 - } 145 - 146 - static int wbsoft_start(struct ieee80211_hw *dev) 147 - { 148 - struct wbsoft_priv *priv = dev->priv; 149 - 150 - priv->enabled = true; 151 - 152 - return 0; 153 - } 154 - 155 - static void hal_set_radio_mode(struct hw_data *pHwData, unsigned char radio_off) 156 - { 157 - struct wb35_reg *reg = &pHwData->reg; 158 - 159 - if (pHwData->SurpriseRemove) 160 - return; 161 - 162 - if (radio_off) { /* disable Baseband receive off */ 163 - pHwData->CurrentRadioSw = 1; /* off */ 164 - reg->M24_MacControl &= 0xffffffbf; 165 - } else { 166 - pHwData->CurrentRadioSw = 0; /* on */ 167 - reg->M24_MacControl |= 0x00000040; 168 - } 169 - Wb35Reg_Write(pHwData, 0x0824, reg->M24_MacControl); 170 - } 171 - 172 - static void hal_set_current_channel_ex(struct hw_data *pHwData, struct chan_info channel) 173 - { 174 - struct wb35_reg *reg = &pHwData->reg; 175 - 176 - if (pHwData->SurpriseRemove) 177 - return; 178 - 179 - RFSynthesizer_SwitchingChannel(pHwData, channel); /* Switch channel */ 180 - pHwData->Channel = channel.ChanNo; 181 - pHwData->band = channel.band; 182 - reg->M28_MacControl &= ~0xff; /* Clean channel information field */ 183 - reg->M28_MacControl |= channel.ChanNo; 184 - Wb35Reg_WriteWithCallbackValue(pHwData, 0x0828, reg->M28_MacControl, 185 - (s8 *) &channel, 186 - sizeof(struct chan_info)); 187 - } 188 - 189 - static void hal_set_current_channel(struct hw_data *pHwData, struct chan_info channel) 190 - { 191 - hal_set_current_channel_ex(pHwData, channel); 192 - } 193 - 194 - static void hal_set_accept_broadcast(struct hw_data *pHwData, u8 enable) 195 - { 196 - struct wb35_reg *reg = &pHwData->reg; 197 - 198 - if (pHwData->SurpriseRemove) 199 - return; 200 - 201 - reg->M00_MacControl &= ~0x02000000; /* The HW value */ 202 - 203 - if (enable) 204 - reg->M00_MacControl |= 0x02000000; /* The HW value */ 205 - 206 - Wb35Reg_Write(pHwData, 0x0800, reg->M00_MacControl); 207 - } 208 - 209 - /* For wep key error detection, we need to accept broadcast packets to be received temporary. */ 210 - static void hal_set_accept_promiscuous(struct hw_data *pHwData, u8 enable) 211 - { 212 - struct wb35_reg *reg = &pHwData->reg; 213 - 214 - if (pHwData->SurpriseRemove) 215 - return; 216 - 217 - if (enable) { 218 - reg->M00_MacControl |= 0x00400000; 219 - Wb35Reg_Write(pHwData, 0x0800, reg->M00_MacControl); 220 - } else { 221 - reg->M00_MacControl &= ~0x00400000; 222 - Wb35Reg_Write(pHwData, 0x0800, reg->M00_MacControl); 223 - } 224 - } 225 - 226 - static void hal_set_accept_multicast(struct hw_data *pHwData, u8 enable) 227 - { 228 - struct wb35_reg *reg = &pHwData->reg; 229 - 230 - if (pHwData->SurpriseRemove) 231 - return; 232 - 233 - reg->M00_MacControl &= ~0x01000000; /* The HW value */ 234 - if (enable) 235 - reg->M00_MacControl |= 0x01000000; /* The HW value */ 236 - Wb35Reg_Write(pHwData, 0x0800, reg->M00_MacControl); 237 - } 238 - 239 - static void hal_set_accept_beacon(struct hw_data *pHwData, u8 enable) 240 - { 241 - struct wb35_reg *reg = &pHwData->reg; 242 - 243 - if (pHwData->SurpriseRemove) 244 - return; 245 - 246 - if (!enable) /* Due to SME and MLME are not suitable for 35 */ 247 - return; 248 - 249 - reg->M00_MacControl &= ~0x04000000; /* The HW value */ 250 - if (enable) 251 - reg->M00_MacControl |= 0x04000000; /* The HW value */ 252 - 253 - Wb35Reg_Write(pHwData, 0x0800, reg->M00_MacControl); 254 - } 255 - 256 - static int wbsoft_config(struct ieee80211_hw *dev, u32 changed) 257 - { 258 - struct wbsoft_priv *priv = dev->priv; 259 - struct chan_info ch; 260 - 261 - /* Should use channel_num, or something, as that is already pre-translated */ 262 - ch.band = 1; 263 - ch.ChanNo = 1; 264 - 265 - hal_set_current_channel(&priv->sHwData, ch); 266 - hal_set_accept_broadcast(&priv->sHwData, 1); 267 - hal_set_accept_promiscuous(&priv->sHwData, 1); 268 - hal_set_accept_multicast(&priv->sHwData, 1); 269 - hal_set_accept_beacon(&priv->sHwData, 1); 270 - hal_set_radio_mode(&priv->sHwData, 0); 271 - 272 - return 0; 273 - } 274 - 275 - static u64 wbsoft_get_tsf(struct ieee80211_hw *dev, struct ieee80211_vif *vif) 276 - { 277 - return 0; 278 - } 279 - 280 - static const struct ieee80211_ops wbsoft_ops = { 281 - .tx = wbsoft_tx, 282 - .start = wbsoft_start, 283 - .stop = wbsoft_stop, 284 - .add_interface = wbsoft_add_interface, 285 - .remove_interface = wbsoft_remove_interface, 286 - .config = wbsoft_config, 287 - .prepare_multicast = wbsoft_prepare_multicast, 288 - .configure_filter = wbsoft_configure_filter, 289 - .get_stats = wbsoft_get_stats, 290 - .get_tsf = wbsoft_get_tsf, 291 - }; 292 - 293 - static void hal_set_ethernet_address(struct hw_data *pHwData, u8 *current_address) 294 - { 295 - u32 ltmp[2]; 296 - 297 - if (pHwData->SurpriseRemove) 298 - return; 299 - 300 - memcpy(pHwData->CurrentMacAddress, current_address, ETH_ALEN); 301 - 302 - ltmp[0] = cpu_to_le32(*(u32 *) pHwData->CurrentMacAddress); 303 - ltmp[1] = cpu_to_le32(*(u32 *) (pHwData->CurrentMacAddress + 4)) & 0xffff; 304 - 305 - Wb35Reg_BurstWrite(pHwData, 0x03e8, ltmp, 2, AUTO_INCREMENT); 306 - } 307 - 308 - static void hal_get_permanent_address(struct hw_data *pHwData, u8 *pethernet_address) 309 - { 310 - if (pHwData->SurpriseRemove) 311 - return; 312 - 313 - memcpy(pethernet_address, pHwData->PermanentMacAddress, 6); 314 - } 315 - 316 - static void hal_stop(struct hw_data *pHwData) 317 - { 318 - struct wb35_reg *reg = &pHwData->reg; 319 - 320 - pHwData->Wb35Rx.rx_halt = 1; 321 - Wb35Rx_stop(pHwData); 322 - 323 - pHwData->Wb35Tx.tx_halt = 1; 324 - Wb35Tx_stop(pHwData); 325 - 326 - reg->D00_DmaControl &= ~0xc0000000; /* Tx Off, Rx Off */ 327 - Wb35Reg_Write(pHwData, 0x0400, reg->D00_DmaControl); 328 - } 329 - 330 - static unsigned char hal_idle(struct hw_data *pHwData) 331 - { 332 - struct wb35_reg *reg = &pHwData->reg; 333 - 334 - if (!pHwData->SurpriseRemove && reg->EP0vm_state != VM_STOP) 335 - return false; 336 - 337 - return true; 338 - } 339 - 340 - u8 hal_get_antenna_number(struct hw_data *pHwData) 341 - { 342 - struct wb35_reg *reg = &pHwData->reg; 343 - 344 - if ((reg->BB2C & BIT(11)) == 0) 345 - return 0; 346 - else 347 - return 1; 348 - } 349 - 350 - /* 0 : radio on; 1: radio off */ 351 - static u8 hal_get_hw_radio_off(struct hw_data *pHwData) 352 - { 353 - struct wb35_reg *reg = &pHwData->reg; 354 - 355 - if (pHwData->SurpriseRemove) 356 - return 1; 357 - 358 - /* read the bit16 of register U1B0 */ 359 - Wb35Reg_Read(pHwData, 0x3b0, &reg->U1B0); 360 - if ((reg->U1B0 & 0x00010000)) { 361 - pHwData->CurrentRadioHw = 1; 362 - return 1; 363 - } else { 364 - pHwData->CurrentRadioHw = 0; 365 - return 0; 366 - } 367 - } 368 - 369 - static u8 LED_GRAY[20] = { 370 - 0, 3, 4, 6, 8, 10, 11, 12, 13, 14, 15, 14, 13, 12, 11, 10, 8, 6, 4, 2 371 - }; 372 - 373 - static u8 LED_GRAY2[30] = { 374 - 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 375 - 0, 15, 14, 13, 12, 11, 10, 9, 8 376 - }; 377 - 378 - static void hal_led_control(unsigned long data) 379 - { 380 - struct wbsoft_priv *adapter = (struct wbsoft_priv *)data; 381 - struct hw_data *pHwData = &adapter->sHwData; 382 - struct wb35_reg *reg = &pHwData->reg; 383 - u32 LEDSet = (pHwData->SoftwareSet & HAL_LED_SET_MASK) >> HAL_LED_SET_SHIFT; 384 - u32 TimeInterval = 500, ltmp, ltmp2; 385 - ltmp = 0; 386 - 387 - if (pHwData->SurpriseRemove) 388 - return; 389 - 390 - if (pHwData->LED_control) { 391 - ltmp2 = pHwData->LED_control & 0xff; 392 - if (ltmp2 == 5) { /* 5 is WPS mode */ 393 - TimeInterval = 100; 394 - ltmp2 = (pHwData->LED_control >> 8) & 0xff; 395 - switch (ltmp2) { 396 - case 1: /* [0.2 On][0.1 Off]... */ 397 - pHwData->LED_Blinking %= 3; 398 - ltmp = 0x1010; /* Led 1 & 0 Green and Red */ 399 - if (pHwData->LED_Blinking == 2) /* Turn off */ 400 - ltmp = 0; 401 - break; 402 - case 2: /* [0.1 On][0.1 Off]... */ 403 - pHwData->LED_Blinking %= 2; 404 - ltmp = 0x0010; /* Led 0 red color */ 405 - if (pHwData->LED_Blinking) /* Turn off */ 406 - ltmp = 0; 407 - break; 408 - case 3: /* [0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.5 Off]... */ 409 - pHwData->LED_Blinking %= 15; 410 - ltmp = 0x0010; /* Led 0 red color */ 411 - if ((pHwData->LED_Blinking >= 9) || (pHwData->LED_Blinking % 2)) /* Turn off 0.6 sec */ 412 - ltmp = 0; 413 - break; 414 - case 4: /* [300 On][ off ] */ 415 - ltmp = 0x1000; /* Led 1 Green color */ 416 - if (pHwData->LED_Blinking >= 3000) 417 - ltmp = 0; /* led maybe on after 300sec * 32bit counter overlap. */ 418 - break; 419 - } 420 - pHwData->LED_Blinking++; 421 - 422 - reg->U1BC_LEDConfigure = ltmp; 423 - if (LEDSet != 7) { /* Only 111 mode has 2 LEDs on PCB. */ 424 - reg->U1BC_LEDConfigure |= (ltmp & 0xff) << 8; /* Copy LED result to each LED control register */ 425 - reg->U1BC_LEDConfigure |= (ltmp & 0xff00) >> 8; 426 - } 427 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); 428 - } 429 - } else if (pHwData->CurrentRadioSw || pHwData->CurrentRadioHw) { /* If radio off */ 430 - if (reg->U1BC_LEDConfigure & 0x1010) { 431 - reg->U1BC_LEDConfigure &= ~0x1010; 432 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); 433 - } 434 - } else { 435 - switch (LEDSet) { 436 - case 4: /* [100] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing */ 437 - if (!pHwData->LED_LinkOn) { /* Blink only if not Link On */ 438 - /* Blinking if scanning is on progress */ 439 - if (pHwData->LED_Scanning) { 440 - if (pHwData->LED_Blinking == 0) { 441 - reg->U1BC_LEDConfigure |= 0x10; 442 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 On */ 443 - pHwData->LED_Blinking = 1; 444 - TimeInterval = 300; 445 - } else { 446 - reg->U1BC_LEDConfigure &= ~0x10; 447 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 Off */ 448 - pHwData->LED_Blinking = 0; 449 - TimeInterval = 300; 450 - } 451 - } else { 452 - /* Turn Off LED_0 */ 453 - if (reg->U1BC_LEDConfigure & 0x10) { 454 - reg->U1BC_LEDConfigure &= ~0x10; 455 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 Off */ 456 - } 457 - } 458 - } else { 459 - /* Turn On LED_0 */ 460 - if ((reg->U1BC_LEDConfigure & 0x10) == 0) { 461 - reg->U1BC_LEDConfigure |= 0x10; 462 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 Off */ 463 - } 464 - } 465 - break; 466 - case 6: /* [110] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing */ 467 - if (!pHwData->LED_LinkOn) { /* Blink only if not Link On */ 468 - /* Blinking if scanning is on progress */ 469 - if (pHwData->LED_Scanning) { 470 - if (pHwData->LED_Blinking == 0) { 471 - reg->U1BC_LEDConfigure &= ~0xf; 472 - reg->U1BC_LEDConfigure |= 0x10; 473 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 On */ 474 - pHwData->LED_Blinking = 1; 475 - TimeInterval = 300; 476 - } else { 477 - reg->U1BC_LEDConfigure &= ~0x1f; 478 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 Off */ 479 - pHwData->LED_Blinking = 0; 480 - TimeInterval = 300; 481 - } 482 - } else { 483 - /* Gray blinking if in disconnect state and not scanning */ 484 - ltmp = reg->U1BC_LEDConfigure; 485 - reg->U1BC_LEDConfigure &= ~0x1f; 486 - if (LED_GRAY2[(pHwData->LED_Blinking % 30)]) { 487 - reg->U1BC_LEDConfigure |= 0x10; 488 - reg->U1BC_LEDConfigure |= 489 - LED_GRAY2[(pHwData->LED_Blinking % 30)]; 490 - } 491 - pHwData->LED_Blinking++; 492 - if (reg->U1BC_LEDConfigure != ltmp) 493 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 Off */ 494 - TimeInterval = 100; 495 - } 496 - } else { 497 - /* Turn On LED_0 */ 498 - if ((reg->U1BC_LEDConfigure & 0x10) == 0) { 499 - reg->U1BC_LEDConfigure |= 0x10; 500 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 Off */ 501 - } 502 - } 503 - break; 504 - case 5: /* [101] Only 1 Led be placed on PCB and use LED_1 for showing */ 505 - if (!pHwData->LED_LinkOn) { /* Blink only if not Link On */ 506 - /* Blinking if scanning is on progress */ 507 - if (pHwData->LED_Scanning) { 508 - if (pHwData->LED_Blinking == 0) { 509 - reg->U1BC_LEDConfigure |= 0x1000; 510 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_1 On */ 511 - pHwData->LED_Blinking = 1; 512 - TimeInterval = 300; 513 - } else { 514 - reg->U1BC_LEDConfigure &= ~0x1000; 515 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_1 Off */ 516 - pHwData->LED_Blinking = 0; 517 - TimeInterval = 300; 518 - } 519 - } else { 520 - /* Turn Off LED_1 */ 521 - if (reg->U1BC_LEDConfigure & 0x1000) { 522 - reg->U1BC_LEDConfigure &= ~0x1000; 523 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_1 Off */ 524 - } 525 - } 526 - } else { 527 - /* Is transmitting/receiving ?? */ 528 - if ((adapter->RxByteCount != 529 - pHwData->RxByteCountLast) 530 - || (adapter->TxByteCount != 531 - pHwData->TxByteCountLast)) { 532 - if ((reg->U1BC_LEDConfigure & 0x3000) != 533 - 0x3000) { 534 - reg->U1BC_LEDConfigure |= 0x3000; 535 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_1 On */ 536 - } 537 - /* Update variable */ 538 - pHwData->RxByteCountLast = 539 - adapter->RxByteCount; 540 - pHwData->TxByteCountLast = 541 - adapter->TxByteCount; 542 - TimeInterval = 200; 543 - } else { 544 - /* Turn On LED_1 and blinking if transmitting/receiving */ 545 - if ((reg->U1BC_LEDConfigure & 0x3000) != 546 - 0x1000) { 547 - reg->U1BC_LEDConfigure &= 548 - ~0x3000; 549 - reg->U1BC_LEDConfigure |= 550 - 0x1000; 551 - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_1 On */ 552 - } 553 - } 554 - } 555 - break; 556 - default: /* Default setting. 2 LED be placed on PCB. LED_0: Link On LED_1 Active */ 557 - if ((reg->U1BC_LEDConfigure & 0x3000) != 0x3000) { 558 - reg->U1BC_LEDConfigure |= 0x3000; /* LED_1 is always on and event enable */ 559 - Wb35Reg_Write(pHwData, 0x03bc, 560 - reg->U1BC_LEDConfigure); 561 - } 562 - 563 - if (pHwData->LED_Blinking) { 564 - /* Gray blinking */ 565 - reg->U1BC_LEDConfigure &= ~0x0f; 566 - reg->U1BC_LEDConfigure |= 0x10; 567 - reg->U1BC_LEDConfigure |= 568 - LED_GRAY[(pHwData->LED_Blinking - 1) % 20]; 569 - Wb35Reg_Write(pHwData, 0x03bc, 570 - reg->U1BC_LEDConfigure); 571 - 572 - pHwData->LED_Blinking += 2; 573 - if (pHwData->LED_Blinking < 40) 574 - TimeInterval = 100; 575 - else { 576 - pHwData->LED_Blinking = 0; /* Stop blinking */ 577 - reg->U1BC_LEDConfigure &= ~0x0f; 578 - Wb35Reg_Write(pHwData, 0x03bc, 579 - reg->U1BC_LEDConfigure); 580 - } 581 - break; 582 - } 583 - 584 - if (pHwData->LED_LinkOn) { 585 - if (!(reg->U1BC_LEDConfigure & 0x10)) { /* Check the LED_0 */ 586 - /* Try to turn ON LED_0 after gray blinking */ 587 - reg->U1BC_LEDConfigure |= 0x10; 588 - pHwData->LED_Blinking = 1; /* Start blinking */ 589 - TimeInterval = 50; 590 - } 591 - } else { 592 - if (reg->U1BC_LEDConfigure & 0x10) { /* Check the LED_0 */ 593 - reg->U1BC_LEDConfigure &= ~0x10; 594 - Wb35Reg_Write(pHwData, 0x03bc, 595 - reg->U1BC_LEDConfigure); 596 - } 597 - } 598 - break; 599 - } 600 - } 601 - 602 - pHwData->time_count += TimeInterval; 603 - Wb35Tx_CurrentTime(adapter, pHwData->time_count); 604 - pHwData->LEDTimer.expires = jiffies + msecs_to_jiffies(TimeInterval); 605 - add_timer(&pHwData->LEDTimer); 606 - } 607 - 608 - static int hal_init_hardware(struct ieee80211_hw *hw) 609 - { 610 - struct wbsoft_priv *priv = hw->priv; 611 - struct hw_data *pHwData = &priv->sHwData; 612 - u16 SoftwareSet; 613 - 614 - pHwData->MaxReceiveLifeTime = DEFAULT_MSDU_LIFE_TIME; 615 - pHwData->FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; 616 - 617 - if (!Wb35Reg_initial(pHwData)) 618 - goto error_reg_destroy; 619 - 620 - if (!Wb35Tx_initial(pHwData)) 621 - goto error_tx_destroy; 622 - 623 - if (!Wb35Rx_initial(pHwData)) 624 - goto error_rx_destroy; 625 - 626 - init_timer(&pHwData->LEDTimer); 627 - pHwData->LEDTimer.function = hal_led_control; 628 - pHwData->LEDTimer.data = (unsigned long)priv; 629 - pHwData->LEDTimer.expires = jiffies + msecs_to_jiffies(1000); 630 - add_timer(&pHwData->LEDTimer); 631 - 632 - SoftwareSet = hal_software_set(pHwData); 633 - 634 - Wb35Rx_start(hw); 635 - Wb35Tx_EP2VM_start(priv); 636 - 637 - return 0; 638 - 639 - error_rx_destroy: 640 - Wb35Rx_destroy(pHwData); 641 - error_tx_destroy: 642 - Wb35Tx_destroy(pHwData); 643 - error_reg_destroy: 644 - Wb35Reg_destroy(pHwData); 645 - 646 - pHwData->SurpriseRemove = 1; 647 - return -EINVAL; 648 - } 649 - 650 - static int wb35_hw_init(struct ieee80211_hw *hw) 651 - { 652 - struct wbsoft_priv *priv = hw->priv; 653 - struct hw_data *pHwData = &priv->sHwData; 654 - u8 EEPROM_region; 655 - u8 HwRadioOff; 656 - u8 *pMacAddr2; 657 - u8 *pMacAddr; 658 - int err; 659 - 660 - pHwData->phy_type = RF_DECIDE_BY_INF; 661 - 662 - priv->Mds.TxRTSThreshold = DEFAULT_RTSThreshold; 663 - priv->Mds.TxFragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; 664 - 665 - priv->sLocalPara.region_INF = REGION_AUTO; 666 - priv->sLocalPara.TxRateMode = RATE_AUTO; 667 - priv->sLocalPara.bMacOperationMode = MODE_802_11_BG; 668 - priv->sLocalPara.MTUsize = MAX_ETHERNET_PACKET_SIZE; 669 - priv->sLocalPara.bPreambleMode = AUTO_MODE; 670 - priv->sLocalPara.bWepKeyError = false; 671 - priv->sLocalPara.bToSelfPacketReceived = false; 672 - priv->sLocalPara.WepKeyDetectTimerCount = 2 * 100; /* 2 seconds */ 673 - 674 - priv->sLocalPara.RadioOffStatus.boSwRadioOff = false; 675 - 676 - err = hal_init_hardware(hw); 677 - if (err) 678 - goto error; 679 - 680 - EEPROM_region = hal_get_region_from_EEPROM(pHwData); 681 - if (EEPROM_region != REGION_AUTO) 682 - priv->sLocalPara.region = EEPROM_region; 683 - else { 684 - if (priv->sLocalPara.region_INF != REGION_AUTO) 685 - priv->sLocalPara.region = priv->sLocalPara.region_INF; 686 - else 687 - priv->sLocalPara.region = REGION_USA; /* default setting */ 688 - } 689 - 690 - Mds_initial(priv); 691 - 692 - /* 693 - * If no user-defined address in the registry, use the address 694 - * "burned" on the NIC instead. 695 - */ 696 - pMacAddr = priv->sLocalPara.ThisMacAddress; 697 - pMacAddr2 = priv->sLocalPara.PermanentAddress; 698 - 699 - /* Reading ethernet address from EEPROM */ 700 - hal_get_permanent_address(pHwData, priv->sLocalPara.PermanentAddress); 701 - if (memcmp(pMacAddr, "\x00\x00\x00\x00\x00\x00", MAC_ADDR_LENGTH) == 0) 702 - memcpy(pMacAddr, pMacAddr2, MAC_ADDR_LENGTH); 703 - else { 704 - /* Set the user define MAC address */ 705 - hal_set_ethernet_address(pHwData, 706 - priv->sLocalPara.ThisMacAddress); 707 - } 708 - 709 - priv->sLocalPara.bAntennaNo = hal_get_antenna_number(pHwData); 710 - hal_get_hw_radio_off(pHwData); 711 - 712 - /* Waiting for HAL setting OK */ 713 - while (!hal_idle(pHwData)) 714 - msleep(10); 715 - 716 - MTO_Init(priv); 717 - 718 - HwRadioOff = hal_get_hw_radio_off(pHwData); 719 - priv->sLocalPara.RadioOffStatus.boHwRadioOff = !!HwRadioOff; 720 - 721 - hal_set_radio_mode(pHwData, 722 - (unsigned char)(priv->sLocalPara.RadioOffStatus. 723 - boSwRadioOff 724 - || priv->sLocalPara.RadioOffStatus. 725 - boHwRadioOff)); 726 - 727 - /* Notify hal that the driver is ready now. */ 728 - hal_driver_init_OK(pHwData) = 1; 729 - 730 - error: 731 - return err; 732 - } 733 - 734 - static int wb35_probe(struct usb_interface *intf, 735 - const struct usb_device_id *id_table) 736 - { 737 - struct usb_device *udev = interface_to_usbdev(intf); 738 - struct usb_endpoint_descriptor *endpoint; 739 - struct usb_host_interface *interface; 740 - struct ieee80211_hw *dev; 741 - struct wbsoft_priv *priv; 742 - int err; 743 - u32 ltmp; 744 - 745 - usb_get_dev(udev); 746 - 747 - /* Check the device if it already be opened */ 748 - err = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 749 - 0x01, 750 - USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN, 751 - 0x0, 0x400, &ltmp, 4, HZ * 100); 752 - if (err < 0) 753 - goto error; 754 - 755 - /* Is already initialized? */ 756 - ltmp = cpu_to_le32(ltmp); 757 - if (ltmp) { 758 - err = -EBUSY; 759 - goto error; 760 - } 761 - 762 - dev = ieee80211_alloc_hw(sizeof(*priv), &wbsoft_ops); 763 - if (!dev) { 764 - err = -ENOMEM; 765 - goto error; 766 - } 767 - 768 - priv = dev->priv; 769 - 770 - priv->sHwData.udev = udev; 771 - 772 - interface = intf->cur_altsetting; 773 - endpoint = &interface->endpoint[0].desc; 774 - 775 - err = wb35_hw_init(dev); 776 - if (err) 777 - goto error_free_hw; 778 - 779 - SET_IEEE80211_DEV(dev, &udev->dev); 780 - { 781 - struct hw_data *pHwData = &priv->sHwData; 782 - unsigned char dev_addr[MAX_ADDR_LEN]; 783 - hal_get_permanent_address(pHwData, dev_addr); 784 - SET_IEEE80211_PERM_ADDR(dev, dev_addr); 785 - } 786 - 787 - dev->extra_tx_headroom = 12; /* FIXME */ 788 - dev->flags = IEEE80211_HW_SIGNAL_UNSPEC; 789 - dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 790 - 791 - dev->max_signal = 100; 792 - dev->queues = 1; 793 - 794 - dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &wbsoft_band_2GHz; 795 - 796 - err = ieee80211_register_hw(dev); 797 - if (err) 798 - goto error_free_hw; 799 - 800 - usb_set_intfdata(intf, dev); 801 - 802 - return 0; 803 - 804 - error_free_hw: 805 - ieee80211_free_hw(dev); 806 - error: 807 - usb_put_dev(udev); 808 - return err; 809 - } 810 - 811 - static void hal_halt(struct hw_data *pHwData) 812 - { 813 - del_timer_sync(&pHwData->LEDTimer); 814 - /* XXX: Wait for Timer DPC exit. */ 815 - msleep(100); 816 - Wb35Rx_destroy(pHwData); 817 - Wb35Tx_destroy(pHwData); 818 - Wb35Reg_destroy(pHwData); 819 - } 820 - 821 - static void wb35_hw_halt(struct wbsoft_priv *adapter) 822 - { 823 - /* Turn off Rx and Tx hardware ability */ 824 - hal_stop(&adapter->sHwData); 825 - /* Waiting Irp completed */ 826 - msleep(100); 827 - 828 - hal_halt(&adapter->sHwData); 829 - } 830 - 831 - static void wb35_disconnect(struct usb_interface *intf) 832 - { 833 - struct ieee80211_hw *hw = usb_get_intfdata(intf); 834 - struct wbsoft_priv *priv = hw->priv; 835 - 836 - wb35_hw_halt(priv); 837 - 838 - ieee80211_stop_queues(hw); 839 - ieee80211_unregister_hw(hw); 840 - ieee80211_free_hw(hw); 841 - 842 - usb_set_intfdata(intf, NULL); 843 - usb_put_dev(interface_to_usbdev(intf)); 844 - } 845 - 846 - static struct usb_driver wb35_driver = { 847 - .name = "w35und", 848 - .id_table = wb35_table, 849 - .probe = wb35_probe, 850 - .disconnect = wb35_disconnect, 851 - }; 852 - 853 - module_usb_driver(wb35_driver);