tjh.dev / kernel
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Catalin Marinas:
"A couple of build/config issues and expanding the speculative SSBS
workaround to more CPUs:

- Expand the speculative SSBS workaround to cover Cortex-A715,
Neoverse-N3 and Microsoft Azure Cobalt 100

- Force position-independent veneers - in some kernel configurations,
the LLD linker generates position-dependent veneers for otherwise
position-independent code, resulting in early boot-time failures

- Fix Kconfig selection of HAVE_DYNAMIC_FTRACE_WITH_ARGS so that it
is not enabled when not supported by the combination of clang and
GNU ld"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: Subscribe Microsoft Azure Cobalt 100 to erratum 3194386
arm64: fix selection of HAVE_DYNAMIC_FTRACE_WITH_ARGS
arm64: errata: Expand speculative SSBS workaround once more
arm64: cputype: Add Neoverse-N3 definitions
arm64: Force position-independent veneers

Linus Torvalds ac308609 7943f06c

+16 -4
+6
Documentation/arch/arm64/silicon-errata.rst
··· 146 146 +----------------+-----------------+-----------------+-----------------------------+ 147 147 | ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 | 148 148 +----------------+-----------------+-----------------+-----------------------------+ 149 + | ARM | Cortex-A715 | #3456084 | ARM64_ERRATUM_3194386 | 150 + +----------------+-----------------+-----------------+-----------------------------+ 149 151 | ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 | 150 152 +----------------+-----------------+-----------------+-----------------------------+ 151 153 | ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | ··· 187 185 | ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 | 188 186 +----------------+-----------------+-----------------+-----------------------------+ 189 187 | ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 | 188 + +----------------+-----------------+-----------------+-----------------------------+ 189 + | ARM | Neoverse-N3 | #3456111 | ARM64_ERRATUM_3194386 | 190 190 +----------------+-----------------+-----------------+-----------------------------+ 191 191 | ARM | Neoverse-V1 | #1619801 | N/A | 192 192 +----------------+-----------------+-----------------+-----------------------------+ ··· 292 288 | Microsoft | Azure Cobalt 100| #2067961 | ARM64_ERRATUM_2067961 | 293 289 +----------------+-----------------+-----------------+-----------------------------+ 294 290 | Microsoft | Azure Cobalt 100| #2253138 | ARM64_ERRATUM_2253138 | 291 + +----------------+-----------------+-----------------+-----------------------------+ 292 + | Microsoft | Azure Cobalt 100| #3324339 | ARM64_ERRATUM_3194386 | 295 293 +----------------+-----------------+-----------------+-----------------------------+
+4 -3
arch/arm64/Kconfig
··· 200 200 select HAVE_DMA_CONTIGUOUS 201 201 select HAVE_DYNAMIC_FTRACE 202 202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 203 - if $(cc-option,-fpatchable-function-entry=2) 203 + if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 204 + CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 204 205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 205 206 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 206 207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ ··· 287 286 def_bool CC_IS_CLANG 288 287 # https://github.com/ClangBuiltLinux/linux/issues/1507 289 288 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 290 - select HAVE_DYNAMIC_FTRACE_WITH_ARGS 291 289 292 290 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 293 291 def_bool CC_IS_GCC 294 292 depends on $(cc-option,-fpatchable-function-entry=2) 295 - select HAVE_DYNAMIC_FTRACE_WITH_ARGS 296 293 297 294 config 64BIT 298 295 def_bool y ··· 1096 1097 * ARM Cortex-A78C erratum 3324346 1097 1098 * ARM Cortex-A78C erratum 3324347 1098 1099 * ARM Cortex-A710 erratam 3324338 1100 + * ARM Cortex-A715 errartum 3456084 1099 1101 * ARM Cortex-A720 erratum 3456091 1100 1102 * ARM Cortex-A725 erratum 3456106 1101 1103 * ARM Cortex-X1 erratum 3324344 ··· 1107 1107 * ARM Cortex-X925 erratum 3324334 1108 1108 * ARM Neoverse-N1 erratum 3324349 1109 1109 * ARM Neoverse N2 erratum 3324339 1110 + * ARM Neoverse-N3 erratum 3456111 1110 1111 * ARM Neoverse-V1 erratum 3324341 1111 1112 * ARM Neoverse V2 erratum 3324336 1112 1113 * ARM Neoverse-V3 erratum 3312417
+1 -1
arch/arm64/Makefile
··· 10 10 # 11 11 # Copyright (C) 1995-2001 by Russell King 12 12 13 - LDFLAGS_vmlinux :=--no-undefined -X 13 + LDFLAGS_vmlinux :=--no-undefined -X --pic-veneer 14 14 15 15 ifeq ($(CONFIG_RELOCATABLE), y) 16 16 # Pass --no-apply-dynamic-relocs to restore pre-binutils-2.27 behaviour
+2
arch/arm64/include/asm/cputype.h
··· 94 94 #define ARM_CPU_PART_NEOVERSE_V3 0xD84 95 95 #define ARM_CPU_PART_CORTEX_X925 0xD85 96 96 #define ARM_CPU_PART_CORTEX_A725 0xD87 97 + #define ARM_CPU_PART_NEOVERSE_N3 0xD8E 97 98 98 99 #define APM_CPU_PART_XGENE 0x000 99 100 #define APM_CPU_VAR_POTENZA 0x00 ··· 177 176 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) 178 177 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) 179 178 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) 179 + #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3) 180 180 #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) 181 181 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) 182 182 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
+3
arch/arm64/kernel/cpu_errata.c
··· 439 439 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), 440 440 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), 441 441 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 442 + MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), 442 443 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), 443 444 MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), 444 445 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), ··· 448 447 MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), 449 448 MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), 450 449 MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), 450 + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 451 451 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), 452 452 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 453 + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), 453 454 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), 454 455 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), 455 456 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),