tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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Merge tag 'mips_6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:
"Just cleanups and fixes"

* tag 'mips_6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
MIPS: TXx9: Do PCI error checks on own line
arch/mips/configs/*_defconfig cleanup
MIPS: VDSO: Conditionally export __vdso_gettimeofday()
Mips: loongson3_defconfig: Enable ast drm driver by default
mips: remove <asm/export.h>
mips: replace #include <asm/export.h> with #include <linux/export.h>
mips: remove unneeded #include <asm/export.h>
MIPS: Loongson64: Fix more __iomem attributes
MIPS: loongson32: Remove regs-rtc.h
MIPS: loongson32: Remove regs-clk.h
MIPS: More explicit DT include clean-ups
MIPS: Fixup explicit DT include clean-up
Revert MIPS: Loongson: Fix build error when make modules_install
MIPS: Only fiddle with CHECKFLAGS if `need-compiler'
MIPS: Fix CONFIG_CPU_DADDI_WORKAROUNDS `modules_install' regression
MIPS: Explicitly include correct DT includes

Linus Torvalds ac2224a4 dd1386dd

+149 -252
+10 -6
arch/mips/Makefile
··· 181 181 cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 182 182 cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap 183 183 184 - cflags-$(CONFIG_CPU_LOONGSON2E) += $(call cc-option,-march=loongson2e) -Wa,--trap 185 - cflags-$(CONFIG_CPU_LOONGSON2F) += $(call cc-option,-march=loongson2f) -Wa,--trap 186 - cflags-$(CONFIG_CPU_LOONGSON64) += $(call cc-option,-march=loongson3a,-march=mips64r2) -Wa,--trap 184 + cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -Wa,--trap 185 + cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -Wa,--trap 187 186 # Some -march= flags enable MMI instructions, and GCC complains about that 188 187 # support being enabled alongside -msoft-float. Thus explicitly disable MMI. 189 188 cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-mno-loongson-mmi) 189 + ifdef CONFIG_CPU_LOONGSON64 190 + cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap 191 + cflags-$(CONFIG_CC_IS_GCC) += -march=loongson3a 192 + cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2 193 + endif 190 194 cflags-$(CONFIG_CPU_LOONGSON64) += $(call cc-option,-mno-loongson-mmi) 191 195 192 196 cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) ··· 303 299 endif 304 300 endif 305 301 306 - ifeq ($(KBUILD_SYM32)$(call cc-option-yn,-msym32), yy) 307 - cflags-y += -msym32 -DKBUILD_64BIT_SYM32 302 + ifeq ($(KBUILD_SYM32), y) 303 + cflags-$(KBUILD_SYM32) += -msym32 -DKBUILD_64BIT_SYM32 308 304 else 309 305 ifeq ($(CONFIG_CPU_DADDI_WORKAROUNDS), y) 310 306 $(error CONFIG_CPU_DADDI_WORKAROUNDS unsupported without -msym32) ··· 345 341 346 342 KBUILD_LDFLAGS += -m $(ld-emul) 347 343 348 - ifdef CONFIG_MIPS 344 + ifdef need-compiler 349 345 CHECKFLAGS += $(shell $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) -dM -E -x c /dev/null | \ 350 346 grep -E -vw '__GNUC_(MINOR_|PATCHLEVEL_)?_' | \ 351 347 sed -e "s/^\#define /-D'/" -e "s/ /'='/" -e "s/$$/'/" -e 's/\$$/&&/g')
-1
arch/mips/bmips/setup.c
··· 16 16 #include <linux/of.h> 17 17 #include <linux/of_clk.h> 18 18 #include <linux/of_fdt.h> 19 - #include <linux/of_platform.h> 20 19 #include <linux/libfdt.h> 21 20 #include <linux/smp.h> 22 21 #include <asm/addrspace.h>
+2 -1
arch/mips/cavium-octeon/flash_setup.c
··· 12 12 #include <linux/semaphore.h> 13 13 #include <linux/mtd/mtd.h> 14 14 #include <linux/mtd/map.h> 15 - #include <linux/of_platform.h> 15 + #include <linux/of.h> 16 + #include <linux/platform_device.h> 16 17 #include <linux/mtd/partitions.h> 17 18 18 19 #include <asm/octeon/octeon.h>
+1 -1
arch/mips/cavium-octeon/octeon-memcpy.S
··· 13 13 * Mnemonic names for arguments to memcpy/__copy_user 14 14 */ 15 15 16 + #include <linux/export.h> 16 17 #include <asm/asm.h> 17 18 #include <asm/asm-offsets.h> 18 - #include <asm/export.h> 19 19 #include <asm/regdef.h> 20 20 21 21 #define dst a0
+2
arch/mips/cavium-octeon/octeon-platform.c
··· 8 8 */ 9 9 10 10 #include <linux/etherdevice.h> 11 + #include <linux/of.h> 11 12 #include <linux/of_platform.h> 12 13 #include <linux/of_fdt.h> 14 + #include <linux/platform_device.h> 13 15 #include <linux/libfdt.h> 14 16 15 17 #include <asm/octeon/octeon.h>
-1
arch/mips/configs/ip22_defconfig
··· 127 127 CONFIG_IP_NF_FILTER=m 128 128 CONFIG_IP_NF_TARGET_REJECT=m 129 129 CONFIG_IP_NF_MANGLE=m 130 - CONFIG_IP_NF_TARGET_CLUSTERIP=m 131 130 CONFIG_IP_NF_TARGET_ECN=m 132 131 CONFIG_IP_NF_TARGET_TTL=m 133 132 CONFIG_IP_NF_RAW=m
+1
arch/mips/configs/loongson3_defconfig
··· 283 283 CONFIG_DRM_AMD_ACP=y 284 284 CONFIG_DRM_AMD_DC=y 285 285 CONFIG_DRM_AMD_DC_SI=y 286 + CONFIG_DRM_AST=m 286 287 CONFIG_DRM_RADEON=m 287 288 CONFIG_DRM_QXL=y 288 289 CONFIG_DRM_VIRTIO_GPU=y
-1
arch/mips/configs/malta_defconfig
··· 127 127 CONFIG_IP_NF_FILTER=m 128 128 CONFIG_IP_NF_TARGET_REJECT=m 129 129 CONFIG_IP_NF_MANGLE=m 130 - CONFIG_IP_NF_TARGET_CLUSTERIP=m 131 130 CONFIG_IP_NF_TARGET_ECN=m 132 131 CONFIG_IP_NF_TARGET_TTL=m 133 132 CONFIG_IP_NF_RAW=m
-1
arch/mips/configs/malta_kvm_defconfig
··· 131 131 CONFIG_IP_NF_FILTER=m 132 132 CONFIG_IP_NF_TARGET_REJECT=m 133 133 CONFIG_IP_NF_MANGLE=m 134 - CONFIG_IP_NF_TARGET_CLUSTERIP=m 135 134 CONFIG_IP_NF_TARGET_ECN=m 136 135 CONFIG_IP_NF_TARGET_TTL=m 137 136 CONFIG_IP_NF_RAW=m
-1
arch/mips/configs/maltaup_xpa_defconfig
··· 128 128 CONFIG_IP_NF_FILTER=m 129 129 CONFIG_IP_NF_TARGET_REJECT=m 130 130 CONFIG_IP_NF_MANGLE=m 131 - CONFIG_IP_NF_TARGET_CLUSTERIP=m 132 131 CONFIG_IP_NF_TARGET_ECN=m 133 132 CONFIG_IP_NF_TARGET_TTL=m 134 133 CONFIG_IP_NF_RAW=m
-1
arch/mips/configs/rm200_defconfig
··· 90 90 CONFIG_IP_NF_FILTER=m 91 91 CONFIG_IP_NF_TARGET_REJECT=m 92 92 CONFIG_IP_NF_MANGLE=m 93 - CONFIG_IP_NF_TARGET_CLUSTERIP=m 94 93 CONFIG_IP_NF_TARGET_ECN=m 95 94 CONFIG_IP_NF_TARGET_TTL=m 96 95 CONFIG_IP_NF_RAW=m
-1
arch/mips/include/asm/Kbuild
··· 7 7 generated-y += unistd_nr_n64.h 8 8 generated-y += unistd_nr_o32.h 9 9 10 - generic-y += export.h 11 10 generic-y += kvm_para.h 12 11 generic-y += mcs_spinlock.h 13 12 generic-y += parport.h
-2
arch/mips/include/asm/mach-loongson32/loongson1.h
··· 45 45 #define LS1X_NAND_BASE 0x1fe78000 46 46 #define LS1X_CLK_BASE 0x1fe78030 47 47 48 - #include <regs-clk.h> 49 48 #include <regs-mux.h> 50 - #include <regs-rtc.h> 51 49 52 50 #endif /* __ASM_MACH_LOONGSON32_LOONGSON1_H */
-81
arch/mips/include/asm/mach-loongson32/regs-clk.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> 4 - * 5 - * Loongson 1 Clock Register Definitions. 6 - */ 7 - 8 - #ifndef __ASM_MACH_LOONGSON32_REGS_CLK_H 9 - #define __ASM_MACH_LOONGSON32_REGS_CLK_H 10 - 11 - #define LS1X_CLK_REG(x) \ 12 - ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x))) 13 - 14 - #define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0) 15 - #define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4) 16 - 17 - #if defined(CONFIG_LOONGSON1_LS1B) 18 - /* Clock PLL Divisor Register Bits */ 19 - #define DIV_DC_EN BIT(31) 20 - #define DIV_DC_RST BIT(30) 21 - #define DIV_CPU_EN BIT(25) 22 - #define DIV_CPU_RST BIT(24) 23 - #define DIV_DDR_EN BIT(19) 24 - #define DIV_DDR_RST BIT(18) 25 - #define RST_DC_EN BIT(5) 26 - #define RST_DC BIT(4) 27 - #define RST_DDR_EN BIT(3) 28 - #define RST_DDR BIT(2) 29 - #define RST_CPU_EN BIT(1) 30 - #define RST_CPU BIT(0) 31 - 32 - #define DIV_DC_SHIFT 26 33 - #define DIV_CPU_SHIFT 20 34 - #define DIV_DDR_SHIFT 14 35 - 36 - #define DIV_DC_WIDTH 4 37 - #define DIV_CPU_WIDTH 4 38 - #define DIV_DDR_WIDTH 4 39 - 40 - #define BYPASS_DC_SHIFT 12 41 - #define BYPASS_DDR_SHIFT 10 42 - #define BYPASS_CPU_SHIFT 8 43 - 44 - #define BYPASS_DC_WIDTH 1 45 - #define BYPASS_DDR_WIDTH 1 46 - #define BYPASS_CPU_WIDTH 1 47 - 48 - #elif defined(CONFIG_LOONGSON1_LS1C) 49 - /* PLL/SDRAM Frequency configuration register Bits */ 50 - #define PLL_VALID BIT(31) 51 - #define FRAC_N GENMASK(23, 16) 52 - #define RST_TIME GENMASK(3, 2) 53 - #define SDRAM_DIV GENMASK(1, 0) 54 - 55 - /* CPU/CAMERA/DC Frequency configuration register Bits */ 56 - #define DIV_DC_EN BIT(31) 57 - #define DIV_DC GENMASK(30, 24) 58 - #define DIV_CAM_EN BIT(23) 59 - #define DIV_CAM GENMASK(22, 16) 60 - #define DIV_CPU_EN BIT(15) 61 - #define DIV_CPU GENMASK(14, 8) 62 - #define DIV_DC_SEL_EN BIT(5) 63 - #define DIV_DC_SEL BIT(4) 64 - #define DIV_CAM_SEL_EN BIT(3) 65 - #define DIV_CAM_SEL BIT(2) 66 - #define DIV_CPU_SEL_EN BIT(1) 67 - #define DIV_CPU_SEL BIT(0) 68 - 69 - #define DIV_DC_SHIFT 24 70 - #define DIV_CAM_SHIFT 16 71 - #define DIV_CPU_SHIFT 8 72 - #define DIV_DDR_SHIFT 0 73 - 74 - #define DIV_DC_WIDTH 7 75 - #define DIV_CAM_WIDTH 7 76 - #define DIV_CPU_WIDTH 7 77 - #define DIV_DDR_WIDTH 2 78 - 79 - #endif 80 - 81 - #endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */
-19
arch/mips/include/asm/mach-loongson32/regs-rtc.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com> 4 - * 5 - * Loongson 1 RTC timer Register Definitions. 6 - */ 7 - 8 - #ifndef __ASM_MACH_LOONGSON32_REGS_RTC_H 9 - #define __ASM_MACH_LOONGSON32_REGS_RTC_H 10 - 11 - #define LS1X_RTC_REG(x) \ 12 - ((void __iomem *)KSEG1ADDR(LS1X_RTC_BASE + (x))) 13 - 14 - #define LS1X_RTC_CTRL LS1X_RTC_REG(0x40) 15 - 16 - #define RTC_EXTCLK_OK (BIT(5) | BIT(8)) 17 - #define RTC_EXTCLK_EN BIT(8) 18 - 19 - #endif /* __ASM_MACH_LOONGSON32_REGS_RTC_H */
+1 -1
arch/mips/kernel/mcount.S
··· 10 10 * Author: Wu Zhangjin <wuzhangjin@gmail.com> 11 11 */ 12 12 13 - #include <asm/export.h> 13 + #include <linux/export.h> 14 14 #include <asm/regdef.h> 15 15 #include <asm/stackframe.h> 16 16 #include <asm/ftrace.h>
-1
arch/mips/kernel/octeon_switch.S
··· 11 11 * written by Carsten Langgaard, carstenl@mips.com 12 12 */ 13 13 #include <asm/asm.h> 14 - #include <asm/export.h> 15 14 #include <asm/asm-offsets.h> 16 15 #include <asm/mipsregs.h> 17 16 #include <asm/regdef.h>
+1 -1
arch/mips/kernel/r2300_fpu.S
··· 11 11 * Further modifications to make this work: 12 12 * Copyright (c) 1998 Harald Koerfgen 13 13 */ 14 + #include <linux/export.h> 14 15 #include <asm/asm.h> 15 16 #include <asm/asmmacro.h> 16 17 #include <asm/errno.h> 17 - #include <asm/export.h> 18 18 #include <asm/fpregdef.h> 19 19 #include <asm/mipsregs.h> 20 20 #include <asm/asm-offsets.h>
-1
arch/mips/kernel/r2300_switch.S
··· 13 13 */ 14 14 #include <asm/asm.h> 15 15 #include <asm/cachectl.h> 16 - #include <asm/export.h> 17 16 #include <asm/fpregdef.h> 18 17 #include <asm/mipsregs.h> 19 18 #include <asm/asm-offsets.h>
+1 -1
arch/mips/kernel/r4k_fpu.S
··· 12 12 * Copyright (C) 2000 MIPS Technologies, Inc. 13 13 * Copyright (C) 1999, 2001 Silicon Graphics, Inc. 14 14 */ 15 + #include <linux/export.h> 15 16 #include <asm/asm.h> 16 17 #include <asm/asmmacro.h> 17 18 #include <asm/errno.h> 18 - #include <asm/export.h> 19 19 #include <asm/fpregdef.h> 20 20 #include <asm/mipsregs.h> 21 21 #include <asm/asm-offsets.h>
+1 -1
arch/mips/lantiq/irq.c
··· 10 10 #include <linux/sched.h> 11 11 #include <linux/irqchip.h> 12 12 #include <linux/irqdomain.h> 13 - #include <linux/of_platform.h> 13 + #include <linux/of.h> 14 14 #include <linux/of_address.h> 15 15 #include <linux/of_irq.h> 16 16
+2 -1
arch/mips/lantiq/xway/dcdc.c
··· 6 6 */ 7 7 8 8 #include <linux/ioport.h> 9 - #include <linux/of_platform.h> 9 + #include <linux/mod_devicetable.h> 10 + #include <linux/platform_device.h> 10 11 11 12 #include <lantiq_soc.h> 12 13
+2 -1
arch/mips/lantiq/xway/gptu.c
··· 8 8 #include <linux/interrupt.h> 9 9 #include <linux/ioport.h> 10 10 #include <linux/init.h> 11 - #include <linux/of_platform.h> 11 + #include <linux/mod_devicetable.h> 12 12 #include <linux/of_irq.h> 13 + #include <linux/platform_device.h> 13 14 14 15 #include <lantiq_soc.h> 15 16 #include "../clk.h"
-1
arch/mips/lantiq/xway/sysctrl.c
··· 10 10 #include <linux/clkdev.h> 11 11 #include <linux/spinlock.h> 12 12 #include <linux/of.h> 13 - #include <linux/of_platform.h> 14 13 #include <linux/of_address.h> 15 14 16 15 #include <lantiq_soc.h>
+2 -1
arch/mips/lantiq/xway/vmmc.c
··· 7 7 #include <linux/err.h> 8 8 #include <linux/export.h> 9 9 #include <linux/gpio/consumer.h> 10 - #include <linux/of_platform.h> 10 + #include <linux/mod_devicetable.h> 11 + #include <linux/platform_device.h> 11 12 #include <linux/dma-mapping.h> 12 13 13 14 #include <lantiq_soc.h>
+1 -1
arch/mips/lib/csum_partial.S
··· 11 11 * Copyright (C) 2014 Imagination Technologies Ltd. 12 12 */ 13 13 #include <linux/errno.h> 14 + #include <linux/export.h> 14 15 #include <asm/asm.h> 15 16 #include <asm/asm-offsets.h> 16 - #include <asm/export.h> 17 17 #include <asm/regdef.h> 18 18 19 19 #ifdef CONFIG_64BIT
+1 -1
arch/mips/lib/memcpy.S
··· 32 32 #undef CONFIG_CPU_HAS_PREFETCH 33 33 #endif 34 34 35 + #include <linux/export.h> 35 36 #include <asm/asm.h> 36 37 #include <asm/asm-offsets.h> 37 - #include <asm/export.h> 38 38 #include <asm/regdef.h> 39 39 40 40 #define dst a0
+1 -1
arch/mips/lib/memset.S
··· 8 8 * Copyright (C) 2007 by Maciej W. Rozycki 9 9 * Copyright (C) 2011, 2012 MIPS Technologies, Inc. 10 10 */ 11 + #include <linux/export.h> 11 12 #include <asm/asm.h> 12 13 #include <asm/asm-offsets.h> 13 - #include <asm/export.h> 14 14 #include <asm/regdef.h> 15 15 16 16 #if LONGSIZE == 4
+1 -1
arch/mips/lib/strncpy_user.S
··· 7 7 * Copyright (C) 2011 MIPS Technologies, Inc. 8 8 */ 9 9 #include <linux/errno.h> 10 + #include <linux/export.h> 10 11 #include <asm/asm.h> 11 12 #include <asm/asm-offsets.h> 12 - #include <asm/export.h> 13 13 #include <asm/regdef.h> 14 14 15 15 #define EX(insn,reg,addr,handler) \
+1 -1
arch/mips/lib/strnlen_user.S
··· 6 6 * Copyright (c) 1996, 1998, 1999, 2004 by Ralf Baechle 7 7 * Copyright (c) 1999 Silicon Graphics, Inc. 8 8 */ 9 + #include <linux/export.h> 9 10 #include <asm/asm.h> 10 11 #include <asm/asm-offsets.h> 11 - #include <asm/export.h> 12 12 #include <asm/regdef.h> 13 13 14 14 #define EX(insn,reg,addr,handler) \
-8
arch/mips/loongson32/common/platform.c
··· 265 265 }; 266 266 267 267 /* Real Time Clock */ 268 - void __init ls1x_rtc_set_extclk(struct platform_device *pdev) 269 - { 270 - u32 val = __raw_readl(LS1X_RTC_CTRL); 271 - 272 - if (!(val & RTC_EXTCLK_OK)) 273 - __raw_writel(val | RTC_EXTCLK_EN, LS1X_RTC_CTRL); 274 - } 275 - 276 268 struct platform_device ls1x_rtc_pdev = { 277 269 .name = "ls1x-rtc", 278 270 .id = -1,
+80 -80
arch/mips/loongson64/smp.c
··· 187 187 188 188 static void ipi_set0_regs_init(void) 189 189 { 190 - ipi_set0_regs[0] = (void *) 190 + ipi_set0_regs[0] = (void __iomem *) 191 191 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0); 192 - ipi_set0_regs[1] = (void *) 192 + ipi_set0_regs[1] = (void __iomem *) 193 193 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0); 194 - ipi_set0_regs[2] = (void *) 194 + ipi_set0_regs[2] = (void __iomem *) 195 195 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0); 196 - ipi_set0_regs[3] = (void *) 196 + ipi_set0_regs[3] = (void __iomem *) 197 197 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0); 198 - ipi_set0_regs[4] = (void *) 198 + ipi_set0_regs[4] = (void __iomem *) 199 199 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0); 200 - ipi_set0_regs[5] = (void *) 200 + ipi_set0_regs[5] = (void __iomem *) 201 201 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0); 202 - ipi_set0_regs[6] = (void *) 202 + ipi_set0_regs[6] = (void __iomem *) 203 203 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0); 204 - ipi_set0_regs[7] = (void *) 204 + ipi_set0_regs[7] = (void __iomem *) 205 205 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0); 206 - ipi_set0_regs[8] = (void *) 206 + ipi_set0_regs[8] = (void __iomem *) 207 207 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0); 208 - ipi_set0_regs[9] = (void *) 208 + ipi_set0_regs[9] = (void __iomem *) 209 209 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0); 210 - ipi_set0_regs[10] = (void *) 210 + ipi_set0_regs[10] = (void __iomem *) 211 211 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0); 212 - ipi_set0_regs[11] = (void *) 212 + ipi_set0_regs[11] = (void __iomem *) 213 213 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0); 214 - ipi_set0_regs[12] = (void *) 214 + ipi_set0_regs[12] = (void __iomem *) 215 215 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0); 216 - ipi_set0_regs[13] = (void *) 216 + ipi_set0_regs[13] = (void __iomem *) 217 217 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0); 218 - ipi_set0_regs[14] = (void *) 218 + ipi_set0_regs[14] = (void __iomem *) 219 219 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0); 220 - ipi_set0_regs[15] = (void *) 220 + ipi_set0_regs[15] = (void __iomem *) 221 221 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0); 222 222 } 223 223 224 224 static void ipi_clear0_regs_init(void) 225 225 { 226 - ipi_clear0_regs[0] = (void *) 226 + ipi_clear0_regs[0] = (void __iomem *) 227 227 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0); 228 - ipi_clear0_regs[1] = (void *) 228 + ipi_clear0_regs[1] = (void __iomem *) 229 229 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0); 230 - ipi_clear0_regs[2] = (void *) 230 + ipi_clear0_regs[2] = (void __iomem *) 231 231 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0); 232 - ipi_clear0_regs[3] = (void *) 232 + ipi_clear0_regs[3] = (void __iomem *) 233 233 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0); 234 - ipi_clear0_regs[4] = (void *) 234 + ipi_clear0_regs[4] = (void __iomem *) 235 235 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0); 236 - ipi_clear0_regs[5] = (void *) 236 + ipi_clear0_regs[5] = (void __iomem *) 237 237 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0); 238 - ipi_clear0_regs[6] = (void *) 238 + ipi_clear0_regs[6] = (void __iomem *) 239 239 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0); 240 - ipi_clear0_regs[7] = (void *) 240 + ipi_clear0_regs[7] = (void __iomem *) 241 241 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0); 242 - ipi_clear0_regs[8] = (void *) 242 + ipi_clear0_regs[8] = (void __iomem *) 243 243 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0); 244 - ipi_clear0_regs[9] = (void *) 244 + ipi_clear0_regs[9] = (void __iomem *) 245 245 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0); 246 - ipi_clear0_regs[10] = (void *) 246 + ipi_clear0_regs[10] = (void __iomem *) 247 247 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0); 248 - ipi_clear0_regs[11] = (void *) 248 + ipi_clear0_regs[11] = (void __iomem *) 249 249 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0); 250 - ipi_clear0_regs[12] = (void *) 250 + ipi_clear0_regs[12] = (void __iomem *) 251 251 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0); 252 - ipi_clear0_regs[13] = (void *) 252 + ipi_clear0_regs[13] = (void __iomem *) 253 253 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0); 254 - ipi_clear0_regs[14] = (void *) 254 + ipi_clear0_regs[14] = (void __iomem *) 255 255 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0); 256 - ipi_clear0_regs[15] = (void *) 256 + ipi_clear0_regs[15] = (void __iomem *) 257 257 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0); 258 258 } 259 259 260 260 static void ipi_status0_regs_init(void) 261 261 { 262 - ipi_status0_regs[0] = (void *) 262 + ipi_status0_regs[0] = (void __iomem *) 263 263 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0); 264 - ipi_status0_regs[1] = (void *) 264 + ipi_status0_regs[1] = (void __iomem *) 265 265 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0); 266 - ipi_status0_regs[2] = (void *) 266 + ipi_status0_regs[2] = (void __iomem *) 267 267 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0); 268 - ipi_status0_regs[3] = (void *) 268 + ipi_status0_regs[3] = (void __iomem *) 269 269 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0); 270 - ipi_status0_regs[4] = (void *) 270 + ipi_status0_regs[4] = (void __iomem *) 271 271 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0); 272 - ipi_status0_regs[5] = (void *) 272 + ipi_status0_regs[5] = (void __iomem *) 273 273 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0); 274 - ipi_status0_regs[6] = (void *) 274 + ipi_status0_regs[6] = (void __iomem *) 275 275 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0); 276 - ipi_status0_regs[7] = (void *) 276 + ipi_status0_regs[7] = (void __iomem *) 277 277 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0); 278 - ipi_status0_regs[8] = (void *) 278 + ipi_status0_regs[8] = (void __iomem *) 279 279 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0); 280 - ipi_status0_regs[9] = (void *) 280 + ipi_status0_regs[9] = (void __iomem *) 281 281 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0); 282 - ipi_status0_regs[10] = (void *) 282 + ipi_status0_regs[10] = (void __iomem *) 283 283 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0); 284 - ipi_status0_regs[11] = (void *) 284 + ipi_status0_regs[11] = (void __iomem *) 285 285 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0); 286 - ipi_status0_regs[12] = (void *) 286 + ipi_status0_regs[12] = (void __iomem *) 287 287 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0); 288 - ipi_status0_regs[13] = (void *) 288 + ipi_status0_regs[13] = (void __iomem *) 289 289 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0); 290 - ipi_status0_regs[14] = (void *) 290 + ipi_status0_regs[14] = (void __iomem *) 291 291 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0); 292 - ipi_status0_regs[15] = (void *) 292 + ipi_status0_regs[15] = (void __iomem *) 293 293 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0); 294 294 } 295 295 296 296 static void ipi_en0_regs_init(void) 297 297 { 298 - ipi_en0_regs[0] = (void *) 298 + ipi_en0_regs[0] = (void __iomem *) 299 299 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0); 300 - ipi_en0_regs[1] = (void *) 300 + ipi_en0_regs[1] = (void __iomem *) 301 301 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0); 302 - ipi_en0_regs[2] = (void *) 302 + ipi_en0_regs[2] = (void __iomem *) 303 303 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0); 304 - ipi_en0_regs[3] = (void *) 304 + ipi_en0_regs[3] = (void __iomem *) 305 305 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0); 306 - ipi_en0_regs[4] = (void *) 306 + ipi_en0_regs[4] = (void __iomem *) 307 307 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0); 308 - ipi_en0_regs[5] = (void *) 308 + ipi_en0_regs[5] = (void __iomem *) 309 309 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0); 310 - ipi_en0_regs[6] = (void *) 310 + ipi_en0_regs[6] = (void __iomem *) 311 311 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0); 312 - ipi_en0_regs[7] = (void *) 312 + ipi_en0_regs[7] = (void __iomem *) 313 313 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0); 314 - ipi_en0_regs[8] = (void *) 314 + ipi_en0_regs[8] = (void __iomem *) 315 315 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0); 316 - ipi_en0_regs[9] = (void *) 316 + ipi_en0_regs[9] = (void __iomem *) 317 317 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0); 318 - ipi_en0_regs[10] = (void *) 318 + ipi_en0_regs[10] = (void __iomem *) 319 319 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0); 320 - ipi_en0_regs[11] = (void *) 320 + ipi_en0_regs[11] = (void __iomem *) 321 321 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0); 322 - ipi_en0_regs[12] = (void *) 322 + ipi_en0_regs[12] = (void __iomem *) 323 323 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0); 324 - ipi_en0_regs[13] = (void *) 324 + ipi_en0_regs[13] = (void __iomem *) 325 325 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0); 326 - ipi_en0_regs[14] = (void *) 326 + ipi_en0_regs[14] = (void __iomem *) 327 327 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0); 328 - ipi_en0_regs[15] = (void *) 328 + ipi_en0_regs[15] = (void __iomem *) 329 329 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0); 330 330 } 331 331 332 332 static void ipi_mailbox_buf_init(void) 333 333 { 334 - ipi_mailbox_buf[0] = (void *) 334 + ipi_mailbox_buf[0] = (void __iomem *) 335 335 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF); 336 - ipi_mailbox_buf[1] = (void *) 336 + ipi_mailbox_buf[1] = (void __iomem *) 337 337 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF); 338 - ipi_mailbox_buf[2] = (void *) 338 + ipi_mailbox_buf[2] = (void __iomem *) 339 339 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF); 340 - ipi_mailbox_buf[3] = (void *) 340 + ipi_mailbox_buf[3] = (void __iomem *) 341 341 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF); 342 - ipi_mailbox_buf[4] = (void *) 342 + ipi_mailbox_buf[4] = (void __iomem *) 343 343 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF); 344 - ipi_mailbox_buf[5] = (void *) 344 + ipi_mailbox_buf[5] = (void __iomem *) 345 345 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF); 346 - ipi_mailbox_buf[6] = (void *) 346 + ipi_mailbox_buf[6] = (void __iomem *) 347 347 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF); 348 - ipi_mailbox_buf[7] = (void *) 348 + ipi_mailbox_buf[7] = (void __iomem *) 349 349 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF); 350 - ipi_mailbox_buf[8] = (void *) 350 + ipi_mailbox_buf[8] = (void __iomem *) 351 351 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF); 352 - ipi_mailbox_buf[9] = (void *) 352 + ipi_mailbox_buf[9] = (void __iomem *) 353 353 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF); 354 - ipi_mailbox_buf[10] = (void *) 354 + ipi_mailbox_buf[10] = (void __iomem *) 355 355 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF); 356 - ipi_mailbox_buf[11] = (void *) 356 + ipi_mailbox_buf[11] = (void __iomem *) 357 357 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF); 358 - ipi_mailbox_buf[12] = (void *) 358 + ipi_mailbox_buf[12] = (void __iomem *) 359 359 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF); 360 - ipi_mailbox_buf[13] = (void *) 360 + ipi_mailbox_buf[13] = (void __iomem *) 361 361 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF); 362 - ipi_mailbox_buf[14] = (void *) 362 + ipi_mailbox_buf[14] = (void __iomem *) 363 363 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF); 364 - ipi_mailbox_buf[15] = (void *) 364 + ipi_mailbox_buf[15] = (void __iomem *) 365 365 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF); 366 366 } 367 367
+1 -1
arch/mips/mm/page-funcs.S
··· 8 8 * Copyright (C) 2012 MIPS Technologies, Inc. 9 9 * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org> 10 10 */ 11 + #include <linux/export.h> 11 12 #include <asm/asm.h> 12 - #include <asm/export.h> 13 13 #include <asm/regdef.h> 14 14 15 15 #ifdef CONFIG_SIBYTE_DMA_PAGEOPS
+1 -1
arch/mips/mm/tlb-funcs.S
··· 11 11 * Copyright (C) 2012 MIPS Technologies, Inc. 12 12 * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org> 13 13 */ 14 + #include <linux/export.h> 14 15 #include <asm/asm.h> 15 - #include <asm/export.h> 16 16 #include <asm/regdef.h> 17 17 18 18 #define FASTPATH_SIZE 128
+2 -2
arch/mips/pci/pci-lantiq.c
··· 13 13 #include <linux/mm.h> 14 14 #include <linux/vmalloc.h> 15 15 #include <linux/clk.h> 16 - #include <linux/of_platform.h> 17 - #include <linux/of_irq.h> 16 + #include <linux/of.h> 18 17 #include <linux/of_pci.h> 18 + #include <linux/platform_device.h> 19 19 20 20 #include <asm/addrspace.h> 21 21
+2 -3
arch/mips/pci/pci-rt2880.c
··· 13 13 #include <linux/pci.h> 14 14 #include <linux/io.h> 15 15 #include <linux/init.h> 16 - #include <linux/of_platform.h> 17 - #include <linux/of_irq.h> 18 - #include <linux/of_pci.h> 16 + #include <linux/mod_devicetable.h> 17 + #include <linux/platform_device.h> 19 18 20 19 #include <asm/mach-ralink/rt288x.h> 21 20
+1 -1
arch/mips/pic32/pic32mzda/config.c
··· 5 5 */ 6 6 #include <linux/init.h> 7 7 #include <linux/io.h> 8 - #include <linux/of_platform.h> 8 + #include <linux/spinlock.h> 9 9 10 10 #include <asm/mach-pic32/pic32.h> 11 11
+2
arch/mips/ralink/ill_acc.c
··· 5 5 */ 6 6 7 7 #include <linux/interrupt.h> 8 + #include <linux/of.h> 8 9 #include <linux/of_platform.h> 9 10 #include <linux/of_irq.h> 11 + #include <linux/platform_device.h> 10 12 11 13 #include <asm/mach-ralink/ralink_regs.h> 12 14
+1 -1
arch/mips/ralink/irq.c
··· 7 7 8 8 #include <linux/io.h> 9 9 #include <linux/bitops.h> 10 - #include <linux/of_platform.h> 10 + #include <linux/of.h> 11 11 #include <linux/of_address.h> 12 12 #include <linux/of_irq.h> 13 13 #include <linux/irqdomain.h>
+1 -1
arch/mips/ralink/of.c
··· 14 14 #include <linux/of_fdt.h> 15 15 #include <linux/kernel.h> 16 16 #include <linux/memblock.h> 17 - #include <linux/of_platform.h> 17 + #include <linux/of.h> 18 18 #include <linux/of_address.h> 19 19 20 20 #include <asm/reboot.h>
-2
arch/mips/ralink/prom.c
··· 7 7 */ 8 8 9 9 #include <linux/string.h> 10 - #include <linux/of_fdt.h> 11 - #include <linux/of_platform.h> 12 10 13 11 #include <asm/bootinfo.h> 14 12 #include <asm/addrspace.h>
+23 -20
arch/mips/txx9/generic/pci.c
··· 51 51 unsigned short vid; 52 52 int cap66 = -1; 53 53 u16 stat; 54 + int ret; 54 55 55 56 /* It seems SLC90E66 needs some time after PCI reset... */ 56 57 mdelay(80); ··· 61 60 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { 62 61 if (PCI_FUNC(pci_devfn)) 63 62 continue; 64 - if (early_read_config_word(hose, top_bus, current_bus, 65 - pci_devfn, PCI_VENDOR_ID, &vid) != 66 - PCIBIOS_SUCCESSFUL) 63 + ret = early_read_config_word(hose, top_bus, current_bus, 64 + pci_devfn, PCI_VENDOR_ID, &vid); 65 + if (ret != PCIBIOS_SUCCESSFUL) 67 66 continue; 68 67 if (vid == 0xffff) 69 68 continue; ··· 344 343 345 344 static void final_fixup(struct pci_dev *dev) 346 345 { 346 + unsigned long timeout; 347 347 unsigned char bist; 348 + int ret; 348 349 349 350 /* Do build-in self test */ 350 - if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL && 351 - (bist & PCI_BIST_CAPABLE)) { 352 - unsigned long timeout; 353 - pci_set_power_state(dev, PCI_D0); 354 - pr_info("PCI: %s BIST...", pci_name(dev)); 355 - pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START); 356 - timeout = jiffies + HZ * 2; /* timeout after 2 sec */ 357 - do { 358 - pci_read_config_byte(dev, PCI_BIST, &bist); 359 - if (time_after(jiffies, timeout)) 360 - break; 361 - } while (bist & PCI_BIST_START); 362 - if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START)) 363 - pr_cont("failed. (0x%x)\n", bist); 364 - else 365 - pr_cont("OK.\n"); 366 - } 351 + ret = pci_read_config_byte(dev, PCI_BIST, &bist); 352 + if ((ret != PCIBIOS_SUCCESSFUL) || !(bist & PCI_BIST_CAPABLE)) 353 + return; 354 + 355 + pci_set_power_state(dev, PCI_D0); 356 + pr_info("PCI: %s BIST...", pci_name(dev)); 357 + pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START); 358 + timeout = jiffies + HZ * 2; /* timeout after 2 sec */ 359 + do { 360 + pci_read_config_byte(dev, PCI_BIST, &bist); 361 + if (time_after(jiffies, timeout)) 362 + break; 363 + } while (bist & PCI_BIST_START); 364 + if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START)) 365 + pr_cont("failed. (0x%x)\n", bist); 366 + else 367 + pr_cont("OK.\n"); 367 368 } 368 369 369 370 #ifdef CONFIG_TOSHIBA_FPCIB0
+2
arch/mips/vdso/vdso.lds.S
··· 94 94 #ifndef CONFIG_MIPS_DISABLE_VDSO 95 95 global: 96 96 __vdso_clock_gettime; 97 + #ifdef CONFIG_MIPS_CLOCK_VSYSCALL 97 98 __vdso_gettimeofday; 99 + #endif 98 100 __vdso_clock_getres; 99 101 #if _MIPS_SIM != _MIPS_SIM_ABI64 100 102 __vdso_clock_gettime64;
+2
drivers/usb/dwc3/dwc3-octeon.c
··· 13 13 #include <linux/io.h> 14 14 #include <linux/module.h> 15 15 #include <linux/mutex.h> 16 + #include <linux/of.h> 16 17 #include <linux/of_platform.h> 18 + #include <linux/platform_device.h> 17 19 18 20 /* 19 21 * USB Control Register