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clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks
According to the R-Car V4H Series Hardware User’s Manual Rev.1.00, the
parent clock of the Pin Function (PFC/GPIO) module clocks is the CP
clock.
Fix this by adding the missing CP clock, and correcting the PFC parents.
Fixes: f2afa78d5a0c0b0b ("dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions")
Fixes: 36ff366033f0dde1 ("clk: renesas: r8a779g0: Add PFC/GPIO clocks")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/5401fccd204dc90b44f0013e7f53b9eff8df8214.1706197297.git.geert+renesas@glider.be
+7
-5
+6
-5
drivers/clk/renesas/r8a779g0-cpg-mssr.c
+6
-5
drivers/clk/renesas/r8a779g0-cpg-mssr.c
···
22
22
23
23
enum clk_ids {
24
24
/* Core Clock Outputs exported to DT */
25
-
LAST_DT_CORE_CLK = R8A779G0_CLK_R,
25
+
LAST_DT_CORE_CLK = R8A779G0_CLK_CP,
26
26
27
27
/* External Input Clocks */
28
28
CLK_EXTAL,
···
141
141
DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
142
142
DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
143
143
DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1),
144
+
DEF_FIXED("cp", R8A779G0_CLK_CP, CLK_EXTAL, 2, 1),
144
145
DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1),
145
146
DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
146
147
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
···
233
232
DEF_MOD("cmt1", 911, R8A779G0_CLK_R),
234
233
DEF_MOD("cmt2", 912, R8A779G0_CLK_R),
235
234
DEF_MOD("cmt3", 913, R8A779G0_CLK_R),
236
-
DEF_MOD("pfc0", 915, R8A779G0_CLK_CL16M),
237
-
DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M),
238
-
DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M),
239
-
DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M),
235
+
DEF_MOD("pfc0", 915, R8A779G0_CLK_CP),
236
+
DEF_MOD("pfc1", 916, R8A779G0_CLK_CP),
237
+
DEF_MOD("pfc2", 917, R8A779G0_CLK_CP),
238
+
DEF_MOD("pfc3", 918, R8A779G0_CLK_CP),
240
239
DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
241
240
DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC),
242
241
DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),