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mips: Add MIPS Release 5 support

There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.

Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.

So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.

So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.

Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.

Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

authored by

Serge Semin and committed by
Thomas Bogendoerfer ab7c01fd bbb5946e

+163 -57
+51 -5
arch/mips/Kconfig
··· 1516 1516 specific type of processor in your system, choose those that one 1517 1517 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system. 1518 1518 1519 + config CPU_MIPS32_R5 1520 + bool "MIPS32 Release 5" 1521 + depends on SYS_HAS_CPU_MIPS32_R5 1522 + select CPU_HAS_PREFETCH 1523 + select CPU_SUPPORTS_32BIT_KERNEL 1524 + select CPU_SUPPORTS_HIGHMEM 1525 + select CPU_SUPPORTS_MSA 1526 + select HAVE_KVM 1527 + select MIPS_O32_FP64_SUPPORT 1528 + help 1529 + Choose this option to build a kernel for release 5 or later of the 1530 + MIPS32 architecture. New MIPS processors, starting with the Warrior 1531 + family, are based on a MIPS32r5 processor. If you own an older 1532 + processor, you probably need to select MIPS32r1 or MIPS32r2 instead. 1533 + 1519 1534 config CPU_MIPS32_R6 1520 1535 bool "MIPS32 Release 6" 1521 1536 depends on SYS_HAS_CPU_MIPS32_R6 ··· 1582 1567 MIPS processor are based on a MIPS64 processor. If you know the 1583 1568 specific type of processor in your system, choose those that one 1584 1569 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system. 1570 + 1571 + config CPU_MIPS64_R5 1572 + bool "MIPS64 Release 5" 1573 + depends on SYS_HAS_CPU_MIPS64_R5 1574 + select CPU_HAS_PREFETCH 1575 + select CPU_SUPPORTS_32BIT_KERNEL 1576 + select CPU_SUPPORTS_64BIT_KERNEL 1577 + select CPU_SUPPORTS_HIGHMEM 1578 + select CPU_SUPPORTS_HUGEPAGES 1579 + select CPU_SUPPORTS_MSA 1580 + select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32 1581 + select HAVE_KVM 1582 + help 1583 + Choose this option to build a kernel for release 5 or later of the 1584 + MIPS64 architecture. This is a intermediate MIPS architecture 1585 + release partly implementing release 6 features. Though there is no 1586 + any hardware known to be based on this release. 1585 1587 1586 1588 config CPU_MIPS64_R6 1587 1589 bool "MIPS64 Release 6" ··· 1794 1762 config CPU_MIPS32_3_5_FEATURES 1795 1763 bool "MIPS32 Release 3.5 Features" 1796 1764 depends on SYS_HAS_CPU_MIPS32_R3_5 1797 - depends on CPU_MIPS32_R2 || CPU_MIPS32_R6 1765 + depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 1798 1766 help 1799 1767 Choose this option to build a kernel for release 2 or later of the 1800 1768 MIPS32 architecture including features from the 3.5 release such as ··· 1814 1782 config CPU_MIPS32_R5_FEATURES 1815 1783 bool "MIPS32 Release 5 Features" 1816 1784 depends on SYS_HAS_CPU_MIPS32_R5 1817 - depends on CPU_MIPS32_R2 1785 + depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 1818 1786 help 1819 1787 Choose this option to build a kernel for release 2 or later of the 1820 1788 MIPS32 architecture including features from release 5 such as ··· 2052 2020 # 2053 2021 config CPU_MIPS32 2054 2022 bool 2055 - default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 2023 + default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \ 2024 + CPU_MIPS32_R6 2056 2025 2057 2026 config CPU_MIPS64 2058 2027 bool 2059 - default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 2028 + default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \ 2029 + CPU_MIPS64_R6 2060 2030 2061 2031 # 2062 2032 # These indicate the revision of the architecture ··· 2070 2036 config CPU_MIPSR2 2071 2037 bool 2072 2038 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON 2039 + select CPU_HAS_RIXI 2040 + select CPU_HAS_DIEI if !CPU_DIEI_BROKEN 2041 + select MIPS_SPRAM 2042 + 2043 + config CPU_MIPSR5 2044 + bool 2045 + default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 2073 2046 select CPU_HAS_RIXI 2074 2047 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN 2075 2048 select MIPS_SPRAM ··· 2095 2054 int 2096 2055 default 1 if CPU_MIPSR1 2097 2056 default 2 if CPU_MIPSR2 2057 + default 5 if CPU_MIPSR5 2098 2058 default 6 if CPU_MIPSR6 2099 2059 default 0 2100 2060 help ··· 2685 2643 2686 2644 config RELOCATABLE 2687 2645 bool "Relocatable kernel" 2688 - depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC) 2646 + depends on SYS_SUPPORTS_RELOCATABLE 2647 + depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \ 2648 + CPU_MIPS32_R5 || CPU_MIPS64_R5 || \ 2649 + CPU_MIPS32_R6 || CPU_MIPS64_R6 || \ 2650 + CAVIUM_OCTEON_SOC 2689 2651 help 2690 2652 This builds a kernel image that retains relocation information 2691 2653 so it can be loaded someplace besides the default 1MB.
+2
arch/mips/Makefile
··· 146 146 cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap 147 147 cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap 148 148 cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,--trap 149 + cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg 149 150 cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap -modd-spreg 150 151 cflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,--trap 151 152 cflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,--trap 153 + cflags-$(CONFIG_CPU_MIPS64_R5) += -march=mips64r5 -Wa,--trap 152 154 cflags-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,--trap 153 155 cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap 154 156 cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=r5000) \
+10 -8
arch/mips/include/asm/asmmacro.h
··· 44 44 .endm 45 45 #endif 46 46 47 - #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) 47 + #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \ 48 + defined(CONFIG_CPU_MIPSR6) 48 49 .macro local_irq_enable reg=t0 49 50 ei 50 51 irq_enable_hazard ··· 55 54 di 56 55 irq_disable_hazard 57 56 .endm 58 - #else 57 + #else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */ 59 58 .macro local_irq_enable reg=t0 60 59 mfc0 \reg, CP0_STATUS 61 60 ori \reg, \reg, 1 ··· 80 79 sw \reg, TI_PRE_COUNT($28) 81 80 #endif 82 81 .endm 83 - #endif /* CONFIG_CPU_MIPSR2 */ 82 + #endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */ 84 83 85 84 .macro fpu_save_16even thread tmp=t0 86 85 .set push ··· 132 131 133 132 .macro fpu_save_double thread status tmp 134 133 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ 135 - defined(CONFIG_CPU_MIPSR6) 134 + defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6) 136 135 sll \tmp, \status, 5 137 136 bgez \tmp, 10f 138 137 fpu_save_16odd \thread ··· 191 190 192 191 .macro fpu_restore_double thread status tmp 193 192 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ 194 - defined(CONFIG_CPU_MIPSR6) 193 + defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6) 195 194 sll \tmp, \status, 5 196 195 bgez \tmp, 10f # 16 register mode? 197 196 ··· 201 200 fpu_restore_16even \thread \tmp 202 201 .endm 203 202 204 - #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) 203 + #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \ 204 + defined(CONFIG_CPU_MIPSR6) 205 205 .macro _EXT rd, rs, p, s 206 206 ext \rd, \rs, \p, \s 207 207 .endm 208 - #else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */ 208 + #else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */ 209 209 .macro _EXT rd, rs, p, s 210 210 srl \rd, \rs, \p 211 211 andi \rd, \rd, (1 << \s) - 1 212 212 .endm 213 - #endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */ 213 + #endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */ 214 214 215 215 /* 216 216 * Temporary until all gas have MT ASE support
+5
arch/mips/include/asm/compiler.h
··· 57 57 #define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL 58 58 #define MIPS_ISA_LEVEL_RAW mips64r6 59 59 #define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW 60 + #elif defined(CONFIG_CPU_MIPSR5) 61 + #define MIPS_ISA_LEVEL "mips64r5" 62 + #define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL 63 + #define MIPS_ISA_LEVEL_RAW mips64r5 64 + #define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW 60 65 #else 61 66 /* MIPS64 is a superset of MIPS32 */ 62 67 #define MIPS_ISA_LEVEL "mips64r2"
+20 -7
arch/mips/include/asm/cpu-features.h
··· 284 284 #ifndef cpu_has_mips32r2 285 285 # define cpu_has_mips32r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2) 286 286 #endif 287 + #ifndef cpu_has_mips32r5 288 + # define cpu_has_mips32r5 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5) 289 + #endif 287 290 #ifndef cpu_has_mips32r6 288 291 # define cpu_has_mips32r6 __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6) 289 292 #endif ··· 295 292 #endif 296 293 #ifndef cpu_has_mips64r2 297 294 # define cpu_has_mips64r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2) 295 + #endif 296 + #ifndef cpu_has_mips64r5 297 + # define cpu_has_mips64r5 (cpu_has_64bits && \ 298 + __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5)) 298 299 #endif 299 300 #ifndef cpu_has_mips64r6 300 301 # define cpu_has_mips64r6 __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6) ··· 320 313 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6) 321 314 #define cpu_has_mips_4_5_64_r2_r6 \ 322 315 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \ 323 - cpu_has_mips_r2 | cpu_has_mips_r6) 316 + cpu_has_mips_r2 | cpu_has_mips_r5 | \ 317 + cpu_has_mips_r6) 324 318 325 - #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6) 326 - #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6) 319 + #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 320 + cpu_has_mips32r5 | cpu_has_mips32r6) 321 + #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | \ 322 + cpu_has_mips64r5 | cpu_has_mips64r6) 327 323 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 328 324 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 325 + #define cpu_has_mips_r5 (cpu_has_mips32r5 | cpu_has_mips64r5) 329 326 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6) 330 327 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 331 - cpu_has_mips32r6 | cpu_has_mips64r1 | \ 332 - cpu_has_mips64r2 | cpu_has_mips64r6) 328 + cpu_has_mips32r5 | cpu_has_mips32r6 | \ 329 + cpu_has_mips64r1 | cpu_has_mips64r2 | \ 330 + cpu_has_mips64r5 | cpu_has_mips64r6) 333 331 334 - /* MIPSR2 and MIPSR6 have a lot of similarities */ 335 - #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6) 332 + /* MIPSR2 - MIPSR6 have a lot of similarities */ 333 + #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r5 | \ 334 + cpu_has_mips_r6) 336 335 337 336 /* 338 337 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
+1 -1
arch/mips/include/asm/cpu-info.h
··· 142 142 static inline unsigned int cpu_cluster(struct cpuinfo_mips *cpuinfo) 143 143 { 144 144 /* Optimisation for systems where multiple clusters aren't used */ 145 - if (!IS_ENABLED(CONFIG_CPU_MIPSR6)) 145 + if (!IS_ENABLED(CONFIG_CPU_MIPSR5) && !IS_ENABLED(CONFIG_CPU_MIPSR6)) 146 146 return 0; 147 147 148 148 return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CLUSTER) >>
+6 -1
arch/mips/include/asm/cpu-type.h
··· 51 51 case CPU_M14KEC: 52 52 case CPU_INTERAPTIV: 53 53 case CPU_PROAPTIV: 54 - case CPU_P5600: 54 + #endif 55 + 56 + #ifdef CONFIG_SYS_HAS_CPU_MIPS32_R5 55 57 case CPU_M5150: 58 + case CPU_P5600: 56 59 #endif 57 60 58 61 #if defined(CONFIG_SYS_HAS_CPU_MIPS32_R2) || \ 62 + defined(CONFIG_SYS_HAS_CPU_MIPS32_R5) || \ 59 63 defined(CONFIG_SYS_HAS_CPU_MIPS32_R6) || \ 60 64 defined(CONFIG_SYS_HAS_CPU_MIPS64_R2) || \ 65 + defined(CONFIG_SYS_HAS_CPU_MIPS64_R5) || \ 61 66 defined(CONFIG_SYS_HAS_CPU_MIPS64_R6) 62 67 case CPU_QEMU_GENERIC: 63 68 #endif
+6 -4
arch/mips/include/asm/cpu.h
··· 347 347 #define MIPS_CPU_ISA_M32R2 0x00000020 348 348 #define MIPS_CPU_ISA_M64R1 0x00000040 349 349 #define MIPS_CPU_ISA_M64R2 0x00000080 350 - #define MIPS_CPU_ISA_M32R6 0x00000100 351 - #define MIPS_CPU_ISA_M64R6 0x00000200 350 + #define MIPS_CPU_ISA_M32R5 0x00000100 351 + #define MIPS_CPU_ISA_M64R5 0x00000200 352 + #define MIPS_CPU_ISA_M32R6 0x00000400 353 + #define MIPS_CPU_ISA_M64R6 0x00000800 352 354 353 355 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \ 354 - MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6) 356 + MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M32R6) 355 357 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 356 358 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \ 357 - MIPS_CPU_ISA_M64R6) 359 + MIPS_CPU_ISA_M64R5 | MIPS_CPU_ISA_M64R6) 358 360 359 361 /* 360 362 * CPU Option encodings
+2 -2
arch/mips/include/asm/fpu.h
··· 71 71 goto fr_common; 72 72 73 73 case FPU_64BIT: 74 - #if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \ 75 - || defined(CONFIG_64BIT)) 74 + #if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \ 75 + defined(CONFIG_CPU_MIPSR6) || defined(CONFIG_64BIT)) 76 76 /* we only have a 32-bit FPU */ 77 77 return SIGFPE; 78 78 #endif
+5 -3
arch/mips/include/asm/hazards.h
··· 22 22 /* 23 23 * TLB hazards 24 24 */ 25 - #if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \ 26 - !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64) 25 + #if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \ 26 + defined(CONFIG_CPU_MIPSR6)) && \ 27 + !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64) 27 28 28 29 /* 29 30 * MIPSR2 defines ehb for hazard avoidance ··· 279 278 280 279 #define __disable_fpu_hazard 281 280 282 - #elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) 281 + #elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \ 282 + defined(CONFIG_CPU_MIPSR6) 283 283 284 284 #define __enable_fpu_hazard \ 285 285 ___ehb
+4
arch/mips/include/asm/module.h
··· 89 89 #define MODULE_PROC_FAMILY "MIPS32_R1 " 90 90 #elif defined CONFIG_CPU_MIPS32_R2 91 91 #define MODULE_PROC_FAMILY "MIPS32_R2 " 92 + #elif defined CONFIG_CPU_MIPS32_R5 93 + #define MODULE_PROC_FAMILY "MIPS32_R5 " 92 94 #elif defined CONFIG_CPU_MIPS32_R6 93 95 #define MODULE_PROC_FAMILY "MIPS32_R6 " 94 96 #elif defined CONFIG_CPU_MIPS64_R1 95 97 #define MODULE_PROC_FAMILY "MIPS64_R1 " 96 98 #elif defined CONFIG_CPU_MIPS64_R2 97 99 #define MODULE_PROC_FAMILY "MIPS64_R2 " 100 + #elif defined CONFIG_CPU_MIPS64_R5 101 + #define MODULE_PROC_FAMILY "MIPS64_R5 " 98 102 #elif defined CONFIG_CPU_MIPS64_R6 99 103 #define MODULE_PROC_FAMILY "MIPS64_R6 " 100 104 #elif defined CONFIG_CPU_R3000
+1 -1
arch/mips/include/asm/stackframe.h
··· 424 424 425 425 .macro RESTORE_SP_AND_RET docfi=0 426 426 RESTORE_SP \docfi 427 - #ifdef CONFIG_CPU_MIPSR6 427 + #if defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6) 428 428 eretnc 429 429 #else 430 430 .set push
+4 -4
arch/mips/include/asm/switch_to.h
··· 67 67 #endif 68 68 69 69 /* 70 - * Clear LLBit during context switches on MIPSr6 such that eretnc can be used 70 + * Clear LLBit during context switches on MIPSr5+ such that eretnc can be used 71 71 * unconditionally when returning to userland in entry.S. 72 72 */ 73 - #define __clear_r6_hw_ll_bit() do { \ 74 - if (cpu_has_mips_r6) \ 73 + #define __clear_r5_hw_ll_bit() do { \ 74 + if (cpu_has_mips_r5 || cpu_has_mips_r6) \ 75 75 write_c0_lladdr(0); \ 76 76 } while (0) 77 77 ··· 129 129 } \ 130 130 clear_c0_status(ST0_CU2); \ 131 131 } \ 132 - __clear_r6_hw_ll_bit(); \ 132 + __clear_r5_hw_ll_bit(); \ 133 133 __clear_software_ll_bit(); \ 134 134 if (cpu_has_userlocal) \ 135 135 write_c0_userlocal(task_thread_info(next)->tp_value); \
+17
arch/mips/kernel/cpu-probe.c
··· 92 92 { 93 93 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 94 94 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 95 + MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 | 95 96 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 96 97 unsigned long sr, fir, fcsr, fcsr0, fcsr1; 97 98 ··· 173 172 case STRICT: 174 173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 175 174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 175 + MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 | 176 176 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 177 177 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; 178 178 } else { ··· 265 263 value = 0; 266 264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 267 265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 266 + MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 | 268 267 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 269 268 value |= MIPS_FPIR_D | MIPS_FPIR_S; 270 269 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 270 + MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 | 271 271 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 272 272 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; 273 273 if (c->options & MIPS_CPU_NAN_2008) ··· 290 286 291 287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 292 288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 289 + MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 | 293 290 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 294 291 if (c->fpu_id & MIPS_FPIR_3D) 295 292 c->ases |= MIPS_ASE_MIPS3D; ··· 537 532 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 538 533 { 539 534 switch (isa) { 535 + case MIPS_CPU_ISA_M64R5: 536 + c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5; 537 + set_elf_base_platform("mips64r5"); 538 + fallthrough; 540 539 case MIPS_CPU_ISA_M64R2: 541 540 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 542 541 set_elf_base_platform("mips64r2"); ··· 572 563 set_elf_base_platform("mips32r6"); 573 564 /* Break here so we don't add incompatible ISAs */ 574 565 break; 566 + case MIPS_CPU_ISA_M32R5: 567 + c->isa_level |= MIPS_CPU_ISA_M32R5; 568 + set_elf_base_platform("mips32r5"); 569 + fallthrough; 575 570 case MIPS_CPU_ISA_M32R2: 576 571 c->isa_level |= MIPS_CPU_ISA_M32R2; 577 572 set_elf_base_platform("mips32r2"); ··· 1764 1751 spram_config(); 1765 1752 1766 1753 switch (__get_cpu_type(c->cputype)) { 1754 + case CPU_M5150: 1755 + case CPU_P5600: 1756 + set_isa(c, MIPS_CPU_ISA_M32R5); 1757 + break; 1767 1758 case CPU_I6500: 1768 1759 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES; 1769 1760 fallthrough;
+3 -3
arch/mips/kernel/entry.S
··· 169 169 jal syscall_trace_leave 170 170 b resume_userspace 171 171 172 - #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) || \ 173 - defined(CONFIG_MIPS_MT) 172 + #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \ 173 + defined(CONFIG_CPU_MIPSR6) || defined(CONFIG_MIPS_MT) 174 174 175 175 /* 176 176 * MIPS32R2 Instruction Hazard Barrier - must be called ··· 183 183 nop 184 184 END(mips_ihb) 185 185 186 - #endif /* CONFIG_CPU_MIPSR2 or CONFIG_CPU_MIPSR6 or CONFIG_MIPS_MT */ 186 + #endif /* CONFIG_CPU_MIPSR2 - CONFIG_CPU_MIPSR6 or CONFIG_MIPS_MT */
+4
arch/mips/kernel/proc.c
··· 98 98 seq_printf(m, "%s", " mips32r1"); 99 99 if (cpu_has_mips32r2) 100 100 seq_printf(m, "%s", " mips32r2"); 101 + if (cpu_has_mips32r5) 102 + seq_printf(m, "%s", " mips32r5"); 101 103 if (cpu_has_mips32r6) 102 104 seq_printf(m, "%s", " mips32r6"); 103 105 if (cpu_has_mips64r1) 104 106 seq_printf(m, "%s", " mips64r1"); 105 107 if (cpu_has_mips64r2) 106 108 seq_printf(m, "%s", " mips64r2"); 109 + if (cpu_has_mips64r5) 110 + seq_printf(m, "%s", " mips64r5"); 107 111 if (cpu_has_mips64r6) 108 112 seq_printf(m, "%s", " mips64r6"); 109 113 seq_printf(m, "\n");
+7 -7
arch/mips/kernel/r4k_fpu.S
··· 41 41 LEAF(_save_fp) 42 42 EXPORT_SYMBOL(_save_fp) 43 43 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ 44 - defined(CONFIG_CPU_MIPSR6) 44 + defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6) 45 45 mfc0 t0, CP0_STATUS 46 46 #endif 47 47 fpu_save_double a0 t0 t1 # clobbers t1 ··· 53 53 */ 54 54 LEAF(_restore_fp) 55 55 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ 56 - defined(CONFIG_CPU_MIPSR6) 56 + defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6) 57 57 mfc0 t0, CP0_STATUS 58 58 #endif 59 59 fpu_restore_double a0 t0 t1 # clobbers t1 ··· 103 103 .set pop 104 104 105 105 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ 106 - defined(CONFIG_CPU_MIPSR6) 106 + defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6) 107 107 .set push 108 108 SET_HARDFLOAT 109 - #ifdef CONFIG_CPU_MIPSR2 109 + #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) 110 110 .set mips32r2 111 111 .set fp=64 112 112 mfc0 t0, CP0_STATUS ··· 170 170 LEAF(_restore_fp_context) 171 171 EX lw t1, 0(a1) 172 172 173 - #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ 174 - defined(CONFIG_CPU_MIPSR6) 173 + #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ 174 + defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6) 175 175 .set push 176 176 SET_HARDFLOAT 177 - #ifdef CONFIG_CPU_MIPSR2 177 + #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) 178 178 .set mips32r2 179 179 .set fp=64 180 180 mfc0 t0, CP0_STATUS
+3 -3
arch/mips/kvm/vz.c
··· 2980 2980 */ 2981 2981 2982 2982 /* PageGrain */ 2983 - if (cpu_has_mips_r6) 2983 + if (cpu_has_mips_r5 || cpu_has_mips_r6) 2984 2984 kvm_write_sw_gc0_pagegrain(cop0, PG_RIE | PG_XIE | PG_IEC); 2985 2985 /* Wired */ 2986 2986 if (cpu_has_mips_r6) ··· 2988 2988 read_gc0_wired() & MIPSR6_WIRED_LIMIT); 2989 2989 /* Status */ 2990 2990 kvm_write_sw_gc0_status(cop0, ST0_BEV | ST0_ERL); 2991 - if (cpu_has_mips_r6) 2991 + if (cpu_has_mips_r5 || cpu_has_mips_r6) 2992 2992 kvm_change_sw_gc0_status(cop0, ST0_FR, read_gc0_status()); 2993 2993 /* IntCtl */ 2994 2994 kvm_write_sw_gc0_intctl(cop0, read_gc0_intctl() & ··· 3086 3086 } 3087 3087 3088 3088 /* reset HTW registers */ 3089 - if (cpu_guest_has_htw && cpu_has_mips_r6) { 3089 + if (cpu_guest_has_htw && (cpu_has_mips_r5 || cpu_has_mips_r6)) { 3090 3090 /* PWField */ 3091 3091 kvm_write_sw_gc0_pwfield(cop0, 0x0c30c302); 3092 3092 /* PWSize */
+4 -2
arch/mips/lib/csum_partial.S
··· 279 279 #endif 280 280 281 281 /* odd buffer alignment? */ 282 - #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON64) 282 + #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \ 283 + defined(CONFIG_CPU_LOONGSON64) 283 284 .set push 284 285 .set arch=mips32r2 285 286 wsbh v1, sum ··· 733 732 addu sum, v1 734 733 #endif 735 734 736 - #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON64) 735 + #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \ 736 + defined(CONFIG_CPU_LOONGSON64) 737 737 .set push 738 738 .set arch=mips32r2 739 739 wsbh v1, sum
+4 -3
arch/mips/mm/c-r4k.c
··· 1709 1709 return; 1710 1710 1711 1711 default: 1712 - if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | 1713 - MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 | 1714 - MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) { 1712 + if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 1713 + MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 1714 + MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 | 1715 + MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 1715 1716 #ifdef CONFIG_MIPS_CPU_SCACHE 1716 1717 if (mips_sc_init ()) { 1717 1718 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
+4 -3
arch/mips/mm/sc-mips.c
··· 194 194 return mips_sc_probe_cm3(); 195 195 196 196 /* Ignore anything but MIPSxx processors */ 197 - if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | 198 - MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 | 199 - MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6))) 197 + if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 198 + MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 199 + MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 | 200 + MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))) 200 201 return 0; 201 202 202 203 /* Does this MIPS32/MIPS64 CPU have a config2 register? */