Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/powerplay: use smu7 hwmgr to manager iceland

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rex Zhu and committed by
Alex Deucher
ab4f06d3 18aafc59

+27 -10
+1 -3
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
··· 7 7 cz_clockpowergating.o pppcielanes.o\ 8 8 process_pptables_v1_0.o ppatomctrl.o \ 9 9 smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \ 10 - smu7_clockpowergating.o iceland_hwmgr.o \ 11 - iceland_clockpowergating.o iceland_thermal.o \ 12 - iceland_powertune.o 10 + smu7_clockpowergating.o 13 11 14 12 15 13 AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
+26 -7
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
··· 36 36 #include "amd_acpi.h" 37 37 38 38 extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr); 39 - extern int iceland_hwmgr_init(struct pp_hwmgr *hwmgr); 40 39 41 40 static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr); 42 41 static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr); 43 42 static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr); 44 43 static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr); 45 44 static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr); 45 + static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr); 46 46 47 47 uint8_t convert_to_vid(uint16_t vddc) 48 48 { ··· 79 79 case AMDGPU_FAMILY_VI: 80 80 switch (hwmgr->chip_id) { 81 81 case CHIP_TOPAZ: 82 - iceland_hwmgr_init(hwmgr); 82 + topaz_set_asic_special_caps(hwmgr); 83 + hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | 84 + PP_VBI_TIME_SUPPORT_MASK | 85 + PP_ENABLE_GFX_CG_THRU_SMU); 86 + hwmgr->pp_table_version = PP_TABLE_V0; 83 87 break; 84 88 case CHIP_TONGA: 85 - smu7_hwmgr_init(hwmgr); 86 89 tonga_set_asic_special_caps(hwmgr); 87 90 hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | 88 91 PP_VBI_TIME_SUPPORT_MASK); 89 92 break; 90 93 case CHIP_FIJI: 91 - smu7_hwmgr_init(hwmgr); 92 94 fiji_set_asic_special_caps(hwmgr); 93 95 hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | 94 96 PP_VBI_TIME_SUPPORT_MASK | ··· 98 96 break; 99 97 case CHIP_POLARIS11: 100 98 case CHIP_POLARIS10: 101 - smu7_hwmgr_init(hwmgr); 102 99 polaris_set_asic_special_caps(hwmgr); 103 100 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); 104 101 break; 105 102 default: 106 103 return -EINVAL; 107 104 } 105 + smu7_hwmgr_init(hwmgr); 108 106 break; 109 107 default: 110 108 return -EINVAL; ··· 215 213 return -1; 216 214 return 0; 217 215 } 218 - 219 - 220 216 221 217 222 218 /** ··· 792 792 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 793 793 PHM_PlatformCaps_CAC); 794 794 795 + return 0; 796 + } 797 + 798 + int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr) 799 + { 800 + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 801 + PHM_PlatformCaps_SQRamping); 802 + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 803 + PHM_PlatformCaps_DBRamping); 804 + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 805 + PHM_PlatformCaps_TDRamping); 806 + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 807 + PHM_PlatformCaps_TCPRamping); 808 + phm_cap_set(hwmgr->platform_descriptor.platformCaps, 809 + PHM_PlatformCaps_TablelessHardwareInterface); 810 + phm_cap_set(hwmgr->platform_descriptor.platformCaps, 811 + PHM_PlatformCaps_CAC); 812 + phm_cap_set(hwmgr->platform_descriptor.platformCaps, 813 + PHM_PlatformCaps_EVV); 795 814 return 0; 796 815 }