pinctrl: realtek: Add pinctrl driver for RTD1315E

+5

drivers/pinctrl/realtek/Kconfig

··· 6 6 default y 7 7 select PINMUX 8 8 select GENERIC_PINCONF 9 + 10 + config PINCTRL_RTD1315E 11 + tristate "Realtek DHC 1315E pin controller driver" 12 + depends on PINCTRL_RTD 13 + default y

+1

drivers/pinctrl/realtek/Makefile

··· 1 1 # SPDX-License-Identifier: GPL-2.0-or-later 2 2 # Realtek DHC pin control drivers 3 3 obj-$(CONFIG_PINCTRL_RTD) += pinctrl-rtd.o 4 + obj-$(CONFIG_PINCTRL_RTD1315E) += pinctrl-rtd1315e.o

+1439

drivers/pinctrl/realtek/pinctrl-rtd1315e.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later 2 + /* 3 + * Realtek DHC 1315E pin controller driver 4 + * 5 + * Copyright (c) 2023 Realtek Semiconductor Corp. 6 + * 7 + */ 8 + 9 + #include <linux/module.h> 10 + #include <linux/of.h> 11 + #include <linux/platform_device.h> 12 + #include <linux/pinctrl/pinctrl.h> 13 + 14 + #include "pinctrl-rtd.h" 15 + 16 + enum rtd13xxe_iso_pins { 17 + RTD1315E_ISO_GPIO_0 = 0, 18 + RTD1315E_ISO_GPIO_1, 19 + RTD1315E_ISO_EMMC_RST_N, 20 + RTD1315E_ISO_EMMC_DD_SB, 21 + RTD1315E_ISO_EMMC_CLK, 22 + RTD1315E_ISO_EMMC_CMD, 23 + RTD1315E_ISO_GPIO_6, 24 + RTD1315E_ISO_GPIO_7, 25 + RTD1315E_ISO_GPIO_8, 26 + RTD1315E_ISO_GPIO_9, 27 + RTD1315E_ISO_GPIO_10, 28 + RTD1315E_ISO_GPIO_11, 29 + RTD1315E_ISO_GPIO_12, 30 + RTD1315E_ISO_GPIO_13, 31 + RTD1315E_ISO_GPIO_14, 32 + RTD1315E_ISO_GPIO_15, 33 + RTD1315E_ISO_GPIO_16, 34 + RTD1315E_ISO_GPIO_17, 35 + RTD1315E_ISO_GPIO_18, 36 + RTD1315E_ISO_GPIO_19, 37 + RTD1315E_ISO_GPIO_20, 38 + RTD1315E_ISO_EMMC_DATA_0, 39 + RTD1315E_ISO_EMMC_DATA_1, 40 + RTD1315E_ISO_EMMC_DATA_2, 41 + RTD1315E_ISO_USB_CC2, 42 + RTD1315E_ISO_GPIO_25, 43 + RTD1315E_ISO_GPIO_26, 44 + RTD1315E_ISO_GPIO_27, 45 + RTD1315E_ISO_GPIO_28, 46 + RTD1315E_ISO_GPIO_29, 47 + RTD1315E_ISO_GPIO_30, 48 + RTD1315E_ISO_GPIO_31, 49 + RTD1315E_ISO_GPIO_32, 50 + RTD1315E_ISO_GPIO_33, 51 + RTD1315E_ISO_GPIO_34, 52 + RTD1315E_ISO_GPIO_35, 53 + RTD1315E_ISO_HIF_DATA, 54 + RTD1315E_ISO_HIF_EN, 55 + RTD1315E_ISO_HIF_RDY, 56 + RTD1315E_ISO_HIF_CLK, 57 + RTD1315E_ISO_GPIO_DUMMY_40, 58 + RTD1315E_ISO_GPIO_DUMMY_41, 59 + RTD1315E_ISO_GPIO_DUMMY_42, 60 + RTD1315E_ISO_GPIO_DUMMY_43, 61 + RTD1315E_ISO_GPIO_DUMMY_44, 62 + RTD1315E_ISO_GPIO_DUMMY_45, 63 + RTD1315E_ISO_GPIO_46, 64 + RTD1315E_ISO_GPIO_47, 65 + RTD1315E_ISO_GPIO_48, 66 + RTD1315E_ISO_GPIO_49, 67 + RTD1315E_ISO_GPIO_50, 68 + RTD1315E_ISO_USB_CC1, 69 + RTD1315E_ISO_EMMC_DATA_3, 70 + RTD1315E_ISO_EMMC_DATA_4, 71 + RTD1315E_ISO_IR_RX, 72 + RTD1315E_ISO_UR0_RX, 73 + RTD1315E_ISO_UR0_TX, 74 + RTD1315E_ISO_GPIO_57, 75 + RTD1315E_ISO_GPIO_58, 76 + RTD1315E_ISO_GPIO_59, 77 + RTD1315E_ISO_GPIO_60, 78 + RTD1315E_ISO_GPIO_61, 79 + RTD1315E_ISO_GPIO_62, 80 + RTD1315E_ISO_GPIO_DUMMY_63, 81 + RTD1315E_ISO_GPIO_DUMMY_64, 82 + RTD1315E_ISO_GPIO_DUMMY_65, 83 + RTD1315E_ISO_GPIO_66, 84 + RTD1315E_ISO_GPIO_67, 85 + RTD1315E_ISO_GPIO_68, 86 + RTD1315E_ISO_GPIO_69, 87 + RTD1315E_ISO_GPIO_70, 88 + RTD1315E_ISO_GPIO_71, 89 + RTD1315E_ISO_GPIO_72, 90 + RTD1315E_ISO_GPIO_DUMMY_73, 91 + RTD1315E_ISO_EMMC_DATA_5, 92 + RTD1315E_ISO_EMMC_DATA_6, 93 + RTD1315E_ISO_EMMC_DATA_7, 94 + RTD1315E_ISO_GPIO_DUMMY_77, 95 + RTD1315E_ISO_GPIO_78, 96 + RTD1315E_ISO_GPIO_79, 97 + RTD1315E_ISO_GPIO_80, 98 + RTD1315E_ISO_GPIO_81, 99 + RTD1315E_ISO_UR2_LOC, 100 + RTD1315E_ISO_GSPI_LOC, 101 + RTD1315E_ISO_HI_WIDTH, 102 + RTD1315E_ISO_SF_EN, 103 + RTD1315E_ISO_ARM_TRACE_DBG_EN, 104 + RTD1315E_ISO_EJTAG_AUCPU_LOC, 105 + RTD1315E_ISO_EJTAG_ACPU_LOC, 106 + RTD1315E_ISO_EJTAG_VCPU_LOC, 107 + RTD1315E_ISO_EJTAG_SCPU_LOC, 108 + RTD1315E_ISO_DMIC_LOC, 109 + RTD1315E_ISO_VTC_DMIC_LOC, 110 + RTD1315E_ISO_VTC_TDM_LOC, 111 + RTD1315E_ISO_VTC_I2SI_LOC, 112 + RTD1315E_ISO_TDM_AI_LOC, 113 + RTD1315E_ISO_AI_LOC, 114 + RTD1315E_ISO_SPDIF_LOC, 115 + RTD1315E_ISO_HIF_EN_LOC, 116 + RTD1315E_ISO_SCAN_SWITCH, 117 + RTD1315E_ISO_WD_RSET, 118 + RTD1315E_ISO_BOOT_SEL, 119 + RTD1315E_ISO_RESET_N, 120 + RTD1315E_ISO_TESTMODE, 121 + }; 122 + 123 + static const struct pinctrl_pin_desc rtd1315e_iso_pins[] = { 124 + PINCTRL_PIN(RTD1315E_ISO_GPIO_0, "gpio_0"), 125 + PINCTRL_PIN(RTD1315E_ISO_GPIO_1, "gpio_1"), 126 + PINCTRL_PIN(RTD1315E_ISO_EMMC_RST_N, "emmc_rst_n"), 127 + PINCTRL_PIN(RTD1315E_ISO_EMMC_DD_SB, "emmc_dd_sb"), 128 + PINCTRL_PIN(RTD1315E_ISO_EMMC_CLK, "emmc_clk"), 129 + PINCTRL_PIN(RTD1315E_ISO_EMMC_CMD, "emmc_cmd"), 130 + PINCTRL_PIN(RTD1315E_ISO_GPIO_6, "gpio_6"), 131 + PINCTRL_PIN(RTD1315E_ISO_GPIO_7, "gpio_7"), 132 + PINCTRL_PIN(RTD1315E_ISO_GPIO_8, "gpio_8"), 133 + PINCTRL_PIN(RTD1315E_ISO_GPIO_9, "gpio_9"), 134 + PINCTRL_PIN(RTD1315E_ISO_GPIO_10, "gpio_10"), 135 + PINCTRL_PIN(RTD1315E_ISO_GPIO_11, "gpio_11"), 136 + PINCTRL_PIN(RTD1315E_ISO_GPIO_12, "gpio_12"), 137 + PINCTRL_PIN(RTD1315E_ISO_GPIO_13, "gpio_13"), 138 + PINCTRL_PIN(RTD1315E_ISO_GPIO_14, "gpio_14"), 139 + PINCTRL_PIN(RTD1315E_ISO_GPIO_15, "gpio_15"), 140 + PINCTRL_PIN(RTD1315E_ISO_GPIO_16, "gpio_16"), 141 + PINCTRL_PIN(RTD1315E_ISO_GPIO_17, "gpio_17"), 142 + PINCTRL_PIN(RTD1315E_ISO_GPIO_18, "gpio_18"), 143 + PINCTRL_PIN(RTD1315E_ISO_GPIO_19, "gpio_19"), 144 + PINCTRL_PIN(RTD1315E_ISO_GPIO_20, "gpio_20"), 145 + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_0, "emmc_data_0"), 146 + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_1, "emmc_data_1"), 147 + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_2, "emmc_data_2"), 148 + PINCTRL_PIN(RTD1315E_ISO_USB_CC2, "usb_cc2"), 149 + PINCTRL_PIN(RTD1315E_ISO_GPIO_25, "gpio_25"), 150 + PINCTRL_PIN(RTD1315E_ISO_GPIO_26, "gpio_26"), 151 + PINCTRL_PIN(RTD1315E_ISO_GPIO_27, "gpio_27"), 152 + PINCTRL_PIN(RTD1315E_ISO_GPIO_28, "gpio_28"), 153 + PINCTRL_PIN(RTD1315E_ISO_GPIO_29, "gpio_29"), 154 + PINCTRL_PIN(RTD1315E_ISO_GPIO_30, "gpio_30"), 155 + PINCTRL_PIN(RTD1315E_ISO_GPIO_31, "gpio_31"), 156 + PINCTRL_PIN(RTD1315E_ISO_GPIO_32, "gpio_32"), 157 + PINCTRL_PIN(RTD1315E_ISO_GPIO_33, "gpio_33"), 158 + PINCTRL_PIN(RTD1315E_ISO_GPIO_34, "gpio_34"), 159 + PINCTRL_PIN(RTD1315E_ISO_GPIO_35, "gpio_35"), 160 + PINCTRL_PIN(RTD1315E_ISO_HIF_DATA, "hif_data"), 161 + PINCTRL_PIN(RTD1315E_ISO_HIF_EN, "hif_en"), 162 + PINCTRL_PIN(RTD1315E_ISO_HIF_RDY, "hif_rdy"), 163 + PINCTRL_PIN(RTD1315E_ISO_HIF_CLK, "hif_clk"), 164 + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_40, "gpio_dummy_40"), 165 + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_41, "gpio_dummy_41"), 166 + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_42, "gpio_dummy_42"), 167 + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_43, "gpio_dummy_43"), 168 + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_44, "gpio_dummy_44"), 169 + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_45, "gpio_dummy_45"), 170 + PINCTRL_PIN(RTD1315E_ISO_GPIO_46, "gpio_46"), 171 + PINCTRL_PIN(RTD1315E_ISO_GPIO_47, "gpio_47"), 172 + PINCTRL_PIN(RTD1315E_ISO_GPIO_48, "gpio_48"), 173 + PINCTRL_PIN(RTD1315E_ISO_GPIO_49, "gpio_49"), 174 + PINCTRL_PIN(RTD1315E_ISO_GPIO_50, "gpio_50"), 175 + PINCTRL_PIN(RTD1315E_ISO_USB_CC1, "usb_cc1"), 176 + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_3, "emmc_data_3"), 177 + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_4, "emmc_data_4"), 178 + PINCTRL_PIN(RTD1315E_ISO_IR_RX, "ir_rx"), 179 + PINCTRL_PIN(RTD1315E_ISO_UR0_RX, "ur0_rx"), 180 + PINCTRL_PIN(RTD1315E_ISO_UR0_TX, "ur0_tx"), 181 + PINCTRL_PIN(RTD1315E_ISO_GPIO_57, "gpio_57"), 182 + PINCTRL_PIN(RTD1315E_ISO_GPIO_58, "gpio_58"), 183 + PINCTRL_PIN(RTD1315E_ISO_GPIO_59, "gpio_59"), 184 + PINCTRL_PIN(RTD1315E_ISO_GPIO_60, "gpio_60"), 185 + PINCTRL_PIN(RTD1315E_ISO_GPIO_61, "gpio_61"), 186 + PINCTRL_PIN(RTD1315E_ISO_GPIO_62, "gpio_62"), 187 + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_63, "gpio_dummy_63"), 188 + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_64, "gpio_dummy_64"), 189 + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_65, "gpio_dummy_65"), 190 + PINCTRL_PIN(RTD1315E_ISO_GPIO_66, "gpio_66"), 191 + PINCTRL_PIN(RTD1315E_ISO_GPIO_67, "gpio_67"), 192 + PINCTRL_PIN(RTD1315E_ISO_GPIO_68, "gpio_68"), 193 + PINCTRL_PIN(RTD1315E_ISO_GPIO_69, "gpio_69"), 194 + PINCTRL_PIN(RTD1315E_ISO_GPIO_70, "gpio_70"), 195 + PINCTRL_PIN(RTD1315E_ISO_GPIO_71, "gpio_71"), 196 + PINCTRL_PIN(RTD1315E_ISO_GPIO_72, "gpio_72"), 197 + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_73, "gpio_dummy_73"), 198 + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_5, "emmc_data_5"), 199 + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_6, "emmc_data_6"), 200 + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_7, "emmc_data_7"), 201 + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_77, "gpio_dummy_77"), 202 + PINCTRL_PIN(RTD1315E_ISO_GPIO_78, "gpio_78"), 203 + PINCTRL_PIN(RTD1315E_ISO_GPIO_79, "gpio_79"), 204 + PINCTRL_PIN(RTD1315E_ISO_GPIO_80, "gpio_80"), 205 + PINCTRL_PIN(RTD1315E_ISO_GPIO_81, "gpio_81"), 206 + PINCTRL_PIN(RTD1315E_ISO_UR2_LOC, "ur2_loc"), 207 + PINCTRL_PIN(RTD1315E_ISO_GSPI_LOC, "gspi_loc"), 208 + PINCTRL_PIN(RTD1315E_ISO_HI_WIDTH, "hi_width"), 209 + PINCTRL_PIN(RTD1315E_ISO_SF_EN, "sf_en"), 210 + PINCTRL_PIN(RTD1315E_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"), 211 + PINCTRL_PIN(RTD1315E_ISO_EJTAG_AUCPU_LOC, "ejtag_aucpu_loc"), 212 + PINCTRL_PIN(RTD1315E_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"), 213 + PINCTRL_PIN(RTD1315E_ISO_EJTAG_VCPU_LOC, "ejtag_vcpu_loc"), 214 + PINCTRL_PIN(RTD1315E_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"), 215 + PINCTRL_PIN(RTD1315E_ISO_DMIC_LOC, "dmic_loc"), 216 + PINCTRL_PIN(RTD1315E_ISO_VTC_DMIC_LOC, "vtc_dmic_loc"), 217 + PINCTRL_PIN(RTD1315E_ISO_VTC_TDM_LOC, "vtc_tdm_loc"), 218 + PINCTRL_PIN(RTD1315E_ISO_VTC_I2SI_LOC, "vtc_i2si_loc"), 219 + PINCTRL_PIN(RTD1315E_ISO_TDM_AI_LOC, "tdm_ai_loc"), 220 + PINCTRL_PIN(RTD1315E_ISO_AI_LOC, "ai_loc"), 221 + PINCTRL_PIN(RTD1315E_ISO_SPDIF_LOC, "spdif_loc"), 222 + PINCTRL_PIN(RTD1315E_ISO_HIF_EN_LOC, "hif_en_loc"), 223 + PINCTRL_PIN(RTD1315E_ISO_SCAN_SWITCH, "scan_switch"), 224 + PINCTRL_PIN(RTD1315E_ISO_WD_RSET, "wd_rset"), 225 + PINCTRL_PIN(RTD1315E_ISO_BOOT_SEL, "boot_sel"), 226 + PINCTRL_PIN(RTD1315E_ISO_RESET_N, "reset_n"), 227 + PINCTRL_PIN(RTD1315E_ISO_TESTMODE, "testmode"), 228 + }; 229 + 230 + #define DECLARE_RTD1315E_PIN(_pin, _name) \ 231 + static const unsigned int rtd1315e_## _name ##_pins[] = { _pin } 232 + 233 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_0, gpio_0); 234 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_1, gpio_1); 235 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_RST_N, emmc_rst_n); 236 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DD_SB, emmc_dd_sb); 237 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_CLK, emmc_clk); 238 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_CMD, emmc_cmd); 239 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_6, gpio_6); 240 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_7, gpio_7); 241 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_8, gpio_8); 242 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_9, gpio_9); 243 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_10, gpio_10); 244 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_11, gpio_11); 245 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_12, gpio_12); 246 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_13, gpio_13); 247 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_14, gpio_14); 248 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_15, gpio_15); 249 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_16, gpio_16); 250 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_17, gpio_17); 251 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_18, gpio_18); 252 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_19, gpio_19); 253 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_20, gpio_20); 254 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_0, emmc_data_0); 255 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_1, emmc_data_1); 256 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_2, emmc_data_2); 257 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_USB_CC2, usb_cc2); 258 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_25, gpio_25); 259 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_26, gpio_26); 260 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_27, gpio_27); 261 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_28, gpio_28); 262 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_29, gpio_29); 263 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_30, gpio_30); 264 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_31, gpio_31); 265 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_32, gpio_32); 266 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_33, gpio_33); 267 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_34, gpio_34); 268 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_35, gpio_35); 269 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_DATA, hif_data); 270 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_EN, hif_en); 271 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_RDY, hif_rdy); 272 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_CLK, hif_clk); 273 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_40, gpio_dummy_40); 274 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_41, gpio_dummy_41); 275 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_42, gpio_dummy_42); 276 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_43, gpio_dummy_43); 277 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_44, gpio_dummy_44); 278 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_45, gpio_dummy_45); 279 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_46, gpio_46); 280 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_47, gpio_47); 281 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_48, gpio_48); 282 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_49, gpio_49); 283 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_50, gpio_50); 284 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_USB_CC1, usb_cc1); 285 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_3, emmc_data_3); 286 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_4, emmc_data_4); 287 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_IR_RX, ir_rx); 288 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR0_RX, ur0_rx); 289 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR0_TX, ur0_tx); 290 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_57, gpio_57); 291 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_58, gpio_58); 292 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_59, gpio_59); 293 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_60, gpio_60); 294 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_61, gpio_61); 295 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_62, gpio_62); 296 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_63, gpio_dummy_63); 297 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_64, gpio_dummy_64); 298 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_65, gpio_dummy_65); 299 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_66, gpio_66); 300 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_67, gpio_67); 301 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_68, gpio_68); 302 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_69, gpio_69); 303 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_70, gpio_70); 304 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_71, gpio_71); 305 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_72, gpio_72); 306 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_73, gpio_dummy_73); 307 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_5, emmc_data_5); 308 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_6, emmc_data_6); 309 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_7, emmc_data_7); 310 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_77, gpio_dummy_77); 311 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_78, gpio_78); 312 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_79, gpio_79); 313 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_80, gpio_80); 314 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_81, gpio_81); 315 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR2_LOC, ur2_loc); 316 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_GSPI_LOC, gspi_loc); 317 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_HI_WIDTH, hi_width); 318 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_SF_EN, sf_en); 319 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en); 320 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_AUCPU_LOC, ejtag_aucpu_loc); 321 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc); 322 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_VCPU_LOC, ejtag_vcpu_loc); 323 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc); 324 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_DMIC_LOC, dmic_loc); 325 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_DMIC_LOC, vtc_dmic_loc); 326 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_TDM_LOC, vtc_tdm_loc); 327 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_I2SI_LOC, vtc_i2si_loc); 328 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_TDM_AI_LOC, tdm_ai_loc); 329 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_AI_LOC, ai_loc); 330 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_SPDIF_LOC, spdif_loc); 331 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_EN_LOC, hif_en_loc); 332 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_SCAN_SWITCH, scan_switch); 333 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_WD_RSET, wd_rset); 334 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_BOOT_SEL, boot_sel); 335 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_RESET_N, reset_n); 336 + DECLARE_RTD1315E_PIN(RTD1315E_ISO_TESTMODE, testmode); 337 + 338 + #define RTD1315E_GROUP(_name) \ 339 + { \ 340 + .name = # _name, \ 341 + .pins = rtd1315e_ ## _name ## _pins, \ 342 + .num_pins = ARRAY_SIZE(rtd1315e_ ## _name ## _pins), \ 343 + } 344 + 345 + static const struct rtd_pin_group_desc rtd1315e_pin_groups[] = { 346 + RTD1315E_GROUP(gpio_0), 347 + RTD1315E_GROUP(gpio_1), 348 + RTD1315E_GROUP(emmc_rst_n), 349 + RTD1315E_GROUP(emmc_dd_sb), 350 + RTD1315E_GROUP(emmc_clk), 351 + RTD1315E_GROUP(emmc_cmd), 352 + RTD1315E_GROUP(gpio_6), 353 + RTD1315E_GROUP(gpio_7), 354 + RTD1315E_GROUP(gpio_8), 355 + RTD1315E_GROUP(gpio_9), 356 + RTD1315E_GROUP(gpio_10), 357 + RTD1315E_GROUP(gpio_11), 358 + RTD1315E_GROUP(gpio_12), 359 + RTD1315E_GROUP(gpio_13), 360 + RTD1315E_GROUP(gpio_14), 361 + RTD1315E_GROUP(gpio_15), 362 + RTD1315E_GROUP(gpio_16), 363 + RTD1315E_GROUP(gpio_17), 364 + RTD1315E_GROUP(gpio_18), 365 + RTD1315E_GROUP(gpio_19), 366 + RTD1315E_GROUP(gpio_20), 367 + RTD1315E_GROUP(emmc_data_0), 368 + RTD1315E_GROUP(emmc_data_1), 369 + RTD1315E_GROUP(emmc_data_2), 370 + RTD1315E_GROUP(usb_cc2), 371 + RTD1315E_GROUP(gpio_25), 372 + RTD1315E_GROUP(gpio_26), 373 + RTD1315E_GROUP(gpio_27), 374 + RTD1315E_GROUP(gpio_28), 375 + RTD1315E_GROUP(gpio_29), 376 + RTD1315E_GROUP(gpio_30), 377 + RTD1315E_GROUP(gpio_31), 378 + RTD1315E_GROUP(gpio_32), 379 + RTD1315E_GROUP(gpio_33), 380 + RTD1315E_GROUP(gpio_34), 381 + RTD1315E_GROUP(gpio_35), 382 + RTD1315E_GROUP(hif_data), 383 + RTD1315E_GROUP(hif_en), 384 + RTD1315E_GROUP(hif_rdy), 385 + RTD1315E_GROUP(hif_clk), 386 + RTD1315E_GROUP(gpio_dummy_40), 387 + RTD1315E_GROUP(gpio_dummy_41), 388 + RTD1315E_GROUP(gpio_dummy_42), 389 + RTD1315E_GROUP(gpio_dummy_43), 390 + RTD1315E_GROUP(gpio_dummy_44), 391 + RTD1315E_GROUP(gpio_dummy_45), 392 + RTD1315E_GROUP(gpio_46), 393 + RTD1315E_GROUP(gpio_47), 394 + RTD1315E_GROUP(gpio_48), 395 + RTD1315E_GROUP(gpio_49), 396 + RTD1315E_GROUP(gpio_50), 397 + RTD1315E_GROUP(usb_cc1), 398 + RTD1315E_GROUP(emmc_data_3), 399 + RTD1315E_GROUP(emmc_data_4), 400 + RTD1315E_GROUP(ir_rx), 401 + RTD1315E_GROUP(ur0_rx), 402 + RTD1315E_GROUP(ur0_tx), 403 + RTD1315E_GROUP(gpio_57), 404 + RTD1315E_GROUP(gpio_58), 405 + RTD1315E_GROUP(gpio_59), 406 + RTD1315E_GROUP(gpio_60), 407 + RTD1315E_GROUP(gpio_61), 408 + RTD1315E_GROUP(gpio_62), 409 + RTD1315E_GROUP(gpio_dummy_63), 410 + RTD1315E_GROUP(gpio_dummy_64), 411 + RTD1315E_GROUP(gpio_dummy_65), 412 + RTD1315E_GROUP(gpio_66), 413 + RTD1315E_GROUP(gpio_67), 414 + RTD1315E_GROUP(gpio_68), 415 + RTD1315E_GROUP(gpio_69), 416 + RTD1315E_GROUP(gpio_70), 417 + RTD1315E_GROUP(gpio_71), 418 + RTD1315E_GROUP(gpio_72), 419 + RTD1315E_GROUP(gpio_dummy_73), 420 + RTD1315E_GROUP(emmc_data_5), 421 + RTD1315E_GROUP(emmc_data_6), 422 + RTD1315E_GROUP(emmc_data_7), 423 + RTD1315E_GROUP(gpio_dummy_77), 424 + RTD1315E_GROUP(gpio_78), 425 + RTD1315E_GROUP(gpio_79), 426 + RTD1315E_GROUP(gpio_80), 427 + RTD1315E_GROUP(gpio_81), 428 + RTD1315E_GROUP(ur2_loc), 429 + RTD1315E_GROUP(gspi_loc), 430 + RTD1315E_GROUP(hi_width), 431 + RTD1315E_GROUP(sf_en), 432 + RTD1315E_GROUP(arm_trace_dbg_en), 433 + RTD1315E_GROUP(ejtag_aucpu_loc), 434 + RTD1315E_GROUP(ejtag_acpu_loc), 435 + RTD1315E_GROUP(ejtag_vcpu_loc), 436 + RTD1315E_GROUP(ejtag_scpu_loc), 437 + RTD1315E_GROUP(dmic_loc), 438 + RTD1315E_GROUP(vtc_dmic_loc), 439 + RTD1315E_GROUP(vtc_tdm_loc), 440 + RTD1315E_GROUP(vtc_i2si_loc), 441 + RTD1315E_GROUP(tdm_ai_loc), 442 + RTD1315E_GROUP(ai_loc), 443 + RTD1315E_GROUP(spdif_loc), 444 + RTD1315E_GROUP(hif_en_loc), 445 + 446 + }; 447 + 448 + static const char * const rtd1315e_gpio_groups[] = { 449 + "gpio_0", "gpio_1", "emmc_rst_n", "emmc_dd_sb", "emmc_clk", 450 + "emmc_cmd", "gpio_6", "gpio_7", "gpio_8", "gpio_9", 451 + "gpio_10", "gpio_11", "gpio_12", "gpio_13", "gpio_14", 452 + "gpio_15", "gpio_16", "gpio_17", "gpio_18", "gpio_19", 453 + "gpio_20", "emmc_data_0", "emmc_data_1", "emmc_data_2", "usb_cc2", 454 + "gpio_25", "gpio_26", "gpio_27", "gpio_28", "gpio_29", 455 + "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34", 456 + "gpio_35", "hif_data", "hif_en", "hif_rdy", "hif_clk", 457 + "gpio_46", "gpio_47", "gpio_48", "gpio_49", 458 + "gpio_50", "usb_cc1", "emmc_data_3", "emmc_data_4", "ir_rx", 459 + "ur0_rx", "ur0_tx", "gpio_57", "gpio_58", "gpio_59", 460 + "gpio_60", "gpio_61", "gpio_62", "gpio_66", "gpio_67", 461 + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", 462 + "emmc_data_5", "emmc_data_6", "emmc_data_7", 463 + "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; 464 + static const char * const rtd1315e_nf_groups[] = { 465 + "emmc_rst_n", "emmc_clk", "emmc_cmd", "emmc_data_0", 466 + "emmc_data_1", "emmc_data_2", "emmc_data_3", "emmc_data_4", 467 + "emmc_data_5", "emmc_data_6", "emmc_data_7", 468 + "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; 469 + static const char * const rtd1315e_emmc_groups[] = { 470 + "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd", 471 + "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", 472 + "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7" }; 473 + 474 + static const char * const rtd1315e_ao_groups[] = { 475 + "gpio_66", "gpio_67", "gpio_68", "gpio_69", "gpio_70", 476 + "gpio_71", "gpio_72" }; 477 + static const char * const rtd1315e_gspi_loc0_groups[] = { 478 + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "gspi_loc" }; 479 + static const char * const rtd1315e_gspi_loc1_groups[] = { 480 + "gpio_8", "gpio_9", "gpio_10", "gpio_11", "gspi_loc" }; 481 + static const char * const rtd1315e_uart0_groups[] = { "ur0_rx", "ur0_tx"}; 482 + static const char * const rtd1315e_uart1_groups[] = { 483 + "gpio_8", "gpio_9", "gpio_10", "gpio_11" }; 484 + static const char * const rtd1315e_uart2_loc0_groups[] = { 485 + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "ur2_loc" }; 486 + static const char * const rtd1315e_uart2_loc1_groups[] = { 487 + "gpio_25", "gpio_26", "gpio_27", "gpio_28", "ur2_loc" }; 488 + static const char * const rtd1315e_i2c0_groups[] = { "gpio_12", "gpio_13" }; 489 + static const char * const rtd1315e_i2c1_groups[] = { "gpio_16", "gpio_17" }; 490 + static const char * const rtd1315e_i2c4_groups[] = { "gpio_34", "gpio_35" }; 491 + static const char * const rtd1315e_i2c5_groups[] = { "gpio_29", "gpio_46" }; 492 + static const char * const rtd1315e_pcie1_groups[] = { "gpio_25" }; 493 + static const char * const rtd1315e_etn_led_groups[] = { "gpio_14", "gpio_15" }; 494 + static const char * const rtd1315e_etn_phy_groups[] = { "gpio_14", "gpio_15" }; 495 + static const char * const rtd1315e_spi_groups[] = { 496 + "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; 497 + static const char * const rtd1315e_pwm0_loc0_groups[] = { "gpio_26" }; 498 + static const char * const rtd1315e_pwm0_loc1_groups[] = { "gpio_20" }; 499 + static const char * const rtd1315e_pwm1_loc0_groups[] = { "gpio_27" }; 500 + static const char * const rtd1315e_pwm1_loc1_groups[] = { "gpio_29" }; 501 + 502 + static const char * const rtd1315e_pwm2_loc0_groups[] = { "gpio_28" }; 503 + static const char * const rtd1315e_pwm2_loc1_groups[] = { "gpio_30" }; 504 + static const char * const rtd1315e_pwm3_loc0_groups[] = { "gpio_47" }; 505 + static const char * const rtd1315e_pwm3_loc1_groups[] = { "gpio_31" }; 506 + static const char * const rtd1315e_spdif_optical_loc0_groups[] = { "gpio_20", "spdif_loc" }; 507 + static const char * const rtd1315e_spdif_optical_loc1_groups[] = { "gpio_6", "spdif_loc" }; 508 + static const char * const rtd1315e_usb_cc1_groups[] = { "usb_cc1" }; 509 + static const char * const rtd1315e_usb_cc2_groups[] = { "usb_cc2" }; 510 + 511 + static const char * const rtd1315e_sd_groups[] = { 512 + "gpio_32", "gpio_33", "gpio_34", "gpio_35", 513 + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; 514 + static const char * const rtd1315e_dmic_loc0_groups[] = { 515 + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", 516 + "gpio_62", "gpio_1", "gpio_6", "dmic_loc" }; 517 + static const char * const rtd1315e_dmic_loc1_groups[] = { 518 + "gpio_32", "gpio_33", "gpio_34", "gpio_35", 519 + "hif_data", "hif_en", "hif_rdy", "hif_clk", 520 + "dmic_loc" }; 521 + static const char * const rtd1315e_ai_loc0_groups[] = { 522 + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", 523 + "gpio_62", "gpio_1", "ai_loc" }; 524 + static const char * const rtd1315e_ai_loc1_groups[] = { 525 + "gpio_32", "gpio_33", "gpio_34", "hif_data", 526 + "hif_en", "hif_rdy", "hif_clk", "ai_loc" }; 527 + static const char * const rtd1315e_tdm_ai_loc0_groups[] = { 528 + "gpio_57", "gpio_58", "gpio_59", 529 + "gpio_60", "tdm_ai_loc" }; 530 + static const char * const rtd1315e_tdm_ai_loc1_groups[] = { 531 + "hif_data", "hif_en", "hif_rdy", "hif_clk", "tdm_ai_loc" }; 532 + static const char * const rtd1315e_hi_loc0_groups[] = { 533 + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; 534 + static const char * const rtd1315e_hi_m_groups[] = { 535 + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; 536 + static const char * const rtd1315e_vtc_i2so_groups[] = { 537 + "gpio_67", "gpio_68", "gpio_69", "gpio_70"}; 538 + static const char * const rtd1315e_vtc_i2si_loc0_groups[] = { 539 + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", 540 + "vtc_i2si_loc" }; 541 + static const char * const rtd1315e_vtc_i2si_loc1_groups[] = { 542 + "gpio_32", "hif_data", "hif_en", "hif_rdy", "hif_clk", 543 + "vtc_i2si_loc" }; 544 + static const char * const rtd1315e_vtc_dmic_loc0_groups[] = { 545 + "gpio_57", "gpio_58", "gpio_59", "gpio_60", 546 + "vtc_dmic_loc" }; 547 + static const char * const rtd1315e_vtc_dmic_loc1_groups[] = { 548 + "hif_data", "hif_en", "hif_rdy", "hif_clk", 549 + "vtc_dmic_loc" }; 550 + static const char * const rtd1315e_vtc_tdm_loc0_groups[] = { 551 + "gpio_57", "gpio_58", "gpio_59", "gpio_60", 552 + "vtc_tdm_loc" }; 553 + static const char * const rtd1315e_vtc_tdm_loc1_groups[] = { 554 + "hif_data", "hif_en", "hif_rdy", "hif_clk", 555 + "vtc_tdm_loc" }; 556 + static const char * const rtd1315e_dc_fan_groups[] = { "gpio_47" }; 557 + static const char * const rtd1315e_pll_test_loc0_groups[] = { "gpio_0", "gpio_1" }; 558 + static const char * const rtd1315e_pll_test_loc1_groups[] = { "gpio_48", "gpio_49" }; 559 + static const char * const rtd1315e_spdif_groups[] = { "gpio_50" }; 560 + static const char * const rtd1315e_ir_rx_groups[] = { "ir_rx" }; 561 + static const char * const rtd1315e_uart2_disable_groups[] = { "ur2_loc" }; 562 + static const char * const rtd1315e_gspi_disable_groups[] = { "gspi_loc" }; 563 + static const char * const rtd1315e_hi_width_disable_groups[] = { "hi_width" }; 564 + static const char * const rtd1315e_hi_width_1bit_groups[] = { "hi_width" }; 565 + static const char * const rtd1315e_sf_disable_groups[] = { "sf_en" }; 566 + static const char * const rtd1315e_sf_enable_groups[] = { "sf_en" }; 567 + static const char * const rtd1315e_scpu_ejtag_loc0_groups[] = { 568 + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", 569 + "ejtag_scpu_loc" }; 570 + static const char * const rtd1315e_scpu_ejtag_loc1_groups[] = { 571 + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", 572 + "ejtag_scpu_loc" }; 573 + static const char * const rtd1315e_scpu_ejtag_loc2_groups[] = { 574 + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", 575 + "ejtag_scpu_loc" }; 576 + static const char * const rtd1315e_scpu_ejtag_loc3_groups[] = { 577 + "hif_data" }; 578 + static const char * const rtd1315e_acpu_ejtag_loc0_groups[] = { 579 + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", 580 + "ejtag_acpu_loc" }; 581 + static const char * const rtd1315e_acpu_ejtag_loc1_groups[] = { 582 + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", 583 + "ejtag_acpu_loc" }; 584 + static const char * const rtd1315e_acpu_ejtag_loc2_groups[] = { 585 + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", 586 + "ejtag_acpu_loc" }; 587 + static const char * const rtd1315e_vcpu_ejtag_loc0_groups[] = { 588 + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", 589 + "ejtag_vcpu_loc" }; 590 + static const char * const rtd1315e_vcpu_ejtag_loc1_groups[] = { 591 + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", 592 + "ejtag_vcpu_loc" }; 593 + static const char * const rtd1315e_vcpu_ejtag_loc2_groups[] = { 594 + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", 595 + "ejtag_vcpu_loc" }; 596 + static const char * const rtd1315e_aucpu_ejtag_loc0_groups[] = { 597 + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", 598 + "ejtag_aucpu_loc" }; 599 + static const char * const rtd1315e_aucpu_ejtag_loc1_groups[] = { 600 + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", 601 + "ejtag_aucpu_loc" }; 602 + static const char * const rtd1315e_aucpu_ejtag_loc2_groups[] = { 603 + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", 604 + "ejtag_aucpu_loc" }; 605 + static const char * const rtd1315e_gpu_ejtag_groups[] = { 606 + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72" }; 607 + 608 + static const char * const rtd1315e_iso_tristate_groups[] = { 609 + "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd", 610 + "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", 611 + "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7", 612 + "gpio_1", "gpio_7", "gpio_8", "gpio_9", "gpio_10", 613 + "gpio_11", "usb_cc2", "gpio_32", "gpio_33", "hif_data", 614 + "hif_en", "hif_rdy", "hif_clk", "ir_rx", "ur0_rx", 615 + "ur0_tx", "gpio_66", "gpio_67", "gpio_68", "gpio_69", "gpio_70", 616 + "gpio_71", "gpio_72", "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; 617 + static const char * const rtd1315e_dbg_out0_groups[] = { 618 + "gpio_0", "gpio_12", "gpio_13", "gpio_16", "gpio_17", "gpio_26", 619 + "gpio_27", "gpio_28", "gpio_29", "gpio_30", "gpio_34", "gpio_35", 620 + "gpio_46", "gpio_48", "gpio_49", "usb_cc1", "gpio_57", "gpio_58", "gpio_59", "gpio_60" }; 621 + static const char * const rtd1315e_dbg_out1_groups[] = { 622 + "gpio_6", "gpio_14", "gpio_15", "gpio_18", "gpio_19", "gpio_20", 623 + "gpio_25", "gpio_31", "gpio_47", "gpio_50", "gpio_59", "gpio_61", 624 + "gpio_62" }; 625 + static const char * const rtd1315e_standby_dbg_groups[] = { 626 + "gpio_1", "gpio_6", "ir_rx" }; 627 + static const char * const rtd1315e_arm_trace_debug_disable_groups[] = { "arm_trace_dbg_en" }; 628 + static const char * const rtd1315e_arm_trace_debug_enable_groups[] = { "arm_trace_dbg_en" }; 629 + static const char * const rtd1315e_aucpu_ejtag_disable_groups[] = { "ejtag_aucpu_loc" }; 630 + static const char * const rtd1315e_acpu_ejtag_disable_groups[] = { "ejtag_acpu_loc" }; 631 + static const char * const rtd1315e_vcpu_ejtag_disable_groups[] = { "ejtag_vcpu_loc" }; 632 + static const char * const rtd1315e_scpu_ejtag_disable_groups[] = { "ejtag_scpu_loc" }; 633 + static const char * const rtd1315e_vtc_dmic_loc_disable_groups[] = { "vtc_dmic_loc" }; 634 + static const char * const rtd1315e_vtc_tdm_disable_groups[] = { "vtc_tdm_loc" }; 635 + static const char * const rtd1315e_vtc_i2si_disable_groups[] = { "vtc_i2si_loc" }; 636 + static const char * const rtd1315e_tdm_ai_disable_groups[] = { "tdm_ai_loc" }; 637 + static const char * const rtd1315e_ai_disable_groups[] = { "ai_loc" }; 638 + static const char * const rtd1315e_spdif_disable_groups[] = { "spdif_loc" }; 639 + static const char * const rtd1315e_hif_disable_groups[] = { "hif_en_loc" }; 640 + static const char * const rtd1315e_hif_enable_groups[] = { "hif_en_loc" }; 641 + static const char * const rtd1315e_test_loop_groups[] = { "gpio_50" }; 642 + static const char * const rtd1315e_pmic_pwrup_groups[] = { "gpio_78" }; 643 + 644 + #define RTD1315E_FUNC(_name) \ 645 + { \ 646 + .name = # _name, \ 647 + .groups = rtd1315e_ ## _name ## _groups, \ 648 + .num_groups = ARRAY_SIZE(rtd1315e_ ## _name ## _groups), \ 649 + } 650 + 651 + static const struct rtd_pin_func_desc rtd1315e_pin_functions[] = { 652 + RTD1315E_FUNC(gpio), 653 + RTD1315E_FUNC(nf), 654 + RTD1315E_FUNC(emmc), 655 + RTD1315E_FUNC(ao), 656 + RTD1315E_FUNC(gspi_loc0), 657 + RTD1315E_FUNC(gspi_loc1), 658 + RTD1315E_FUNC(uart0), 659 + RTD1315E_FUNC(uart1), 660 + RTD1315E_FUNC(uart2_loc0), 661 + RTD1315E_FUNC(uart2_loc1), 662 + RTD1315E_FUNC(i2c0), 663 + RTD1315E_FUNC(i2c1), 664 + RTD1315E_FUNC(i2c4), 665 + RTD1315E_FUNC(i2c5), 666 + RTD1315E_FUNC(pcie1), 667 + RTD1315E_FUNC(etn_led), 668 + RTD1315E_FUNC(etn_phy), 669 + RTD1315E_FUNC(spi), 670 + RTD1315E_FUNC(pwm0_loc0), 671 + RTD1315E_FUNC(pwm0_loc1), 672 + RTD1315E_FUNC(pwm1_loc0), 673 + RTD1315E_FUNC(pwm1_loc1), 674 + RTD1315E_FUNC(pwm2_loc0), 675 + RTD1315E_FUNC(pwm2_loc1), 676 + RTD1315E_FUNC(pwm3_loc0), 677 + RTD1315E_FUNC(pwm3_loc1), 678 + RTD1315E_FUNC(spdif_optical_loc0), 679 + RTD1315E_FUNC(spdif_optical_loc1), 680 + RTD1315E_FUNC(usb_cc1), 681 + RTD1315E_FUNC(usb_cc2), 682 + RTD1315E_FUNC(sd), 683 + RTD1315E_FUNC(dmic_loc0), 684 + RTD1315E_FUNC(dmic_loc1), 685 + RTD1315E_FUNC(ai_loc0), 686 + RTD1315E_FUNC(ai_loc1), 687 + RTD1315E_FUNC(tdm_ai_loc0), 688 + RTD1315E_FUNC(tdm_ai_loc1), 689 + RTD1315E_FUNC(hi_loc0), 690 + RTD1315E_FUNC(hi_m), 691 + RTD1315E_FUNC(vtc_i2so), 692 + RTD1315E_FUNC(vtc_i2si_loc0), 693 + RTD1315E_FUNC(vtc_i2si_loc1), 694 + RTD1315E_FUNC(vtc_dmic_loc0), 695 + RTD1315E_FUNC(vtc_dmic_loc1), 696 + RTD1315E_FUNC(vtc_tdm_loc0), 697 + RTD1315E_FUNC(vtc_tdm_loc1), 698 + RTD1315E_FUNC(dc_fan), 699 + RTD1315E_FUNC(pll_test_loc0), 700 + RTD1315E_FUNC(pll_test_loc1), 701 + RTD1315E_FUNC(ir_rx), 702 + RTD1315E_FUNC(uart2_disable), 703 + RTD1315E_FUNC(gspi_disable), 704 + RTD1315E_FUNC(hi_width_disable), 705 + RTD1315E_FUNC(hi_width_1bit), 706 + RTD1315E_FUNC(sf_disable), 707 + RTD1315E_FUNC(sf_enable), 708 + RTD1315E_FUNC(scpu_ejtag_loc0), 709 + RTD1315E_FUNC(scpu_ejtag_loc1), 710 + RTD1315E_FUNC(scpu_ejtag_loc2), 711 + RTD1315E_FUNC(scpu_ejtag_loc3), 712 + RTD1315E_FUNC(acpu_ejtag_loc0), 713 + RTD1315E_FUNC(acpu_ejtag_loc1), 714 + RTD1315E_FUNC(acpu_ejtag_loc2), 715 + RTD1315E_FUNC(vcpu_ejtag_loc0), 716 + RTD1315E_FUNC(vcpu_ejtag_loc1), 717 + RTD1315E_FUNC(vcpu_ejtag_loc2), 718 + RTD1315E_FUNC(aucpu_ejtag_loc0), 719 + RTD1315E_FUNC(aucpu_ejtag_loc1), 720 + RTD1315E_FUNC(aucpu_ejtag_loc2), 721 + RTD1315E_FUNC(gpu_ejtag), 722 + RTD1315E_FUNC(iso_tristate), 723 + RTD1315E_FUNC(dbg_out0), 724 + RTD1315E_FUNC(dbg_out1), 725 + RTD1315E_FUNC(standby_dbg), 726 + RTD1315E_FUNC(spdif), 727 + RTD1315E_FUNC(arm_trace_debug_disable), 728 + RTD1315E_FUNC(arm_trace_debug_enable), 729 + RTD1315E_FUNC(aucpu_ejtag_disable), 730 + RTD1315E_FUNC(acpu_ejtag_disable), 731 + RTD1315E_FUNC(vcpu_ejtag_disable), 732 + RTD1315E_FUNC(scpu_ejtag_disable), 733 + RTD1315E_FUNC(vtc_dmic_loc_disable), 734 + RTD1315E_FUNC(vtc_tdm_disable), 735 + RTD1315E_FUNC(vtc_i2si_disable), 736 + RTD1315E_FUNC(tdm_ai_disable), 737 + RTD1315E_FUNC(ai_disable), 738 + RTD1315E_FUNC(spdif_disable), 739 + RTD1315E_FUNC(hif_disable), 740 + RTD1315E_FUNC(hif_enable), 741 + RTD1315E_FUNC(test_loop), 742 + RTD1315E_FUNC(pmic_pwrup), 743 + }; 744 + 745 + #undef RTD1315E_FUNC 746 + 747 + static const struct rtd_pin_desc rtd1315e_iso_muxes[ARRAY_SIZE(rtd1315e_iso_pins)] = { 748 + [RTD1315E_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(3, 0), 749 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), 750 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"), 751 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"), 752 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), 753 + [RTD1315E_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(7, 4), 754 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), 755 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"), 756 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), 757 + [RTD1315E_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(11, 8), 758 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), 759 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"), 760 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"), 761 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), 762 + [RTD1315E_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(15, 12), 763 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), 764 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), 765 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"), 766 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), 767 + [RTD1315E_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(19, 16), 768 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), 769 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"), 770 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"), 771 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), 772 + [RTD1315E_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(23, 20), 773 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), 774 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"), 775 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc"), 776 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), 777 + [RTD1315E_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(27, 24), 778 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), 779 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"), 780 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "emmc"), 781 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), 782 + [RTD1315E_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(31, 28), 783 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), 784 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"), 785 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "emmc"), 786 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), 787 + 788 + [RTD1315E_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x4, GENMASK(3, 0), 789 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), 790 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"), 791 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"), 792 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), 793 + [RTD1315E_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x4, GENMASK(7, 4), 794 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), 795 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "nf"), 796 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"), 797 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), 798 + [RTD1315E_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x4, GENMASK(11, 8), 799 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), 800 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"), 801 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"), 802 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), 803 + [RTD1315E_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x4, GENMASK(15, 12), 804 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), 805 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), 806 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"), 807 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), 808 + [RTD1315E_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x4, GENMASK(19, 16), 809 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), 810 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pll_test_loc0"), 811 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")), 812 + [RTD1315E_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x4, GENMASK(23, 20), 813 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), 814 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "standby_dbg"), 815 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "pll_test_loc0"), 816 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc0"), 817 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "ai_loc0"), 818 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), 819 + [RTD1315E_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x4, GENMASK(27, 24), 820 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), 821 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "standby_dbg"), 822 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc0"), 823 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "spdif_optical_loc1"), 824 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), 825 + [RTD1315E_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x4, GENMASK(31, 28), 826 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), 827 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), 828 + 829 + [RTD1315E_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0x8, GENMASK(3, 0), 830 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), 831 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"), 832 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi_loc1"), 833 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), 834 + [RTD1315E_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0x8, GENMASK(7, 4), 835 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), 836 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart1"), 837 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "gspi_loc1"), 838 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), 839 + [RTD1315E_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0x8, GENMASK(11, 8), 840 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), 841 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart1"), 842 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc1"), 843 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), 844 + [RTD1315E_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0x8, GENMASK(15, 12), 845 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), 846 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart1"), 847 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc1"), 848 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), 849 + [RTD1315E_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0x8, GENMASK(19, 16), 850 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), 851 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "i2c0"), 852 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")), 853 + [RTD1315E_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0x8, GENMASK(23, 20), 854 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), 855 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c0"), 856 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")), 857 + [RTD1315E_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0x8, GENMASK(27, 24), 858 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), 859 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "etn_led"), 860 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "etn_phy"), 861 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), 862 + [RTD1315E_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0x8, GENMASK(31, 28), 863 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), 864 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "etn_led"), 865 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "etn_phy"), 866 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")), 867 + 868 + [RTD1315E_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0xc, GENMASK(3, 0), 869 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), 870 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "i2c1"), 871 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), 872 + [RTD1315E_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0xc, GENMASK(7, 4), 873 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), 874 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "i2c1"), 875 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), 876 + [RTD1315E_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0xc, GENMASK(11, 8), 877 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), 878 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2_loc0"), 879 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc0"), 880 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")), 881 + [RTD1315E_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0xc, GENMASK(15, 12), 882 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), 883 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2_loc0"), 884 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc0"), 885 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")), 886 + [RTD1315E_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0xc, GENMASK(19, 16), 887 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), 888 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc0"), 889 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pwm0_loc1"), 890 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi_loc0"), 891 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "spdif_optical_loc0"), 892 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")), 893 + [RTD1315E_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0xc, GENMASK(23, 20), 894 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), 895 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "usb_cc2"), 896 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), 897 + [RTD1315E_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0xc, GENMASK(27, 24), 898 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), 899 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "uart2_loc1"), 900 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "pcie1"), 901 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), 902 + [RTD1315E_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0xc, GENMASK(31, 28), 903 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), 904 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart2_loc1"), 905 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "pwm0_loc0"), 906 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")), 907 + 908 + [RTD1315E_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0x10, GENMASK(3, 0), 909 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), 910 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc1"), 911 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "pwm1_loc0"), 912 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), 913 + [RTD1315E_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0x10, GENMASK(7, 4), 914 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), 915 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart2_loc1"), 916 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "pwm2_loc0"), 917 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), 918 + [RTD1315E_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0x10, GENMASK(11, 8), 919 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), 920 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "i2c5"), 921 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "pwm1_loc1"), 922 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")), 923 + [RTD1315E_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0x10, GENMASK(15, 12), 924 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), 925 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "pwm2_loc1"), 926 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")), 927 + [RTD1315E_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0x10, GENMASK(19, 16), 928 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), 929 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc0"), 930 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pwm3_loc1"), 931 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi_loc0"), 932 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")), 933 + [RTD1315E_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0x10, GENMASK(23, 20), 934 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), 935 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "sd"), 936 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "aucpu_ejtag_loc1"), 937 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc1"), 938 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc1"), 939 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc1"), 940 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc1"), 941 + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_loc1"), 942 + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2si_loc1"), 943 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), 944 + [RTD1315E_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0x10, GENMASK(27, 24), 945 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), 946 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"), 947 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "aucpu_ejtag_loc1"), 948 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc1"), 949 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "scpu_ejtag_loc1"), 950 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc1"), 951 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc1"), 952 + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "ai_loc1"), 953 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), 954 + [RTD1315E_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0x10, GENMASK(31, 28), 955 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), 956 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sd"), 957 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc1"), 958 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "i2c4"), 959 + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 28), "ai_loc1"), 960 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")), 961 + 962 + [RTD1315E_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0x14, GENMASK(3, 0), 963 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), 964 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sd"), 965 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc1"), 966 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "i2c4"), 967 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), 968 + [RTD1315E_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x14, GENMASK(7, 4), 969 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), 970 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sd"), 971 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "aucpu_ejtag_loc1"), 972 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc1"), 973 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "tdm_ai_loc1"), 974 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc1"), 975 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc1"), 976 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc1"), 977 + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ai_loc1"), 978 + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "hi_loc0"), 979 + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 4), "hi_m"), 980 + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 4), "vtc_i2si_loc1"), 981 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "vtc_tdm_loc1"), 982 + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "vtc_dmic_loc1"), 983 + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "scpu_ejtag_loc3"), 984 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), 985 + [RTD1315E_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x14, GENMASK(11, 8), 986 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), 987 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sd"), 988 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "aucpu_ejtag_loc1"), 989 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc1"), 990 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "tdm_ai_loc1"), 991 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc1"), 992 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc1"), 993 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc1"), 994 + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "ai_loc1"), 995 + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "hi_loc0"), 996 + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "hi_m"), 997 + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2si_loc1"), 998 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "vtc_tdm_loc1"), 999 + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 8), "vtc_dmic_loc1"), 1000 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), 1001 + [RTD1315E_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x14, GENMASK(15, 12), 1002 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), 1003 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sd"), 1004 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc1"), 1005 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "tdm_ai_loc1"), 1006 + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "ai_loc1"), 1007 + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "hi_loc0"), 1008 + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 12), "hi_m"), 1009 + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 12), "vtc_i2si_loc1"), 1010 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "vtc_tdm_loc1"), 1011 + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 12), "vtc_dmic_loc1"), 1012 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), 1013 + [RTD1315E_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x14, GENMASK(19, 16), 1014 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), 1015 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "sd"), 1016 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "aucpu_ejtag_loc1"), 1017 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic_loc1"), 1018 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "tdm_ai_loc1"), 1019 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc1"), 1020 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc1"), 1021 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc1"), 1022 + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ai_loc1"), 1023 + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "hi_loc0"), 1024 + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "hi_m"), 1025 + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2si_loc1"), 1026 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "vtc_tdm_loc1"), 1027 + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "vtc_dmic_loc1"), 1028 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), 1029 + [RTD1315E_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x14, GENMASK(23, 20), 1030 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), 1031 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c5"), 1032 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")), 1033 + [RTD1315E_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x14, GENMASK(27, 24), 1034 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), 1035 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "dc_fan"), 1036 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "pwm3_loc0"), 1037 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), 1038 + [RTD1315E_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x14, GENMASK(31, 28), 1039 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), 1040 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "pll_test_loc1"), 1041 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")), 1042 + 1043 + [RTD1315E_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x18, GENMASK(3, 0), 1044 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), 1045 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pll_test_loc1"), 1046 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), 1047 + [RTD1315E_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x18, GENMASK(7, 4), 1048 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), 1049 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "spdif"), 1050 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "test_loop"), 1051 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out1")), 1052 + [RTD1315E_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x18, GENMASK(11, 8), 1053 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), 1054 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "usb_cc1"), 1055 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")), 1056 + [RTD1315E_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x18, GENMASK(15, 12), 1057 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), 1058 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "ir_rx"), 1059 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "standby_dbg"), 1060 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), 1061 + [RTD1315E_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x18, GENMASK(19, 16), 1062 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), 1063 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart0"), 1064 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), 1065 + [RTD1315E_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x18, GENMASK(23, 20), 1066 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), 1067 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "uart0"), 1068 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), 1069 + [RTD1315E_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x18, GENMASK(27, 24), 1070 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), 1071 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "tdm_ai_loc0"), 1072 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "ai_loc0"), 1073 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc0"), 1074 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc2"), 1075 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc2"), 1076 + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "aucpu_ejtag_loc2"), 1077 + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 24), "vtc_i2si_loc0"), 1078 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 24), "vtc_tdm_loc0"), 1079 + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "vtc_dmic_loc0"), 1080 + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 24), "scpu_ejtag_loc2"), 1081 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out0")), 1082 + [RTD1315E_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x18, GENMASK(31, 28), 1083 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), 1084 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "tdm_ai_loc0"), 1085 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "ai_loc0"), 1086 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc0"), 1087 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "acpu_ejtag_loc2"), 1088 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "vcpu_ejtag_loc2"), 1089 + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 28), "aucpu_ejtag_loc2"), 1090 + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 28), "vtc_i2si_loc0"), 1091 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 28), "vtc_tdm_loc0"), 1092 + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "vtc_dmic_loc0"), 1093 + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 28), "scpu_ejtag_loc2"), 1094 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")), 1095 + 1096 + [RTD1315E_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x1c, GENMASK(3, 0), 1097 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), 1098 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "tdm_ai_loc0"), 1099 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ai_loc0"), 1100 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc0"), 1101 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc2"), 1102 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc2"), 1103 + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "aucpu_ejtag_loc2"), 1104 + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2si_loc0"), 1105 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 0), "vtc_tdm_loc0"), 1106 + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 0), "vtc_dmic_loc0"), 1107 + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "scpu_ejtag_loc2"), 1108 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out1")), 1109 + [RTD1315E_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x1c, GENMASK(7, 4), 1110 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), 1111 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "tdm_ai_loc0"), 1112 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ai_loc0"), 1113 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc0"), 1114 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc2"), 1115 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc2"), 1116 + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "aucpu_ejtag_loc2"), 1117 + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 4), "vtc_i2si_loc0"), 1118 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "vtc_tdm_loc0"), 1119 + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "vtc_dmic_loc0"), 1120 + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "scpu_ejtag_loc2"), 1121 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), 1122 + [RTD1315E_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x1c, GENMASK(11, 8), 1123 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), 1124 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc0"), 1125 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc0"), 1126 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc2"), 1127 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc2"), 1128 + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "aucpu_ejtag_loc2"), 1129 + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2si_loc0"), 1130 + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "scpu_ejtag_loc2"), 1131 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")), 1132 + [RTD1315E_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x1c, GENMASK(15, 12), 1133 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), 1134 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ai_loc0"), 1135 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc0"), 1136 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")), 1137 + [RTD1315E_ISO_GPIO_66] = RTK_PIN_MUX(gpio_66, 0x1c, GENMASK(19, 16), 1138 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), 1139 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "ao"), 1140 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), 1141 + [RTD1315E_ISO_GPIO_67] = RTK_PIN_MUX(gpio_67, 0x1c, GENMASK(23, 20), 1142 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), 1143 + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2so"), 1144 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 20), "ao"), 1145 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), 1146 + [RTD1315E_ISO_GPIO_68] = RTK_PIN_MUX(gpio_68, 0x1c, GENMASK(27, 24), 1147 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), 1148 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "aucpu_ejtag_loc0"), 1149 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "gpu_ejtag"), 1150 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "scpu_ejtag_loc0"), 1151 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc0"), 1152 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc0"), 1153 + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 24), "vtc_i2so"), 1154 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 24), "ao"), 1155 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), 1156 + [RTD1315E_ISO_GPIO_69] = RTK_PIN_MUX(gpio_69, 0x1c, GENMASK(31, 28), 1157 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), 1158 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "aucpu_ejtag_loc0"), 1159 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "gpu_ejtag"), 1160 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "scpu_ejtag_loc0"), 1161 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "acpu_ejtag_loc0"), 1162 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "vcpu_ejtag_loc0"), 1163 + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 28), "vtc_i2so"), 1164 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 28), "ao"), 1165 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), 1166 + 1167 + [RTD1315E_ISO_GPIO_70] = RTK_PIN_MUX(gpio_70, 0x20, GENMASK(3, 0), 1168 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), 1169 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "aucpu_ejtag_loc0"), 1170 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "gpu_ejtag"), 1171 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc0"), 1172 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc0"), 1173 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc0"), 1174 + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2so"), 1175 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 0), "ao"), 1176 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), 1177 + [RTD1315E_ISO_GPIO_71] = RTK_PIN_MUX(gpio_71, 0x20, GENMASK(7, 4), 1178 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), 1179 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "aucpu_ejtag_loc0"), 1180 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "gpu_ejtag"), 1181 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc0"), 1182 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc0"), 1183 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc0"), 1184 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "ao"), 1185 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), 1186 + [RTD1315E_ISO_GPIO_72] = RTK_PIN_MUX(gpio_72, 0x20, GENMASK(11, 8), 1187 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), 1188 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "aucpu_ejtag_loc0"), 1189 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "gpu_ejtag"), 1190 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc0"), 1191 + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc0"), 1192 + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc0"), 1193 + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "ao"), 1194 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), 1195 + [RTD1315E_ISO_GPIO_78] = RTK_PIN_MUX(gpio_78, 0x20, GENMASK(15, 12), 1196 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), 1197 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), 1198 + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "pmic_pwrup"), 1199 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "spi"), 1200 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), 1201 + [RTD1315E_ISO_GPIO_79] = RTK_PIN_MUX(gpio_79, 0x20, GENMASK(19, 16), 1202 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), 1203 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"), 1204 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "spi"), 1205 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), 1206 + [RTD1315E_ISO_GPIO_80] = RTK_PIN_MUX(gpio_80, 0x20, GENMASK(23, 20), 1207 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), 1208 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"), 1209 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "spi"), 1210 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), 1211 + [RTD1315E_ISO_GPIO_81] = RTK_PIN_MUX(gpio_81, 0x20, GENMASK(27, 24), 1212 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), 1213 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"), 1214 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "spi"), 1215 + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), 1216 + 1217 + [RTD1315E_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0), 1218 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "uart2_disable"), 1219 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc0"), 1220 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart2_loc1")), 1221 + [RTD1315E_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2), 1222 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gspi_disable"), 1223 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "gspi_loc0"), 1224 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "gspi_loc1")), 1225 + [RTD1315E_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8), 1226 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"), 1227 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")), 1228 + [RTD1315E_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11), 1229 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"), 1230 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")), 1231 + [RTD1315E_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12), 1232 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"), 1233 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")), 1234 + [RTD1315E_ISO_EJTAG_AUCPU_LOC] = RTK_PIN_MUX(ejtag_aucpu_loc, 0x120, GENMASK(16, 14), 1235 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "aucpu_ejtag_disable"), 1236 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "aucpu_ejtag_loc0"), 1237 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "aucpu_ejtag_loc1"), 1238 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "aucpu_ejtag_loc2")), 1239 + [RTD1315E_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17), 1240 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "acpu_ejtag_disable"), 1241 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "acpu_ejtag_loc0"), 1242 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "acpu_ejtag_loc1"), 1243 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "acpu_ejtag_loc2")), 1244 + [RTD1315E_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20), 1245 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "vcpu_ejtag_disable"), 1246 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vcpu_ejtag_loc0"), 1247 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vcpu_ejtag_loc1"), 1248 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "vcpu_ejtag_loc2")), 1249 + [RTD1315E_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23), 1250 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "scpu_ejtag_disable"), 1251 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"), 1252 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"), 1253 + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")), 1254 + [RTD1315E_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26), 1255 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "dmic_loc0"), 1256 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "dmic_loc1")), 1257 + 1258 + [RTD1315E_ISO_VTC_DMIC_LOC] = RTK_PIN_MUX(vtc_dmic_loc, 0x128, GENMASK(1, 0), 1259 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "vtc_dmic_loc_disable"), 1260 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vtc_dmic_loc0"), 1261 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "vtc_dmic_loc1")), 1262 + [RTD1315E_ISO_VTC_TDM_LOC] = RTK_PIN_MUX(vtc_tdm_loc, 0x128, GENMASK(3, 2), 1263 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "vtc_tdm_disable"), 1264 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "vtc_tdm_loc0"), 1265 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "vtc_tdm_loc1")), 1266 + [RTD1315E_ISO_VTC_I2SI_LOC] = RTK_PIN_MUX(vtc_i2si_loc, 0x128, GENMASK(5, 4), 1267 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "vtc_i2si_disable"), 1268 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vtc_i2si_loc0"), 1269 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vtc_i2si_loc1")), 1270 + [RTD1315E_ISO_TDM_AI_LOC] = RTK_PIN_MUX(tdm_ai_loc, 0x128, GENMASK(7, 6), 1271 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "tdm_ai_disable"), 1272 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "tdm_ai_loc0"), 1273 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "tdm_ai_loc1")), 1274 + [RTD1315E_ISO_AI_LOC] = RTK_PIN_MUX(ai_loc, 0x128, GENMASK(9, 8), 1275 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "ai_disable"), 1276 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "ai_loc0"), 1277 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc1")), 1278 + [RTD1315E_ISO_SPDIF_LOC] = RTK_PIN_MUX(spdif_loc, 0x128, GENMASK(11, 10), 1279 + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "spdif_disable"), 1280 + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "spdif_optical_loc0"), 1281 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "spdif_optical_loc1")), 1282 + 1283 + [RTD1315E_ISO_HIF_EN_LOC] = RTK_PIN_MUX(hif_en_loc, 0x12c, GENMASK(2, 0), 1284 + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "hif_disable"), 1285 + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "hif_enable")), 1286 + }; 1287 + 1288 + static const struct rtd_pin_config_desc rtd1315e_iso_configs[ARRAY_SIZE(rtd1315e_iso_pins)] = { 1289 + [RTD1315E_ISO_BOOT_SEL] = RTK_PIN_CONFIG(boot_sel, 0x24, 0, 0, 1, NA, 2, 3, NA), 1290 + [RTD1315E_ISO_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x24, 4, 0, 1, NA, 2, 12, NA), 1291 + [RTD1315E_ISO_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x24, 17, 0, 1, NA, 2, 13, NA), 1292 + [RTD1315E_ISO_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x28, 0, 0, 1, NA, 2, 12, NA), 1293 + [RTD1315E_ISO_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x28, 13, 0, 1, NA, 2, 12, NA), 1294 + [RTD1315E_ISO_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x2c, 0, 0, 1, NA, 2, 12, NA), 1295 + [RTD1315E_ISO_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x2c, 13, 0, 1, NA, 2, 12, NA), 1296 + [RTD1315E_ISO_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x30, 0, 0, 1, NA, 2, 12, NA), 1297 + [RTD1315E_ISO_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x30, 13, 0, 1, NA, 2, 12, NA), 1298 + [RTD1315E_ISO_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x34, 0, 0, 1, NA, 2, 12, NA), 1299 + [RTD1315E_ISO_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x34, 13, 0, 1, NA, 2, 12, NA), 1300 + [RTD1315E_ISO_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x38, 0, 0, 1, NA, 2, 12, NA), 1301 + [RTD1315E_ISO_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x38, 13, 0, 1, NA, 2, 12, NA), 1302 + [RTD1315E_ISO_GPIO_1] = RTK_PIN_CONFIG(gpio_1, 0x3c, 0, 1, 2, 0, 3, 4, PADDRI_4_8), 1303 + [RTD1315E_ISO_GPIO_6] = RTK_PIN_CONFIG(gpio_6, 0x3c, 5, 1, 2, 0, 3, 4, PADDRI_4_8), 1304 + [RTD1315E_ISO_GPIO_7] = RTK_PIN_CONFIG(gpio_7, 0x3c, 10, 1, 2, 0, 3, 4, PADDRI_4_8), 1305 + [RTD1315E_ISO_GPIO_8] = RTK_PIN_CONFIG(gpio_8, 0x3c, 15, 1, 2, 0, 3, 4, PADDRI_4_8), 1306 + [RTD1315E_ISO_GPIO_9] = RTK_PIN_CONFIG(gpio_9, 0x3c, 20, 1, 2, 0, 3, 4, PADDRI_4_8), 1307 + [RTD1315E_ISO_GPIO_10] = RTK_PIN_CONFIG(gpio_10, 0x3c, 25, 1, 2, 0, 3, 4, PADDRI_4_8), 1308 + [RTD1315E_ISO_GPIO_11] = RTK_PIN_CONFIG(gpio_11, 0x40, 0, 1, 2, 0, 3, 4, PADDRI_4_8), 1309 + [RTD1315E_ISO_GPIO_12] = RTK_PIN_CONFIG(gpio_12, 0x40, 5, 1, 2, 0, 3, 4, PADDRI_4_8), 1310 + [RTD1315E_ISO_GPIO_13] = RTK_PIN_CONFIG(gpio_13, 0x40, 10, 1, 2, 0, 3, 4, PADDRI_4_8), 1311 + [RTD1315E_ISO_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x40, 15, 1, 2, 0, 3, 4, PADDRI_4_8), 1312 + [RTD1315E_ISO_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x40, 20, 1, 2, 0, 3, 4, PADDRI_4_8), 1313 + [RTD1315E_ISO_GPIO_16] = RTK_PIN_CONFIG(gpio_16, 0x40, 25, 1, 2, 0, 3, 4, PADDRI_4_8), 1314 + [RTD1315E_ISO_GPIO_17] = RTK_PIN_CONFIG(gpio_17, 0x44, 0, 1, 2, 0, 3, 4, PADDRI_4_8), 1315 + [RTD1315E_ISO_GPIO_18] = RTK_PIN_CONFIG(gpio_18, 0x44, 5, 1, 2, 0, 3, 4, PADDRI_4_8), 1316 + [RTD1315E_ISO_GPIO_19] = RTK_PIN_CONFIG(gpio_19, 0x44, 10, 1, 2, 0, 3, 4, PADDRI_4_8), 1317 + [RTD1315E_ISO_GPIO_20] = RTK_PIN_CONFIG(gpio_20, 0x44, 15, 1, 2, 0, 3, 4, PADDRI_4_8), 1318 + [RTD1315E_ISO_GPIO_25] = RTK_PIN_CONFIG(gpio_25, 0x44, 20, 1, 2, 0, 3, 4, PADDRI_4_8), 1319 + [RTD1315E_ISO_GPIO_26] = RTK_PIN_CONFIG(gpio_26, 0x44, 25, 1, 2, 0, 3, 4, PADDRI_4_8), 1320 + [RTD1315E_ISO_GPIO_27] = RTK_PIN_CONFIG(gpio_27, 0x48, 0, 1, 2, 0, 3, 4, PADDRI_4_8), 1321 + [RTD1315E_ISO_GPIO_28] = RTK_PIN_CONFIG(gpio_28, 0x48, 6, 1, 2, 0, 3, 4, PADDRI_4_8), 1322 + [RTD1315E_ISO_GPIO_29] = RTK_PIN_CONFIG(gpio_29, 0x48, 12, 1, 2, 0, 3, 4, PADDRI_4_8), 1323 + [RTD1315E_ISO_GPIO_30] = RTK_PIN_CONFIG(gpio_30, 0x48, 17, 1, 2, 0, 3, 4, PADDRI_4_8), 1324 + [RTD1315E_ISO_GPIO_31] = RTK_PIN_CONFIG(gpio_31, 0x4c, 0, 1, 2, 0, 3, 4, PADDRI_4_8), 1325 + [RTD1315E_ISO_GPIO_32] = RTK_PIN_CONFIG(gpio_32, 0x4c, 5, 0, 1, NA, 2, 12, NA), 1326 + [RTD1315E_ISO_GPIO_33] = RTK_PIN_CONFIG(gpio_33, 0x4c, 18, 0, 1, NA, 2, 12, NA), 1327 + [RTD1315E_ISO_GPIO_34] = RTK_PIN_CONFIG(gpio_34, 0x50, 0, 1, 2, 0, 3, 4, PADDRI_4_8), 1328 + [RTD1315E_ISO_GPIO_35] = RTK_PIN_CONFIG(gpio_35, 0x50, 5, 1, 2, 0, 3, 4, PADDRI_4_8), 1329 + [RTD1315E_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x50, 10, 1, 2, 0, 3, 4, PADDRI_4_8), 1330 + [RTD1315E_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x50, 15, 1, 2, 0, 3, 4, PADDRI_4_8), 1331 + [RTD1315E_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x50, 20, 1, 2, 0, 3, 4, PADDRI_4_8), 1332 + [RTD1315E_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x50, 25, 1, 2, 0, 3, 4, PADDRI_4_8), 1333 + [RTD1315E_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x54, 0, 1, 2, 0, 3, 4, PADDRI_4_8), 1334 + [RTD1315E_ISO_GPIO_57] = RTK_PIN_CONFIG(gpio_57, 0x54, 5, 1, 2, 0, 3, 4, PADDRI_4_8), 1335 + [RTD1315E_ISO_GPIO_58] = RTK_PIN_CONFIG(gpio_58, 0x54, 10, 1, 2, 0, 3, 4, PADDRI_4_8), 1336 + [RTD1315E_ISO_GPIO_59] = RTK_PIN_CONFIG(gpio_59, 0x54, 15, 1, 2, 0, 3, 4, PADDRI_4_8), 1337 + [RTD1315E_ISO_GPIO_60] = RTK_PIN_CONFIG(gpio_60, 0x54, 20, 1, 2, 0, 3, 4, PADDRI_4_8), 1338 + [RTD1315E_ISO_GPIO_61] = RTK_PIN_CONFIG(gpio_61, 0x54, 25, 1, 2, 0, 3, 4, PADDRI_4_8), 1339 + [RTD1315E_ISO_GPIO_62] = RTK_PIN_CONFIG(gpio_62, 0x58, 0, 1, 2, 0, 3, 4, PADDRI_4_8), 1340 + [RTD1315E_ISO_GPIO_66] = RTK_PIN_CONFIG(gpio_66, 0x58, 5, 1, 2, 0, 3, 4, PADDRI_4_8), 1341 + [RTD1315E_ISO_GPIO_67] = RTK_PIN_CONFIG(gpio_67, 0x58, 10, 1, 2, 0, 3, 4, PADDRI_4_8), 1342 + [RTD1315E_ISO_GPIO_68] = RTK_PIN_CONFIG(gpio_68, 0x58, 15, 1, 2, 0, 3, 4, PADDRI_4_8), 1343 + [RTD1315E_ISO_GPIO_69] = RTK_PIN_CONFIG(gpio_69, 0x58, 20, 1, 2, 0, 3, 4, PADDRI_4_8), 1344 + [RTD1315E_ISO_GPIO_70] = RTK_PIN_CONFIG(gpio_70, 0x58, 25, 1, 2, 0, 3, 4, PADDRI_4_8), 1345 + [RTD1315E_ISO_GPIO_71] = RTK_PIN_CONFIG(gpio_71, 0x5c, 0, 1, 2, 0, 3, 4, PADDRI_4_8), 1346 + [RTD1315E_ISO_GPIO_72] = RTK_PIN_CONFIG(gpio_72, 0x5c, 5, 1, 2, 0, 3, 4, PADDRI_4_8), 1347 + [RTD1315E_ISO_GPIO_78] = RTK_PIN_CONFIG(gpio_78, 0x5c, 10, 0, 1, NA, 2, 12, NA), 1348 + [RTD1315E_ISO_GPIO_79] = RTK_PIN_CONFIG(gpio_79, 0x60, 0, 0, 1, NA, 2, 12, NA), 1349 + [RTD1315E_ISO_GPIO_80] = RTK_PIN_CONFIG(gpio_80, 0x60, 13, 0, 1, NA, 2, 12, NA), 1350 + [RTD1315E_ISO_GPIO_81] = RTK_PIN_CONFIG(gpio_81, 0x64, 0, 0, 1, NA, 2, 12, NA), 1351 + [RTD1315E_ISO_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x64, 13, 0, 1, NA, 2, 12, NA), 1352 + [RTD1315E_ISO_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x68, 0, 0, 1, NA, 2, 12, NA), 1353 + [RTD1315E_ISO_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x68, 13, 0, 1, NA, 2, 12, NA), 1354 + [RTD1315E_ISO_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x68, 26, 0, 1, NA, 2, 12, NA), 1355 + [RTD1315E_ISO_IR_RX] = RTK_PIN_CONFIG(ir_rx, 0x6c, 7, 1, 2, 0, 3, 4, PADDRI_4_8), 1356 + [RTD1315E_ISO_RESET_N] = RTK_PIN_CONFIG(reset_n, 0x6c, 12, 0, 1, NA, 2, 3, PADDRI_4_8), 1357 + [RTD1315E_ISO_SCAN_SWITCH] = RTK_PIN_CONFIG(scan_switch, 0x6c, 16, NA, NA, 0, 1, 2, PADDRI_4_8), 1358 + [RTD1315E_ISO_TESTMODE] = RTK_PIN_CONFIG(testmode, 0x6c, 19, 0, 1, NA, 2, 3, PADDRI_4_8), 1359 + [RTD1315E_ISO_UR0_RX] = RTK_PIN_CONFIG(ur0_rx, 0x6c, 23, 1, 2, 0, 3, 4, PADDRI_4_8), 1360 + [RTD1315E_ISO_UR0_TX] = RTK_PIN_CONFIG(ur0_tx, 0x6c, 28, 1, 2, 0, 3, 4, PADDRI_4_8), 1361 + [RTD1315E_ISO_USB_CC1] = RTK_PIN_CONFIG(usb_cc1, 0x70, 1, NA, NA, 0, 1, 2, PADDRI_4_8), 1362 + [RTD1315E_ISO_USB_CC2] = RTK_PIN_CONFIG(usb_cc2, 0x70, 4, NA, NA, 0, 1, 2, PADDRI_4_8), 1363 + [RTD1315E_ISO_WD_RSET] = RTK_PIN_CONFIG(wd_rset, 0x70, 7, 1, 2, 0, 3, 4, PADDRI_4_8), 1364 + }; 1365 + 1366 + static const struct rtd_pin_sconfig_desc rtd1315e_iso_sconfigs[] = { 1367 + RTK_PIN_SCONFIG(emmc_clk, 0x24, 7, 3, 10, 3, 13, 3), 1368 + RTK_PIN_SCONFIG(emmc_cmd, 0x24, 20, 3, 23, 3, 26, 3), 1369 + RTK_PIN_SCONFIG(emmc_data_0, 0x28, 3, 3, 6, 3, 9, 3), 1370 + RTK_PIN_SCONFIG(emmc_data_1, 0x28, 16, 3, 19, 3, 22, 3), 1371 + RTK_PIN_SCONFIG(emmc_data_2, 0x2c, 3, 3, 6, 3, 9, 3), 1372 + RTK_PIN_SCONFIG(emmc_data_3, 0x2c, 16, 3, 19, 3, 22, 3), 1373 + RTK_PIN_SCONFIG(emmc_data_4, 0x30, 3, 3, 6, 3, 9, 3), 1374 + RTK_PIN_SCONFIG(emmc_data_5, 0x30, 16, 3, 19, 3, 22, 3), 1375 + RTK_PIN_SCONFIG(emmc_data_6, 0x34, 3, 3, 6, 3, 9, 3), 1376 + RTK_PIN_SCONFIG(emmc_data_7, 0x34, 16, 3, 19, 3, 22, 3), 1377 + RTK_PIN_SCONFIG(emmc_dd_sb, 0x38, 3, 3, 6, 3, 9, 3), 1378 + RTK_PIN_SCONFIG(emmc_rst_n, 0x38, 16, 3, 19, 3, 22, 3), 1379 + RTK_PIN_SCONFIG(gpio_32, 0x4c, 8, 3, 11, 3, 14, 3), 1380 + RTK_PIN_SCONFIG(gpio_33, 0x4c, 21, 3, 24, 3, 27, 3), 1381 + RTK_PIN_SCONFIG(gpio_78, 0x5c, 13, 3, 16, 3, 19, 3), 1382 + RTK_PIN_SCONFIG(gpio_79, 0x60, 3, 3, 6, 3, 9, 3), 1383 + RTK_PIN_SCONFIG(gpio_80, 0x60, 16, 3, 19, 3, 22, 3), 1384 + RTK_PIN_SCONFIG(gpio_81, 0x64, 3, 3, 6, 3, 9, 3), 1385 + RTK_PIN_SCONFIG(hif_clk, 0x64, 16, 3, 19, 3, 22, 3), 1386 + RTK_PIN_SCONFIG(hif_data, 0x68, 3, 3, 6, 3, 9, 3), 1387 + RTK_PIN_SCONFIG(hif_en, 0x68, 16, 3, 19, 3, 22, 3), 1388 + RTK_PIN_SCONFIG(hif_rdy, 0x68, 29, 3, 32, 3, 35, 3), 1389 + 1390 + }; 1391 + 1392 + static const struct rtd_pinctrl_desc rtd1315e_iso_pinctrl_desc = { 1393 + .pins = rtd1315e_iso_pins, 1394 + .num_pins = ARRAY_SIZE(rtd1315e_iso_pins), 1395 + .groups = rtd1315e_pin_groups, 1396 + .num_groups = ARRAY_SIZE(rtd1315e_pin_groups), 1397 + .functions = rtd1315e_pin_functions, 1398 + .num_functions = ARRAY_SIZE(rtd1315e_pin_functions), 1399 + .muxes = rtd1315e_iso_muxes, 1400 + .num_muxes = ARRAY_SIZE(rtd1315e_iso_muxes), 1401 + .configs = rtd1315e_iso_configs, 1402 + .num_configs = ARRAY_SIZE(rtd1315e_iso_configs), 1403 + .sconfigs = rtd1315e_iso_sconfigs, 1404 + .num_sconfigs = ARRAY_SIZE(rtd1315e_iso_sconfigs), 1405 + }; 1406 + 1407 + static int rtd1315e_pinctrl_probe(struct platform_device *pdev) 1408 + { 1409 + return rtd_pinctrl_probe(pdev, &rtd1315e_iso_pinctrl_desc); 1410 + } 1411 + 1412 + static const struct of_device_id rtd1315e_pinctrl_of_match[] = { 1413 + { .compatible = "realtek,rtd1315e-pinctrl", }, 1414 + {}, 1415 + }; 1416 + 1417 + static struct platform_driver rtd1315e_pinctrl_driver = { 1418 + .driver = { 1419 + .name = "rtd1315e-pinctrl", 1420 + .of_match_table = rtd1315e_pinctrl_of_match, 1421 + }, 1422 + .probe = rtd1315e_pinctrl_probe, 1423 + }; 1424 + 1425 + static int __init rtd1315e_pinctrl_init(void) 1426 + { 1427 + return platform_driver_register(&rtd1315e_pinctrl_driver); 1428 + } 1429 + arch_initcall(rtd1315e_pinctrl_init); 1430 + 1431 + static void __exit rtd1315e_pinctrl_exit(void) 1432 + { 1433 + platform_driver_unregister(&rtd1315e_pinctrl_driver); 1434 + } 1435 + module_exit(rtd1315e_pinctrl_exit); 1436 + 1437 + MODULE_LICENSE("GPL"); 1438 + MODULE_AUTHOR("Realtek Semiconductor Corporation"); 1439 + MODULE_DESCRIPTION("Realtek DHC SoC RTD1315E pinctrl driver");