tjh.dev / kernel
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clk: qcom: gcc-sm8650: Don't use shared clk_ops for QUPs

The QUPs aren't shared in a way that requires parking the RCG at an
always on parent in case some other entity turns on the clk. The
hardware is capable of setting a new frequency itself with the DFS mode,
so parking is unnecessary. Furthermore, there aren't any GDSCs for these
devices, so there isn't a possibility of the GDSC turning on the clks
for housekeeping purposes.

Like for the SM8550 GCC QUP clocks at [1], do not use shared clk_ops for QUPs.

[1] https://lore.kernel.org/all/20240827231237.1014813-3-swboyd@chromium.org/

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240829-topic-sm8650-upstream-fix-qup-clk-rcg-shared-v1-1-7ecdbc672187@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by Neil Armstrong and committed by Stephen Boyd aa2eb2c4 7b6dfa1b

+28 -28
unified split
+28 -28
drivers/clk/qcom/gcc-sm8650.c
··· 713 713 .parent_data = gcc_parent_data_0, 714 714 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 715 715 .flags = CLK_SET_RATE_PARENT, 716 - .ops = &clk_rcg2_shared_ops, 716 + .ops = &clk_rcg2_ops, 717 717 }, 718 718 }; 719 719 ··· 728 728 .parent_data = gcc_parent_data_0, 729 729 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 730 730 .flags = CLK_SET_RATE_PARENT, 731 - .ops = &clk_rcg2_shared_ops, 731 + .ops = &clk_rcg2_ops, 732 732 }, 733 733 }; 734 734 ··· 743 743 .parent_data = gcc_parent_data_0, 744 744 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 745 745 .flags = CLK_SET_RATE_PARENT, 746 - .ops = &clk_rcg2_shared_ops, 746 + .ops = &clk_rcg2_ops, 747 747 }, 748 748 }; 749 749 ··· 758 758 .parent_data = gcc_parent_data_0, 759 759 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 760 760 .flags = CLK_SET_RATE_PARENT, 761 - .ops = &clk_rcg2_shared_ops, 761 + .ops = &clk_rcg2_ops, 762 762 }, 763 763 }; 764 764 ··· 773 773 .parent_data = gcc_parent_data_0, 774 774 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 775 775 .flags = CLK_SET_RATE_PARENT, 776 - .ops = &clk_rcg2_shared_ops, 776 + .ops = &clk_rcg2_ops, 777 777 }, 778 778 }; 779 779 ··· 788 788 .parent_data = gcc_parent_data_0, 789 789 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 790 790 .flags = CLK_SET_RATE_PARENT, 791 - .ops = &clk_rcg2_shared_ops, 791 + .ops = &clk_rcg2_ops, 792 792 }, 793 793 }; 794 794 ··· 803 803 .parent_data = gcc_parent_data_0, 804 804 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 805 805 .flags = CLK_SET_RATE_PARENT, 806 - .ops = &clk_rcg2_shared_ops, 806 + .ops = &clk_rcg2_ops, 807 807 }, 808 808 }; 809 809 ··· 818 818 .parent_data = gcc_parent_data_0, 819 819 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 820 820 .flags = CLK_SET_RATE_PARENT, 821 - .ops = &clk_rcg2_shared_ops, 821 + .ops = &clk_rcg2_ops, 822 822 }, 823 823 }; 824 824 ··· 833 833 .parent_data = gcc_parent_data_0, 834 834 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 835 835 .flags = CLK_SET_RATE_PARENT, 836 - .ops = &clk_rcg2_shared_ops, 836 + .ops = &clk_rcg2_ops, 837 837 }, 838 838 }; 839 839 ··· 848 848 .parent_data = gcc_parent_data_0, 849 849 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 850 850 .flags = CLK_SET_RATE_PARENT, 851 - .ops = &clk_rcg2_shared_ops, 851 + .ops = &clk_rcg2_ops, 852 852 }, 853 853 }; 854 854 ··· 863 863 .parent_data = gcc_parent_data_0, 864 864 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 865 865 .flags = CLK_SET_RATE_PARENT, 866 - .ops = &clk_rcg2_shared_ops, 866 + .ops = &clk_rcg2_ops, 867 867 }; 868 868 869 869 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = { ··· 899 899 .parent_data = gcc_parent_data_0, 900 900 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 901 901 .flags = CLK_SET_RATE_PARENT, 902 - .ops = &clk_rcg2_shared_ops, 902 + .ops = &clk_rcg2_ops, 903 903 }; 904 904 905 905 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { ··· 916 916 .parent_data = gcc_parent_data_0, 917 917 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 918 918 .flags = CLK_SET_RATE_PARENT, 919 - .ops = &clk_rcg2_shared_ops, 919 + .ops = &clk_rcg2_ops, 920 920 }; 921 921 922 922 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { ··· 948 948 .parent_data = gcc_parent_data_0, 949 949 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 950 950 .flags = CLK_SET_RATE_PARENT, 951 - .ops = &clk_rcg2_shared_ops, 951 + .ops = &clk_rcg2_ops, 952 952 }; 953 953 954 954 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { ··· 980 980 .parent_data = gcc_parent_data_0, 981 981 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 982 982 .flags = CLK_SET_RATE_PARENT, 983 - .ops = &clk_rcg2_shared_ops, 983 + .ops = &clk_rcg2_ops, 984 984 }; 985 985 986 986 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { ··· 997 997 .parent_data = gcc_parent_data_0, 998 998 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 999 999 .flags = CLK_SET_RATE_PARENT, 1000 - .ops = &clk_rcg2_shared_ops, 1000 + .ops = &clk_rcg2_ops, 1001 1001 }; 1002 1002 1003 1003 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { ··· 1014 1014 .parent_data = gcc_parent_data_0, 1015 1015 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1016 1016 .flags = CLK_SET_RATE_PARENT, 1017 - .ops = &clk_rcg2_shared_ops, 1017 + .ops = &clk_rcg2_ops, 1018 1018 }; 1019 1019 1020 1020 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { ··· 1031 1031 .parent_data = gcc_parent_data_0, 1032 1032 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1033 1033 .flags = CLK_SET_RATE_PARENT, 1034 - .ops = &clk_rcg2_shared_ops, 1034 + .ops = &clk_rcg2_ops, 1035 1035 }; 1036 1036 1037 1037 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { ··· 1059 1059 .parent_data = gcc_parent_data_2, 1060 1060 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1061 1061 .flags = CLK_SET_RATE_PARENT, 1062 - .ops = &clk_rcg2_shared_ops, 1062 + .ops = &clk_rcg2_ops, 1063 1063 }, 1064 1064 }; 1065 1065 ··· 1068 1068 .parent_data = gcc_parent_data_0, 1069 1069 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1070 1070 .flags = CLK_SET_RATE_PARENT, 1071 - .ops = &clk_rcg2_shared_ops, 1071 + .ops = &clk_rcg2_ops, 1072 1072 }; 1073 1073 1074 1074 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { ··· 1085 1085 .parent_data = gcc_parent_data_0, 1086 1086 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1087 1087 .flags = CLK_SET_RATE_PARENT, 1088 - .ops = &clk_rcg2_shared_ops, 1088 + .ops = &clk_rcg2_ops, 1089 1089 }; 1090 1090 1091 1091 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { ··· 1102 1102 .parent_data = gcc_parent_data_0, 1103 1103 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1104 1104 .flags = CLK_SET_RATE_PARENT, 1105 - .ops = &clk_rcg2_shared_ops, 1105 + .ops = &clk_rcg2_ops, 1106 1106 }; 1107 1107 1108 1108 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { ··· 1119 1119 .parent_data = gcc_parent_data_0, 1120 1120 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1121 1121 .flags = CLK_SET_RATE_PARENT, 1122 - .ops = &clk_rcg2_shared_ops, 1122 + .ops = &clk_rcg2_ops, 1123 1123 }; 1124 1124 1125 1125 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { ··· 1136 1136 .parent_data = gcc_parent_data_0, 1137 1137 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1138 1138 .flags = CLK_SET_RATE_PARENT, 1139 - .ops = &clk_rcg2_shared_ops, 1139 + .ops = &clk_rcg2_ops, 1140 1140 }; 1141 1141 1142 1142 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { ··· 1153 1153 .parent_data = gcc_parent_data_0, 1154 1154 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1155 1155 .flags = CLK_SET_RATE_PARENT, 1156 - .ops = &clk_rcg2_shared_ops, 1156 + .ops = &clk_rcg2_ops, 1157 1157 }; 1158 1158 1159 1159 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { ··· 1186 1186 .parent_data = gcc_parent_data_10, 1187 1187 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 1188 1188 .flags = CLK_SET_RATE_PARENT, 1189 - .ops = &clk_rcg2_shared_ops, 1189 + .ops = &clk_rcg2_ops, 1190 1190 }; 1191 1191 1192 1192 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { ··· 1203 1203 .parent_data = gcc_parent_data_0, 1204 1204 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1205 1205 .flags = CLK_SET_RATE_PARENT, 1206 - .ops = &clk_rcg2_shared_ops, 1206 + .ops = &clk_rcg2_ops, 1207 1207 }; 1208 1208 1209 1209 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { ··· 1226 1226 .parent_data = gcc_parent_data_0, 1227 1227 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1228 1228 .flags = CLK_SET_RATE_PARENT, 1229 - .ops = &clk_rcg2_shared_ops, 1229 + .ops = &clk_rcg2_ops, 1230 1230 }; 1231 1231 1232 1232 static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src = {