tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
soc: mediatek: mmsys: Migrate all tables to MMSYS_ROUTE() macro
Now that all of the mmsys routing tables have been fixed,
migrate all of them to use the MMSYS_ROUTE() macro: this
will make sure that future additions to any of the tables
for the currently supported SoCs are compile-time sanity
checked, greatly reducing room for (way too common) mistakes.
Link: https://lore.kernel.org/r/20250212100012.33001-8-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+442
-606
+15
-21
drivers/soc/mediatek/mt8167-mmsys.h
+15
-21
drivers/soc/mediatek/mt8167-mmsys.h
···
14
14
#define MT8167_DSI0_SEL_IN_RDMA0 0x1
15
15
16
16
static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
17
-
{
18
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
19
-
MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
20
-
OVL0_MOUT_EN_COLOR0
21
-
}, {
22
-
DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
23
-
MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0,
24
-
MT8167_DITHER_MOUT_EN_RDMA0
25
-
}, {
26
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
27
-
MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
28
-
COLOR0_SEL_IN_OVL0
29
-
}, {
30
-
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
31
-
MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0,
32
-
MT8167_DSI0_SEL_IN_RDMA0
33
-
}, {
34
-
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
35
-
MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0,
36
-
MT8167_RDMA0_SOUT_DSI0
37
-
},
17
+
MMSYS_ROUTE(OVL0, COLOR0,
18
+
MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
19
+
OVL0_MOUT_EN_COLOR0),
20
+
MMSYS_ROUTE(DITHER0, RDMA0,
21
+
MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0,
22
+
MT8167_DITHER_MOUT_EN_RDMA0),
23
+
MMSYS_ROUTE(OVL0, COLOR0,
24
+
MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
25
+
COLOR0_SEL_IN_OVL0),
26
+
MMSYS_ROUTE(RDMA0, DSI0,
27
+
MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0,
28
+
MT8167_DSI0_SEL_IN_RDMA0),
29
+
MMSYS_ROUTE(RDMA0, DSI0,
30
+
MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0,
31
+
MT8167_RDMA0_SOUT_DSI0),
38
32
};
39
33
40
34
#endif /* __SOC_MEDIATEK_MT8167_MMSYS_H */
+42
-57
drivers/soc/mediatek/mt8173-mmsys.h
+42
-57
drivers/soc/mediatek/mt8173-mmsys.h
···
33
33
#define MT8173_RDMA0_SOUT_COLOR0 BIT(0)
34
34
35
35
static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
36
-
{
37
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
38
-
MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
39
-
MT8173_OVL0_MOUT_EN_COLOR0, MT8173_OVL0_MOUT_EN_COLOR0
40
-
}, {
41
-
DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
42
-
MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN,
43
-
MT8173_OD0_MOUT_EN_RDMA0, MT8173_OD0_MOUT_EN_RDMA0
44
-
}, {
45
-
DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
46
-
MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN,
47
-
MT8173_UFOE_MOUT_EN_DSI0, MT8173_UFOE_MOUT_EN_DSI0
48
-
}, {
49
-
DDP_COMPONENT_COLOR0, DDP_COMPONENT_AAL0,
50
-
MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN,
51
-
MT8173_COLOR0_SOUT_MERGE, 0 /* SOUT to AAL */
52
-
}, {
53
-
DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,
54
-
MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN,
55
-
MT8173_RDMA0_SOUT_COLOR0, 0 /* SOUT to UFOE */
56
-
}, {
57
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
58
-
MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
59
-
MT8173_COLOR0_SEL_IN_OVL0, MT8173_COLOR0_SEL_IN_OVL0
60
-
}, {
61
-
DDP_COMPONENT_AAL0, DDP_COMPONENT_COLOR0,
62
-
MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN,
63
-
MT8173_AAL_SEL_IN_MERGE, 0 /* SEL_IN from COLOR0 */
64
-
}, {
65
-
DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,
66
-
MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN,
67
-
MT8173_UFOE_SEL_IN_RDMA0, 0 /* SEL_IN from RDMA0 */
68
-
}, {
69
-
DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
70
-
MT8173_DISP_REG_CONFIG_DSI0_SEL_IN,
71
-
MT8173_DSI0_SEL_IN_UFOE, 0, /* SEL_IN from UFOE */
72
-
}, {
73
-
DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
74
-
MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN,
75
-
MT8173_OVL1_MOUT_EN_COLOR1, MT8173_OVL1_MOUT_EN_COLOR1
76
-
}, {
77
-
DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
78
-
MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN,
79
-
MT8173_GAMMA_MOUT_EN_RDMA1, MT8173_GAMMA_MOUT_EN_RDMA1
80
-
}, {
81
-
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
82
-
MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN,
83
-
RDMA1_SOUT_MASK, RDMA1_SOUT_DPI0
84
-
}, {
85
-
DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
86
-
MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN,
87
-
COLOR1_SEL_IN_OVL1, COLOR1_SEL_IN_OVL1
88
-
}, {
89
-
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
90
-
MT8173_DISP_REG_CONFIG_DPI_SEL_IN,
91
-
MT8173_DPI0_SEL_IN_MASK, MT8173_DPI0_SEL_IN_RDMA1
92
-
}
36
+
MMSYS_ROUTE(OVL0, COLOR0,
37
+
MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8173_OVL0_MOUT_EN_COLOR0,
38
+
MT8173_OVL0_MOUT_EN_COLOR0),
39
+
MMSYS_ROUTE(OD0, RDMA0,
40
+
MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN, MT8173_OD0_MOUT_EN_RDMA0,
41
+
MT8173_OD0_MOUT_EN_RDMA0),
42
+
MMSYS_ROUTE(UFOE, DSI0,
43
+
MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8173_UFOE_MOUT_EN_DSI0,
44
+
MT8173_UFOE_MOUT_EN_DSI0),
45
+
MMSYS_ROUTE(COLOR0, AAL0,
46
+
MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN, MT8173_COLOR0_SOUT_MERGE,
47
+
0 /* SOUT to AAL */),
48
+
MMSYS_ROUTE(RDMA0, UFOE,
49
+
MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8173_RDMA0_SOUT_COLOR0,
50
+
0 /* SOUT to UFOE */),
51
+
MMSYS_ROUTE(OVL0, COLOR0,
52
+
MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8173_COLOR0_SEL_IN_OVL0,
53
+
MT8173_COLOR0_SEL_IN_OVL0),
54
+
MMSYS_ROUTE(AAL0, COLOR0,
55
+
MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN, MT8173_AAL_SEL_IN_MERGE,
56
+
0 /* SEL_IN from COLOR0 */),
57
+
MMSYS_ROUTE(RDMA0, UFOE,
58
+
MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, MT8173_UFOE_SEL_IN_RDMA0,
59
+
0 /* SEL_IN from RDMA0 */),
60
+
MMSYS_ROUTE(UFOE, DSI0,
61
+
MT8173_DISP_REG_CONFIG_DSI0_SEL_IN, MT8173_DSI0_SEL_IN_UFOE,
62
+
0 /* SEL_IN from UFOE */),
63
+
MMSYS_ROUTE(OVL1, COLOR1,
64
+
MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, MT8173_OVL1_MOUT_EN_COLOR1,
65
+
MT8173_OVL1_MOUT_EN_COLOR1),
66
+
MMSYS_ROUTE(GAMMA, RDMA1,
67
+
MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, MT8173_GAMMA_MOUT_EN_RDMA1,
68
+
MT8173_GAMMA_MOUT_EN_RDMA1),
69
+
MMSYS_ROUTE(RDMA1, DPI0,
70
+
MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
71
+
RDMA1_SOUT_DPI0),
72
+
MMSYS_ROUTE(OVL1, COLOR1,
73
+
MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
74
+
COLOR1_SEL_IN_OVL1),
75
+
MMSYS_ROUTE(RDMA1, DPI0,
76
+
MT8173_DISP_REG_CONFIG_DPI_SEL_IN, MT8173_DPI0_SEL_IN_MASK,
77
+
MT8173_DPI0_SEL_IN_RDMA1),
93
78
};
94
79
95
80
#endif /* __SOC_MEDIATEK_MT8173_MMSYS_H */
+21
-29
drivers/soc/mediatek/mt8183-mmsys.h
+21
-29
drivers/soc/mediatek/mt8183-mmsys.h
···
28
28
#define MT8183_MMSYS_SW0_RST_B 0x140
29
29
30
30
static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
31
-
{
32
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
33
-
MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
34
-
MT8183_OVL0_MOUT_EN_OVL0_2L
35
-
}, {
36
-
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
37
-
MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
38
-
MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
39
-
}, {
40
-
DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
41
-
MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
42
-
MT8183_OVL1_2L_MOUT_EN_RDMA1
43
-
}, {
44
-
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
45
-
MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
46
-
MT8183_DITHER0_MOUT_IN_DSI0
47
-
}, {
48
-
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
49
-
MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
50
-
MT8183_DISP_PATH0_SEL_IN_OVL0_2L
51
-
}, {
52
-
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
53
-
MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
54
-
MT8183_DPI0_SEL_IN_RDMA1
55
-
}, {
56
-
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
57
-
MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
58
-
MT8183_RDMA0_SOUT_COLOR0
59
-
}
31
+
MMSYS_ROUTE(OVL0, OVL_2L0,
32
+
MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
33
+
MT8183_OVL0_MOUT_EN_OVL0_2L),
34
+
MMSYS_ROUTE(OVL_2L0, RDMA0,
35
+
MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
36
+
MT8183_OVL0_2L_MOUT_EN_DISP_PATH0),
37
+
MMSYS_ROUTE(OVL_2L1, RDMA1,
38
+
MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
39
+
MT8183_OVL1_2L_MOUT_EN_RDMA1),
40
+
MMSYS_ROUTE(DITHER0, DSI0,
41
+
MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
42
+
MT8183_DITHER0_MOUT_IN_DSI0),
43
+
MMSYS_ROUTE(OVL_2L0, RDMA0,
44
+
MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
45
+
MT8183_DISP_PATH0_SEL_IN_OVL0_2L),
46
+
MMSYS_ROUTE(RDMA1, DPI0,
47
+
MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
48
+
MT8183_DPI0_SEL_IN_RDMA1),
49
+
MMSYS_ROUTE(RDMA0, COLOR0,
50
+
MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
51
+
MT8183_RDMA0_SOUT_COLOR0),
60
52
};
61
53
62
54
#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
+33
-55
drivers/soc/mediatek/mt8186-mmsys.h
+33
-55
drivers/soc/mediatek/mt8186-mmsys.h
···
63
63
#define MT8186_MMSYS_SW0_RST_B 0x160
64
64
65
65
static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
66
-
{
67
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
68
-
MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
69
-
MT8186_OVL0_MOUT_TO_RDMA0
70
-
},
71
-
{
72
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
73
-
MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
74
-
MT8186_RDMA0_FROM_OVL0
75
-
},
76
-
{
77
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
78
-
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
79
-
MT8186_OVL0_GO_BLEND
80
-
},
81
-
{
82
-
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
83
-
MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
84
-
MT8186_RDMA0_SOUT_TO_COLOR0
85
-
},
86
-
{
87
-
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
88
-
MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
89
-
MT8186_DITHER0_MOUT_TO_DSI0,
90
-
},
91
-
{
92
-
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
93
-
MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
94
-
MT8186_DSI0_FROM_DITHER0
95
-
},
96
-
{
97
-
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
98
-
MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
99
-
MT8186_OVL0_2L_MOUT_TO_RDMA1
100
-
},
101
-
{
102
-
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
103
-
MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
104
-
MT8186_RDMA1_FROM_OVL0_2L
105
-
},
106
-
{
107
-
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
108
-
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
109
-
MT8186_OVL0_2L_GO_BLEND
110
-
},
111
-
{
112
-
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
113
-
MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
114
-
MT8186_RDMA1_MOUT_TO_DPI0_SEL
115
-
},
116
-
{
117
-
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
118
-
MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
119
-
MT8186_DPI0_FROM_RDMA1
120
-
},
66
+
MMSYS_ROUTE(OVL0, RDMA0,
67
+
MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
68
+
MT8186_OVL0_MOUT_TO_RDMA0),
69
+
MMSYS_ROUTE(OVL0, RDMA0,
70
+
MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
71
+
MT8186_RDMA0_FROM_OVL0),
72
+
MMSYS_ROUTE(OVL0, RDMA0,
73
+
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
74
+
MT8186_OVL0_GO_BLEND),
75
+
MMSYS_ROUTE(RDMA0, COLOR0,
76
+
MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
77
+
MT8186_RDMA0_SOUT_TO_COLOR0),
78
+
MMSYS_ROUTE(DITHER0, DSI0,
79
+
MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
80
+
MT8186_DITHER0_MOUT_TO_DSI0),
81
+
MMSYS_ROUTE(DITHER0, DSI0,
82
+
MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
83
+
MT8186_DSI0_FROM_DITHER0),
84
+
MMSYS_ROUTE(OVL_2L0, RDMA1,
85
+
MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
86
+
MT8186_OVL0_2L_MOUT_TO_RDMA1),
87
+
MMSYS_ROUTE(OVL_2L0, RDMA1,
88
+
MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
89
+
MT8186_RDMA1_FROM_OVL0_2L),
90
+
MMSYS_ROUTE(OVL_2L0, RDMA1,
91
+
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
92
+
MT8186_OVL0_2L_GO_BLEND),
93
+
MMSYS_ROUTE(RDMA1, DPI0,
94
+
MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
95
+
MT8186_RDMA1_MOUT_TO_DPI0_SEL),
96
+
MMSYS_ROUTE(RDMA1, DPI0,
97
+
MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
98
+
MT8186_DPI0_FROM_RDMA1),
121
99
};
122
100
123
101
#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */
+30
-41
drivers/soc/mediatek/mt8192-mmsys.h
+30
-41
drivers/soc/mediatek/mt8192-mmsys.h
···
31
31
#define MT8192_DSI0_SEL_IN_DITHER0 0x1
32
32
33
33
static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
34
-
{
35
-
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
36
-
MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
37
-
MT8192_OVL0_MOUT_EN_DISP_RDMA0
38
-
}, {
39
-
DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
40
-
MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
41
-
MT8192_OVL2_2L_MOUT_EN_RDMA4
42
-
}, {
43
-
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
44
-
MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
45
-
MT8192_DITHER0_MOUT_IN_DSI0
46
-
}, {
47
-
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
48
-
MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
49
-
MT8192_RDMA0_SEL_IN_OVL0_2L
50
-
}, {
51
-
DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
52
-
MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
53
-
MT8192_AAL0_SEL_IN_CCORR0
54
-
}, {
55
-
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
56
-
MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
57
-
MT8192_DSI0_SEL_IN_DITHER0
58
-
}, {
59
-
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
60
-
MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
61
-
MT8192_RDMA0_SOUT_COLOR0
62
-
}, {
63
-
DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
64
-
MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
65
-
MT8192_CCORR0_SOUT_AAL0
66
-
}, {
67
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
68
-
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
69
-
MT8192_DISP_OVL0_GO_BG
70
-
}, {
71
-
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
72
-
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
73
-
MT8192_DISP_OVL0_2L_GO_BLEND
74
-
}
34
+
MMSYS_ROUTE(OVL_2L0, RDMA0,
35
+
MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
36
+
MT8192_OVL0_MOUT_EN_DISP_RDMA0),
37
+
MMSYS_ROUTE(OVL_2L2, RDMA4,
38
+
MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
39
+
MT8192_OVL2_2L_MOUT_EN_RDMA4),
40
+
MMSYS_ROUTE(DITHER0, DSI0,
41
+
MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
42
+
MT8192_DITHER0_MOUT_IN_DSI0),
43
+
MMSYS_ROUTE(OVL_2L0, RDMA0,
44
+
MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
45
+
MT8192_RDMA0_SEL_IN_OVL0_2L),
46
+
MMSYS_ROUTE(CCORR, AAL0,
47
+
MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
48
+
MT8192_AAL0_SEL_IN_CCORR0),
49
+
MMSYS_ROUTE(DITHER0, DSI0,
50
+
MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
51
+
MT8192_DSI0_SEL_IN_DITHER0),
52
+
MMSYS_ROUTE(RDMA0, COLOR0,
53
+
MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
54
+
MT8192_RDMA0_SOUT_COLOR0),
55
+
MMSYS_ROUTE(CCORR, AAL0,
56
+
MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
57
+
MT8192_CCORR0_SOUT_AAL0),
58
+
MMSYS_ROUTE(OVL0, OVL_2L0,
59
+
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
60
+
MT8192_DISP_OVL0_GO_BG),
61
+
MMSYS_ROUTE(OVL_2L0, RDMA0,
62
+
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
63
+
MT8192_DISP_OVL0_2L_GO_BLEND),
75
64
};
76
65
77
66
#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */
+270
-362
drivers/soc/mediatek/mt8195-mmsys.h
+270
-362
drivers/soc/mediatek/mt8195-mmsys.h
···
160
160
#define MT8195_SVPP3_MDP_RSZ BIT(5)
161
161
162
162
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
163
-
{
164
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
165
-
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
166
-
MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
167
-
}, {
168
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
169
-
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
170
-
MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
171
-
}, {
172
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
173
-
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
174
-
MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
175
-
}, {
176
-
DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
177
-
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
178
-
MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
179
-
}, {
180
-
DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
181
-
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
182
-
MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
183
-
}, {
184
-
DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
185
-
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
186
-
MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
187
-
}, {
188
-
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
189
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
190
-
MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
191
-
}, {
192
-
DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
193
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
194
-
MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
195
-
}, {
196
-
DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
197
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
198
-
MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
199
-
}, {
200
-
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
201
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
202
-
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
203
-
}, {
204
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
205
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
206
-
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
207
-
}, {
208
-
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
209
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
210
-
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
211
-
}, {
212
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
213
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
214
-
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
215
-
}, {
216
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
217
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
218
-
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
219
-
}, {
220
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
221
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
222
-
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
223
-
}, {
224
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
225
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
226
-
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
227
-
}, {
228
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
229
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
230
-
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
231
-
}, {
232
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
233
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
234
-
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
235
-
}, {
236
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
237
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
238
-
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
239
-
}, {
240
-
DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
241
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
242
-
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
243
-
}, {
244
-
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
245
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
246
-
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
247
-
}, {
248
-
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
249
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
250
-
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
251
-
}, {
252
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
253
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
254
-
MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
255
-
}, {
256
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
257
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
258
-
MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
259
-
}, {
260
-
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
261
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
262
-
MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
263
-
}, {
264
-
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
265
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
266
-
MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
267
-
}, {
268
-
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
269
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
270
-
MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
271
-
}, {
272
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
273
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
274
-
MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
275
-
}, {
276
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
277
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
278
-
MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
279
-
}, {
280
-
DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
281
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
282
-
MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
283
-
}, {
284
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
285
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
286
-
MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
287
-
}, {
288
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
289
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
290
-
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
291
-
}, {
292
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
293
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
294
-
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
295
-
}, {
296
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
297
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
298
-
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
299
-
}, {
300
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
301
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
302
-
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
303
-
}, {
304
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
305
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
306
-
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
307
-
}, {
308
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
309
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
310
-
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
311
-
}, {
312
-
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
313
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
314
-
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
315
-
}, {
316
-
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
317
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
318
-
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
319
-
}, {
320
-
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
321
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
322
-
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
323
-
}, {
324
-
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
325
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
326
-
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
327
-
}, {
328
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
329
-
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
330
-
MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
331
-
}, {
332
-
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
333
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
334
-
MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
335
-
}, {
336
-
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
337
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
338
-
MT8195_SOUT_DISP_DITHER0_TO_DSI0
339
-
}, {
340
-
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
341
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
342
-
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
343
-
}, {
344
-
DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
345
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
346
-
MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
347
-
}, {
348
-
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
349
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
350
-
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
351
-
}, {
352
-
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
353
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
354
-
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
355
-
}, {
356
-
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
357
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
358
-
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
359
-
}, {
360
-
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
361
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
362
-
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
363
-
}, {
364
-
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
365
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
366
-
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
367
-
}, {
368
-
DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
369
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
370
-
MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
371
-
}, {
372
-
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
373
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
374
-
MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
375
-
}, {
376
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
377
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
378
-
MT8195_SOUT_VPP_MERGE_TO_DSI1
379
-
}, {
380
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
381
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
382
-
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
383
-
}, {
384
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
385
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
386
-
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
387
-
}, {
388
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
389
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
390
-
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
391
-
}, {
392
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
393
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
394
-
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
395
-
}, {
396
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
397
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
398
-
MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
399
-
}, {
400
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
401
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
402
-
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
403
-
}, {
404
-
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
405
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
406
-
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
407
-
}, {
408
-
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
409
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
410
-
MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
411
-
}, {
412
-
DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
413
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
414
-
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
415
-
}, {
416
-
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
417
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
418
-
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
419
-
}, {
420
-
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
421
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
422
-
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
423
-
}, {
424
-
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
425
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
426
-
MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
427
-
}, {
428
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
429
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
430
-
MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
431
-
}, {
432
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
433
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
434
-
MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
435
-
}, {
436
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
437
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
438
-
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
439
-
}, {
440
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
441
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
442
-
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
443
-
}, {
444
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
445
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
446
-
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
447
-
}, {
448
-
DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
449
-
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
450
-
MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
451
-
}
163
+
MMSYS_ROUTE(OVL0, RDMA0,
164
+
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
165
+
MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0),
166
+
MMSYS_ROUTE(OVL0, WDMA0,
167
+
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
168
+
MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0),
169
+
MMSYS_ROUTE(OVL0, OVL1,
170
+
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
171
+
MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1),
172
+
MMSYS_ROUTE(OVL1, RDMA1,
173
+
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
174
+
MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1),
175
+
MMSYS_ROUTE(OVL1, WDMA1,
176
+
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
177
+
MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1),
178
+
MMSYS_ROUTE(OVL1, OVL0,
179
+
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
180
+
MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0),
181
+
MMSYS_ROUTE(DSC0, MERGE0,
182
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
183
+
MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT),
184
+
MMSYS_ROUTE(DITHER1, MERGE0,
185
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
186
+
MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1),
187
+
MMSYS_ROUTE(MERGE5, MERGE0,
188
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
189
+
MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0),
190
+
MMSYS_ROUTE(DITHER0, DSC0,
191
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
192
+
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0),
193
+
MMSYS_ROUTE(MERGE0, DSC0,
194
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
195
+
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE),
196
+
MMSYS_ROUTE(DITHER1, DSC1,
197
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
198
+
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1),
199
+
MMSYS_ROUTE(MERGE0, DSC1,
200
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
201
+
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE),
202
+
MMSYS_ROUTE(MERGE0, DP_INTF1,
203
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
204
+
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
205
+
MMSYS_ROUTE(MERGE0, DPI0,
206
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
207
+
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
208
+
MMSYS_ROUTE(MERGE0, DPI1,
209
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
210
+
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
211
+
MMSYS_ROUTE(DSC1, DP_INTF1,
212
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
213
+
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
214
+
MMSYS_ROUTE(DSC1, DPI0,
215
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
216
+
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
217
+
MMSYS_ROUTE(DSC1, DPI1,
218
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
219
+
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
220
+
MMSYS_ROUTE(DSC0, DP_INTF1,
221
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
222
+
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
223
+
MMSYS_ROUTE(DSC0, DPI0,
224
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
225
+
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
226
+
MMSYS_ROUTE(DSC0, DPI1,
227
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
228
+
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
229
+
MMSYS_ROUTE(DSC1, DP_INTF0,
230
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
231
+
MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT),
232
+
MMSYS_ROUTE(MERGE0, DP_INTF0,
233
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
234
+
MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE),
235
+
MMSYS_ROUTE(MERGE5, DP_INTF0,
236
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
237
+
MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0),
238
+
MMSYS_ROUTE(DSC0, DSI0,
239
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
240
+
MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT),
241
+
MMSYS_ROUTE(DITHER0, DSI0,
242
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
243
+
MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0),
244
+
MMSYS_ROUTE(DSC1, DSI1,
245
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
246
+
MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT),
247
+
MMSYS_ROUTE(MERGE0, DSI1,
248
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
249
+
MT8195_SEL_IN_DSI1_FROM_VPP_MERGE),
250
+
MMSYS_ROUTE(OVL1, WDMA1,
251
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
252
+
MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1),
253
+
MMSYS_ROUTE(MERGE0, WDMA1,
254
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
255
+
MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE),
256
+
MMSYS_ROUTE(DSC1, DSI1,
257
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
258
+
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
259
+
MMSYS_ROUTE(DSC1, DP_INTF0,
260
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
261
+
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
262
+
MMSYS_ROUTE(DSC1, DP_INTF1,
263
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
264
+
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
265
+
MMSYS_ROUTE(DSC1, DPI0,
266
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
267
+
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
268
+
MMSYS_ROUTE(DSC1, DPI1,
269
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
270
+
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
271
+
MMSYS_ROUTE(DSC1, MERGE0,
272
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
273
+
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
274
+
MMSYS_ROUTE(DITHER1, DSI1,
275
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
276
+
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
277
+
MMSYS_ROUTE(DITHER1, DP_INTF0,
278
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
279
+
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
280
+
MMSYS_ROUTE(DITHER1, DPI0,
281
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
282
+
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
283
+
MMSYS_ROUTE(DITHER1, DPI1,
284
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
285
+
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
286
+
MMSYS_ROUTE(OVL0, WDMA0,
287
+
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
288
+
MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0),
289
+
MMSYS_ROUTE(DITHER0, DSC0,
290
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
291
+
MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN),
292
+
MMSYS_ROUTE(DITHER0, DSI0,
293
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
294
+
MT8195_SOUT_DISP_DITHER0_TO_DSI0),
295
+
MMSYS_ROUTE(DITHER1, DSC1,
296
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
297
+
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN),
298
+
MMSYS_ROUTE(DITHER1, MERGE0,
299
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
300
+
MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE),
301
+
MMSYS_ROUTE(DITHER1, DSI1,
302
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
303
+
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
304
+
MMSYS_ROUTE(DITHER1, DP_INTF0,
305
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
306
+
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
307
+
MMSYS_ROUTE(DITHER1, DP_INTF1,
308
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
309
+
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
310
+
MMSYS_ROUTE(DITHER1, DPI0,
311
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
312
+
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
313
+
MMSYS_ROUTE(DITHER1, DPI1,
314
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
315
+
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
316
+
MMSYS_ROUTE(MERGE5, MERGE0,
317
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
318
+
MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE),
319
+
MMSYS_ROUTE(MERGE5, DP_INTF0,
320
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
321
+
MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0),
322
+
MMSYS_ROUTE(MERGE0, DSI1,
323
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
324
+
MT8195_SOUT_VPP_MERGE_TO_DSI1),
325
+
MMSYS_ROUTE(MERGE0, DP_INTF0,
326
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
327
+
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0),
328
+
MMSYS_ROUTE(MERGE0, DP_INTF1,
329
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
330
+
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
331
+
MMSYS_ROUTE(MERGE0, DPI0,
332
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
333
+
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
334
+
MMSYS_ROUTE(MERGE0, DPI1,
335
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
336
+
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
337
+
MMSYS_ROUTE(MERGE0, WDMA1,
338
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
339
+
MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1),
340
+
MMSYS_ROUTE(MERGE0, DSC0,
341
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
342
+
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN),
343
+
MMSYS_ROUTE(MERGE0, DSC1,
344
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
345
+
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN),
346
+
MMSYS_ROUTE(DSC0, DSI0,
347
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
348
+
MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0),
349
+
MMSYS_ROUTE(DSC0, DP_INTF1,
350
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
351
+
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
352
+
MMSYS_ROUTE(DSC0, DPI0,
353
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
354
+
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
355
+
MMSYS_ROUTE(DSC0, DPI1,
356
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
357
+
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
358
+
MMSYS_ROUTE(DSC0, MERGE0,
359
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
360
+
MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE),
361
+
MMSYS_ROUTE(DSC1, DSI1,
362
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
363
+
MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1),
364
+
MMSYS_ROUTE(DSC1, DP_INTF0,
365
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
366
+
MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0),
367
+
MMSYS_ROUTE(DSC1, DP_INTF1,
368
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
369
+
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
370
+
MMSYS_ROUTE(DSC1, DPI0,
371
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
372
+
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
373
+
MMSYS_ROUTE(DSC1, DPI1,
374
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
375
+
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
376
+
MMSYS_ROUTE(DSC1, MERGE0,
377
+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
378
+
MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE),
452
379
};
453
380
454
381
static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = {
455
-
{
456
-
DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
457
-
MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
458
-
MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
459
-
}, {
460
-
DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
461
-
MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
462
-
MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
463
-
}, {
464
-
DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
465
-
MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
466
-
MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
467
-
}, {
468
-
DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
469
-
MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
470
-
MT8195_SOUT_TO_MIXER_IN1_SEL
471
-
}, {
472
-
DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
473
-
MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
474
-
MT8195_SOUT_TO_MIXER_IN2_SEL
475
-
}, {
476
-
DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
477
-
MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
478
-
MT8195_SOUT_TO_MIXER_IN3_SEL
479
-
}, {
480
-
DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
481
-
MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
482
-
MT8195_SOUT_TO_MIXER_IN4_SEL
483
-
}, {
484
-
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
485
-
MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
486
-
MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
487
-
}, {
488
-
DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
489
-
MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
490
-
MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
491
-
}, {
492
-
DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
493
-
MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
494
-
MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
495
-
}, {
496
-
DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
497
-
MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
498
-
MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
499
-
}, {
500
-
DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
501
-
MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
502
-
MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
503
-
}, {
504
-
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
505
-
MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
506
-
MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
507
-
}, {
508
-
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
509
-
MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
510
-
MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
511
-
}, {
512
-
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
513
-
MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
514
-
MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
515
-
}, {
516
-
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
517
-
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
518
-
MT8195_MERGE4_SOUT_TO_DPI1_SEL
519
-
}, {
520
-
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
521
-
MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
522
-
MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
523
-
}, {
524
-
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
525
-
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
526
-
MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
527
-
}
382
+
MMSYS_ROUTE(MDP_RDMA0, MERGE1,
383
+
MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
384
+
MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0),
385
+
MMSYS_ROUTE(MDP_RDMA1, MERGE1,
386
+
MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
387
+
MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1),
388
+
MMSYS_ROUTE(MDP_RDMA2, MERGE2,
389
+
MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
390
+
MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2),
391
+
MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
392
+
MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
393
+
MT8195_SOUT_TO_MIXER_IN1_SEL),
394
+
MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
395
+
MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
396
+
MT8195_SOUT_TO_MIXER_IN2_SEL),
397
+
MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
398
+
MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
399
+
MT8195_SOUT_TO_MIXER_IN3_SEL),
400
+
MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
401
+
MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
402
+
MT8195_SOUT_TO_MIXER_IN4_SEL),
403
+
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
404
+
MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
405
+
MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL),
406
+
MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
407
+
MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
408
+
MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT),
409
+
MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
410
+
MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
411
+
MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT),
412
+
MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
413
+
MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
414
+
MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT),
415
+
MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
416
+
MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
417
+
MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT),
418
+
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
419
+
MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
420
+
MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER),
421
+
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
422
+
MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
423
+
MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT),
424
+
MMSYS_ROUTE(MERGE5, DPI1,
425
+
MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
426
+
MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT),
427
+
MMSYS_ROUTE(MERGE5, DPI1,
428
+
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
429
+
MT8195_MERGE4_SOUT_TO_DPI1_SEL),
430
+
MMSYS_ROUTE(MERGE5, DP_INTF1,
431
+
MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
432
+
MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT),
433
+
MMSYS_ROUTE(MERGE5, DP_INTF1,
434
+
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
435
+
MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL),
528
436
};
529
437
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
+31
-41
drivers/soc/mediatek/mt8365-mmsys.h
+31
-41
drivers/soc/mediatek/mt8365-mmsys.h
···
28
28
#define MT8365_DPI0_SEL_IN_RDMA1 0x0
29
29
30
30
static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
31
-
{
32
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
33
-
MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
34
-
MT8365_DISP_MS_IN_OUT_MASK, MT8365_OVL0_MOUT_PATH0_SEL
35
-
}, {
36
-
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
37
-
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
38
-
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SEL_IN_OVL0
39
-
}, {
40
-
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
41
-
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
42
-
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SOUT_COLOR0
43
-
}, {
44
-
DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR,
45
-
MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
46
-
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DISP_COLOR_SEL_IN_COLOR0
47
-
}, {
48
-
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
49
-
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
50
-
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DITHER_MOUT_EN_DSI0
51
-
}, {
52
-
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
53
-
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
54
-
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DSI0_SEL_IN_DITHER
55
-
}, {
56
-
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
57
-
MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
58
-
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
59
-
}, {
60
-
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
61
-
MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
62
-
MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK, MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK
63
-
}, {
64
-
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
65
-
MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
66
-
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DPI0_SEL_IN_RDMA1
67
-
}, {
68
-
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
69
-
MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
70
-
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA1_SOUT_DPI0
71
-
},
31
+
MMSYS_ROUTE(OVL0, RDMA0,
32
+
MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
33
+
MT8365_DISP_MS_IN_OUT_MASK, MT8365_OVL0_MOUT_PATH0_SEL),
34
+
MMSYS_ROUTE(OVL0, RDMA0,
35
+
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
36
+
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SEL_IN_OVL0),
37
+
MMSYS_ROUTE(RDMA0, COLOR0,
38
+
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
39
+
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SOUT_COLOR0),
40
+
MMSYS_ROUTE(COLOR0, CCORR,
41
+
MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
42
+
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DISP_COLOR_SEL_IN_COLOR0),
43
+
MMSYS_ROUTE(DITHER0, DSI0,
44
+
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
45
+
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DITHER_MOUT_EN_DSI0),
46
+
MMSYS_ROUTE(DITHER0, DSI0,
47
+
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
48
+
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DSI0_SEL_IN_DITHER),
49
+
MMSYS_ROUTE(RDMA0, COLOR0,
50
+
MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
51
+
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0),
52
+
MMSYS_ROUTE(RDMA1, DPI0,
53
+
MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
54
+
MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK,
55
+
MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK),
56
+
MMSYS_ROUTE(RDMA1, DPI0,
57
+
MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
58
+
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DPI0_SEL_IN_RDMA1),
59
+
MMSYS_ROUTE(RDMA1, DPI0,
60
+
MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
61
+
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA1_SOUT_DPI0),
72
62
};
73
63
74
64
#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */