tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
perf vendor events amd: Add Zen 5 metrics
Add metrics taken from Section 1.2 "Performance Measurement" of the
Performance Monitor Counters for AMD Family 1Ah Model 00h-0Fh Processors
document available at the link below.
The recommended metrics are sourced from Table 1 "Guidance for Common
Performance Statistics with Complex Event Selects".
The pipeline utilization metrics are sourced from Table 2 "Guidance
for Pipeline Utilization Analysis Statistics". These are useful for
finding performance bottlenecks by analyzing activity at different
stages of the pipeline. There are metric groups available for Level 1
and Level 2 analysis.
Reviewed-by: Ian Rogers <irogers@google.com>
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ananth Narayan <ananth.narayan@amd.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Stephane Eranian <eranian@google.com>
Link: https://bugzilla.kernel.org/attachment.cgi?id=305974
Link: https://lore.kernel.org/r/ee21ff77d89efa99997d3c2ebeeae22ddb6e7e12.1714717230.git.sandipan.das@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
authored by
Sandipan Das
and committed by
Arnaldo Carvalho de Melo
a9fe4ac7
dc082ae6
+444
+99
tools/perf/pmu-events/arch/x86/amdzen5/pipeline.json
+99
tools/perf/pmu-events/arch/x86/amdzen5/pipeline.json
···
1
+
[
2
+
{
3
+
"MetricName": "total_dispatch_slots",
4
+
"BriefDescription": "Total dispatch slots (up to 8 instructions can be dispatched in each cycle).",
5
+
"MetricExpr": "8 * ls_not_halted_cyc",
6
+
"ScaleUnit": "1slots"
7
+
},
8
+
{
9
+
"MetricName": "frontend_bound",
10
+
"BriefDescription": "Percentage of dispatch slots that remained unused because the frontend did not supply enough instructions/ops.",
11
+
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend, total_dispatch_slots)",
12
+
"MetricGroup": "PipelineL1",
13
+
"ScaleUnit": "100%slots"
14
+
},
15
+
{
16
+
"MetricName": "bad_speculation",
17
+
"BriefDescription": "Percentage of dispatched ops that did not retire.",
18
+
"MetricExpr": "d_ratio(de_src_op_disp.all - ex_ret_ops, total_dispatch_slots)",
19
+
"MetricGroup": "PipelineL1",
20
+
"ScaleUnit": "100%ops"
21
+
},
22
+
{
23
+
"MetricName": "backend_bound",
24
+
"BriefDescription": "Percentage of dispatch slots that remained unused because of backend stalls.",
25
+
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.backend_stalls, total_dispatch_slots)",
26
+
"MetricGroup": "PipelineL1",
27
+
"ScaleUnit": "100%slots"
28
+
},
29
+
{
30
+
"MetricName": "smt_contention",
31
+
"BriefDescription": "Percentage of dispatch slots that remained unused because the other thread was selected.",
32
+
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.smt_contention, total_dispatch_slots)",
33
+
"MetricGroup": "PipelineL1",
34
+
"ScaleUnit": "100%slots"
35
+
},
36
+
{
37
+
"MetricName": "retiring",
38
+
"BriefDescription": "Percentage of dispatch slots used by ops that retired.",
39
+
"MetricExpr": "d_ratio(ex_ret_ops, total_dispatch_slots)",
40
+
"MetricGroup": "PipelineL1",
41
+
"ScaleUnit": "100%slots"
42
+
},
43
+
{
44
+
"MetricName": "frontend_bound_by_latency",
45
+
"BriefDescription": "Percentage of dispatch slots that remained unused because of a latency bottleneck in the frontend (such as instruction cache or TLB misses).",
46
+
"MetricExpr": "d_ratio((8 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\\,cmask\\=0x8@), total_dispatch_slots)",
47
+
"MetricGroup": "PipelineL2;frontend_bound_group",
48
+
"ScaleUnit": "100%slots"
49
+
},
50
+
{
51
+
"MetricName": "frontend_bound_by_bandwidth",
52
+
"BriefDescription": "Percentage of dispatch slots that remained unused because of a bandwidth bottleneck in the frontend (such as decode or op cache fetch bandwidth).",
53
+
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend - (8 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\\,cmask\\=0x8@), total_dispatch_slots)",
54
+
"MetricGroup": "PipelineL2;frontend_bound_group",
55
+
"ScaleUnit": "100%slots"
56
+
},
57
+
{
58
+
"MetricName": "bad_speculation_from_mispredicts",
59
+
"BriefDescription": "Percentage of dispatched ops that were flushed due to branch mispredicts.",
60
+
"MetricExpr": "d_ratio(bad_speculation * ex_ret_brn_misp, ex_ret_brn_misp + bp_redirects.resync)",
61
+
"MetricGroup": "PipelineL2;bad_speculation_group",
62
+
"ScaleUnit": "100%ops"
63
+
},
64
+
{
65
+
"MetricName": "bad_speculation_from_pipeline_restarts",
66
+
"BriefDescription": "Percentage of dispatched ops that were flushed due to pipeline restarts (resyncs).",
67
+
"MetricExpr": "d_ratio(bad_speculation * bp_redirects.resync, ex_ret_brn_misp + bp_redirects.resync)",
68
+
"MetricGroup": "PipelineL2;bad_speculation_group",
69
+
"ScaleUnit": "100%ops"
70
+
},
71
+
{
72
+
"MetricName": "backend_bound_by_memory",
73
+
"BriefDescription": "Percentage of dispatch slots that remained unused because of stalls due to the memory subsystem.",
74
+
"MetricExpr": "backend_bound * d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete)",
75
+
"MetricGroup": "PipelineL2;backend_bound_group",
76
+
"ScaleUnit": "100%slots"
77
+
},
78
+
{
79
+
"MetricName": "backend_bound_by_cpu",
80
+
"BriefDescription": "Percentage of dispatch slots that remained unused because of stalls not related to the memory subsystem.",
81
+
"MetricExpr": "backend_bound * (1 - d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete))",
82
+
"MetricGroup": "PipelineL2;backend_bound_group",
83
+
"ScaleUnit": "100%slots"
84
+
},
85
+
{
86
+
"MetricName": "retiring_from_fastpath",
87
+
"BriefDescription": "Percentage of dispatch slots used by fastpath ops that retired.",
88
+
"MetricExpr": "retiring * (1 - d_ratio(ex_ret_ucode_ops, ex_ret_ops))",
89
+
"MetricGroup": "PipelineL2;retiring_group",
90
+
"ScaleUnit": "100%slots"
91
+
},
92
+
{
93
+
"MetricName": "retiring_from_microcode",
94
+
"BriefDescription": "Percentage of dispatch slots used by microcode ops that retired.",
95
+
"MetricExpr": "retiring * d_ratio(ex_ret_ucode_ops, ex_ret_ops)",
96
+
"MetricGroup": "PipelineL2;retiring_group",
97
+
"ScaleUnit": "100%slots"
98
+
}
99
+
]
+345
tools/perf/pmu-events/arch/x86/amdzen5/recommended.json
+345
tools/perf/pmu-events/arch/x86/amdzen5/recommended.json
···
1
+
[
2
+
{
3
+
"MetricName": "branch_misprediction_rate",
4
+
"BriefDescription": "Execution-time branch misprediction rate (non-speculative).",
5
+
"MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
6
+
"MetricGroup": "branch_prediction",
7
+
"ScaleUnit": "1per_branch"
8
+
},
9
+
{
10
+
"MetricName": "all_data_cache_accesses_pti",
11
+
"BriefDescription": "All data cache accesses per thousand instructions.",
12
+
"MetricExpr": "ls_dispatch.all / instructions",
13
+
"MetricGroup": "l1_dcache",
14
+
"ScaleUnit": "1e3per_1k_instr"
15
+
},
16
+
{
17
+
"MetricName": "all_l2_cache_accesses_pti",
18
+
"BriefDescription": "All L2 cache accesses per thousand instructions.",
19
+
"MetricExpr": "(l2_request_g1.all_no_prefetch + l2_pf_hit_l2.l2_hwpf + l2_pf_miss_l2_hit_l3.l2_hwpf + l2_pf_miss_l2_l3.l2_hwpf) / instructions",
20
+
"MetricGroup": "l2_cache",
21
+
"ScaleUnit": "1e3per_1k_instr"
22
+
},
23
+
{
24
+
"MetricName": "l2_cache_accesses_from_l1_ic_misses_pti",
25
+
"BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch) per thousand instructions.",
26
+
"MetricExpr": "l2_request_g1.cacheable_ic_read / instructions",
27
+
"MetricGroup": "l2_cache",
28
+
"ScaleUnit": "1e3per_1k_instr"
29
+
},
30
+
{
31
+
"MetricName": "l2_cache_accesses_from_l1_dc_misses_pti",
32
+
"BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch) per thousand instructions.",
33
+
"MetricExpr": "l2_request_g1.all_dc / instructions",
34
+
"MetricGroup": "l2_cache",
35
+
"ScaleUnit": "1e3per_1k_instr"
36
+
},
37
+
{
38
+
"MetricName": "l2_cache_accesses_from_l2_hwpf_pti",
39
+
"BriefDescription": "L2 cache accesses from L2 cache hardware prefetcher per thousand instructions.",
40
+
"MetricExpr": "(l2_pf_hit_l2.l1_dc_l2_hwpf + l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf + l2_pf_miss_l2_l3.l1_dc_l2_hwpf) / instructions",
41
+
"MetricGroup": "l2_cache",
42
+
"ScaleUnit": "1e3per_1k_instr"
43
+
},
44
+
{
45
+
"MetricName": "all_l2_cache_misses_pti",
46
+
"BriefDescription": "All L2 cache misses per thousand instructions.",
47
+
"MetricExpr": "(l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.l2_hwpf + l2_pf_miss_l2_l3.l2_hwpf) / instructions",
48
+
"MetricGroup": "l2_cache",
49
+
"ScaleUnit": "1e3per_1k_instr"
50
+
},
51
+
{
52
+
"MetricName": "l2_cache_misses_from_l1_ic_miss_pti",
53
+
"BriefDescription": "L2 cache misses from L1 instruction cache misses per thousand instructions.",
54
+
"MetricExpr": "l2_cache_req_stat.ic_fill_miss / instructions",
55
+
"MetricGroup": "l2_cache",
56
+
"ScaleUnit": "1e3per_1k_instr"
57
+
},
58
+
{
59
+
"MetricName": "l2_cache_misses_from_l1_dc_miss_pti",
60
+
"BriefDescription": "L2 cache misses from L1 data cache misses per thousand instructions.",
61
+
"MetricExpr": "l2_cache_req_stat.ls_rd_blk_c / instructions",
62
+
"MetricGroup": "l2_cache",
63
+
"ScaleUnit": "1e3per_1k_instr"
64
+
},
65
+
{
66
+
"MetricName": "l2_cache_misses_from_l2_hwpf_pti",
67
+
"BriefDescription": "L2 cache misses from L2 cache hardware prefetcher per thousand instructions.",
68
+
"MetricExpr": "(l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf + l2_pf_miss_l2_l3.l1_dc_l2_hwpf) / instructions",
69
+
"MetricGroup": "l2_cache",
70
+
"ScaleUnit": "1e3per_1k_instr"
71
+
},
72
+
{
73
+
"MetricName": "all_l2_cache_hits_pti",
74
+
"BriefDescription": "All L2 cache hits per thousand instructions.",
75
+
"MetricExpr": "(l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.l2_hwpf) / instructions",
76
+
"MetricGroup": "l2_cache",
77
+
"ScaleUnit": "1e3per_1k_instr"
78
+
},
79
+
{
80
+
"MetricName": "l2_cache_hits_from_l1_ic_miss_pti",
81
+
"BriefDescription": "L2 cache hits from L1 instruction cache misses per thousand instructions.",
82
+
"MetricExpr": "l2_cache_req_stat.ic_hit_in_l2 / instructions",
83
+
"MetricGroup": "l2_cache",
84
+
"ScaleUnit": "1e3per_1k_instr"
85
+
},
86
+
{
87
+
"MetricName": "l2_cache_hits_from_l1_dc_miss_pti",
88
+
"BriefDescription": "L2 cache hits from L1 data cache misses per thousand instructions.",
89
+
"MetricExpr": "l2_cache_req_stat.dc_hit_in_l2 / instructions",
90
+
"MetricGroup": "l2_cache",
91
+
"ScaleUnit": "1e3per_1k_instr"
92
+
},
93
+
{
94
+
"MetricName": "l2_cache_hits_from_l2_hwpf_pti",
95
+
"BriefDescription": "L2 cache hits from L2 cache hardware prefetcher per thousand instructions.",
96
+
"MetricExpr": "l2_pf_hit_l2.l1_dc_l2_hwpf / instructions",
97
+
"MetricGroup": "l2_cache",
98
+
"ScaleUnit": "1e3per_1k_instr"
99
+
},
100
+
{
101
+
"MetricName": "l3_cache_accesses",
102
+
"BriefDescription": "L3 cache accesses.",
103
+
"MetricExpr": "l3_lookup_state.all_coherent_accesses_to_l3",
104
+
"MetricGroup": "l3_cache"
105
+
},
106
+
{
107
+
"MetricName": "l3_misses",
108
+
"BriefDescription": "L3 misses (including cacheline state change requests).",
109
+
"MetricExpr": "l3_lookup_state.l3_miss",
110
+
"MetricGroup": "l3_cache"
111
+
},
112
+
{
113
+
"MetricName": "l3_read_miss_latency",
114
+
"BriefDescription": "Average L3 read miss latency (in core clocks).",
115
+
"MetricExpr": "(l3_xi_sampled_latency.all * 10) / l3_xi_sampled_latency_requests.all",
116
+
"MetricGroup": "l3_cache",
117
+
"ScaleUnit": "1ns"
118
+
},
119
+
{
120
+
"MetricName": "l3_read_miss_latency_for_local_dram",
121
+
"BriefDescription": "Average L3 read miss latency (in core clocks) for local DRAM.",
122
+
"MetricExpr": "(l3_xi_sampled_latency.dram_near * 10) / l3_xi_sampled_latency_requests.dram_near",
123
+
"MetricGroup": "l3_cache",
124
+
"ScaleUnit": "1ns"
125
+
},
126
+
{
127
+
"MetricName": "l3_read_miss_latency_for_remote_dram",
128
+
"BriefDescription": "Average L3 read miss latency (in core clocks) for remote DRAM.",
129
+
"MetricExpr": "(l3_xi_sampled_latency.dram_far * 10) / l3_xi_sampled_latency_requests.dram_far",
130
+
"MetricGroup": "l3_cache",
131
+
"ScaleUnit": "1ns"
132
+
},
133
+
{
134
+
"MetricName": "op_cache_fetch_miss_ratio",
135
+
"BriefDescription": "Op cache miss ratio for all fetches.",
136
+
"MetricExpr": "d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)",
137
+
"ScaleUnit": "100%"
138
+
},
139
+
{
140
+
"MetricName": "ic_fetch_miss_ratio",
141
+
"BriefDescription": "Instruction cache miss ratio for all fetches. An instruction cache miss will not be counted by this metric if it is an OC hit.",
142
+
"MetricExpr": "d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)",
143
+
"ScaleUnit": "100%"
144
+
},
145
+
{
146
+
"MetricName": "l1_data_cache_fills_from_memory_pti",
147
+
"BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node per thousand instructions.",
148
+
"MetricExpr": "ls_any_fills_from_sys.dram_io_all / instructions",
149
+
"MetricGroup": "l1_dcache",
150
+
"ScaleUnit": "1e3per_1k_instr"
151
+
},
152
+
{
153
+
"MetricName": "l1_data_cache_fills_from_remote_node_pti",
154
+
"BriefDescription": "L1 data cache fills from a different NUMA node per thousand instructions.",
155
+
"MetricExpr": "ls_any_fills_from_sys.far_all / instructions",
156
+
"MetricGroup": "l1_dcache",
157
+
"ScaleUnit": "1e3per_1k_instr"
158
+
},
159
+
{
160
+
"MetricName": "l1_data_cache_fills_from_same_ccx_pti",
161
+
"BriefDescription": "L1 data cache fills from within the same CCX per thousand instructions.",
162
+
"MetricExpr": "ls_any_fills_from_sys.local_all / instructions",
163
+
"MetricGroup": "l1_dcache",
164
+
"ScaleUnit": "1e3per_1k_instr"
165
+
},
166
+
{
167
+
"MetricName": "l1_data_cache_fills_from_different_ccx_pti",
168
+
"BriefDescription": "L1 data cache fills from another CCX cache in any NUMA node per thousand instructions.",
169
+
"MetricExpr": "ls_any_fills_from_sys.remote_cache / instructions",
170
+
"MetricGroup": "l1_dcache",
171
+
"ScaleUnit": "1e3per_1k_instr"
172
+
},
173
+
{
174
+
"MetricName": "all_l1_data_cache_fills_pti",
175
+
"BriefDescription": "All L1 data cache fills per thousand instructions.",
176
+
"MetricExpr": "ls_any_fills_from_sys.all / instructions",
177
+
"MetricGroup": "l1_dcache",
178
+
"ScaleUnit": "1e3per_1k_instr"
179
+
},
180
+
{
181
+
"MetricName": "l1_demand_data_cache_fills_from_local_l2_pti",
182
+
"BriefDescription": "L1 demand data cache fills from local L2 cache per thousand instructions.",
183
+
"MetricExpr": "ls_dmnd_fills_from_sys.local_l2 / instructions",
184
+
"MetricGroup": "l1_dcache",
185
+
"ScaleUnit": "1e3per_1k_instr"
186
+
},
187
+
{
188
+
"MetricName": "l1_demand_data_cache_fills_from_same_ccx_pti",
189
+
"BriefDescription": "L1 demand data cache fills from within the same CCX per thousand instructions.",
190
+
"MetricExpr": "ls_dmnd_fills_from_sys.local_ccx / instructions",
191
+
"MetricGroup": "l1_dcache",
192
+
"ScaleUnit": "1e3per_1k_instr"
193
+
},
194
+
{
195
+
"MetricName": "l1_demand_data_cache_fills_from_near_cache_pti",
196
+
"BriefDescription": "L1 demand data cache fills from another CCX cache in the same NUMA node per thousand instructions.",
197
+
"MetricExpr": "ls_dmnd_fills_from_sys.near_cache / instructions",
198
+
"MetricGroup": "l1_dcache",
199
+
"ScaleUnit": "1e3per_1k_instr"
200
+
},
201
+
{
202
+
"MetricName": "l1_demand_data_cache_fills_from_near_memory_pti",
203
+
"BriefDescription": "L1 demand data cache fills from DRAM or MMIO in the same NUMA node per thousand instructions.",
204
+
"MetricExpr": "ls_dmnd_fills_from_sys.dram_io_near / instructions",
205
+
"MetricGroup": "l1_dcache",
206
+
"ScaleUnit": "1e3per_1k_instr"
207
+
},
208
+
{
209
+
"MetricName": "l1_demand_data_cache_fills_from_far_cache_pti",
210
+
"BriefDescription": "L1 demand data cache fills from another CCX cache in a different NUMA node per thousand instructions.",
211
+
"MetricExpr": "ls_dmnd_fills_from_sys.far_cache / instructions",
212
+
"MetricGroup": "l1_dcache",
213
+
"ScaleUnit": "1e3per_1k_instr"
214
+
},
215
+
{
216
+
"MetricName": "l1_demand_data_cache_fills_from_far_memory_pti",
217
+
"BriefDescription": "L1 demand data cache fills from DRAM or MMIO in a different NUMA node per thousand instructions.",
218
+
"MetricExpr": "ls_dmnd_fills_from_sys.dram_io_far / instructions",
219
+
"MetricGroup": "l1_dcache",
220
+
"ScaleUnit": "1e3per_1k_instr"
221
+
},
222
+
{
223
+
"MetricName": "l1_itlb_misses_pti",
224
+
"BriefDescription": "L1 instruction TLB misses per thousand instructions.",
225
+
"MetricExpr": "(bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss.all) / instructions",
226
+
"MetricGroup": "tlb",
227
+
"ScaleUnit": "1e3per_1k_instr"
228
+
},
229
+
{
230
+
"MetricName": "l2_itlb_misses_pti",
231
+
"BriefDescription": "L2 instruction TLB misses and instruction page walks per thousand instructions.",
232
+
"MetricExpr": "bp_l1_tlb_miss_l2_tlb_miss.all / instructions",
233
+
"MetricGroup": "tlb",
234
+
"ScaleUnit": "1e3per_1k_instr"
235
+
},
236
+
{
237
+
"MetricName": "l1_dtlb_misses_pti",
238
+
"BriefDescription": "L1 data TLB misses per thousand instructions.",
239
+
"MetricExpr": "ls_l1_d_tlb_miss.all / instructions",
240
+
"MetricGroup": "tlb",
241
+
"ScaleUnit": "1e3per_1k_instr"
242
+
},
243
+
{
244
+
"MetricName": "l2_dtlb_misses_pti",
245
+
"BriefDescription": "L2 data TLB misses and data page walks per thousand instructions.",
246
+
"MetricExpr": "ls_l1_d_tlb_miss.all_l2_miss / instructions",
247
+
"MetricGroup": "tlb",
248
+
"ScaleUnit": "1e3per_1k_instr"
249
+
},
250
+
{
251
+
"MetricName": "all_tlbs_flushed_pti",
252
+
"BriefDescription": "All TLBs flushed per thousand instructions.",
253
+
"MetricExpr": "ls_tlb_flush.all / instructions",
254
+
"MetricGroup": "tlb",
255
+
"ScaleUnit": "1e3per_1k_instr"
256
+
},
257
+
{
258
+
"MetricName": "macro_ops_dispatched",
259
+
"BriefDescription": "Macro-ops dispatched.",
260
+
"MetricExpr": "de_src_op_disp.all",
261
+
"MetricGroup": "decoder"
262
+
},
263
+
{
264
+
"MetricName": "sse_avx_stalls",
265
+
"BriefDescription": "Mixed SSE/AVX stalls.",
266
+
"MetricExpr": "fp_disp_faults.sse_avx_all"
267
+
},
268
+
{
269
+
"MetricName": "macro_ops_retired",
270
+
"BriefDescription": "Macro-ops retired.",
271
+
"MetricExpr": "ex_ret_ops"
272
+
},
273
+
{
274
+
"MetricName": "umc_data_bus_utilization",
275
+
"BriefDescription": "Memory controller data bus utilization.",
276
+
"MetricExpr": "d_ratio(umc_data_slot_clks.all / 2, umc_mem_clk)",
277
+
"MetricGroup": "memory_controller",
278
+
"PerPkg": "1",
279
+
"ScaleUnit": "100%"
280
+
},
281
+
{
282
+
"MetricName": "umc_cas_cmd_rate",
283
+
"BriefDescription": "Memory controller CAS command rate.",
284
+
"MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",
285
+
"MetricGroup": "memory_controller",
286
+
"PerPkg": "1",
287
+
"ScaleUnit": "1per_memclk"
288
+
},
289
+
{
290
+
"MetricName": "umc_cas_cmd_read_ratio",
291
+
"BriefDescription": "Ratio of memory controller CAS commands for reads.",
292
+
"MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",
293
+
"MetricGroup": "memory_controller",
294
+
"PerPkg": "1",
295
+
"ScaleUnit": "100%"
296
+
},
297
+
{
298
+
"MetricName": "umc_cas_cmd_write_ratio",
299
+
"BriefDescription": "Ratio of memory controller CAS commands for writes.",
300
+
"MetricExpr": "d_ratio(umc_cas_cmd.wr, umc_cas_cmd.all)",
301
+
"MetricGroup": "memory_controller",
302
+
"PerPkg": "1",
303
+
"ScaleUnit": "100%"
304
+
},
305
+
{
306
+
"MetricName": "umc_mem_read_bandwidth",
307
+
"BriefDescription": "Estimated memory read bandwidth.",
308
+
"MetricExpr": "(umc_cas_cmd.rd * 64) / 1e6 / duration_time",
309
+
"MetricGroup": "memory_controller",
310
+
"PerPkg": "1",
311
+
"ScaleUnit": "1MB/s"
312
+
},
313
+
{
314
+
"MetricName": "umc_mem_write_bandwidth",
315
+
"BriefDescription": "Estimated memory write bandwidth.",
316
+
"MetricExpr": "(umc_cas_cmd.wr * 64) / 1e6 / duration_time",
317
+
"MetricGroup": "memory_controller",
318
+
"PerPkg": "1",
319
+
"ScaleUnit": "1MB/s"
320
+
},
321
+
{
322
+
"MetricName": "umc_mem_bandwidth",
323
+
"BriefDescription": "Estimated combined memory bandwidth.",
324
+
"MetricExpr": "(umc_cas_cmd.all * 64) / 1e6 / duration_time",
325
+
"MetricGroup": "memory_controller",
326
+
"PerPkg": "1",
327
+
"ScaleUnit": "1MB/s"
328
+
},
329
+
{
330
+
"MetricName": "umc_activate_cmd_rate",
331
+
"BriefDescription": "Memory controller ACTIVATE command rate.",
332
+
"MetricExpr": "d_ratio(umc_act_cmd.all * 1000, umc_mem_clk)",
333
+
"MetricGroup": "memory_controller",
334
+
"PerPkg": "1",
335
+
"ScaleUnit": "1per_memclk"
336
+
},
337
+
{
338
+
"MetricName": "umc_precharge_cmd_rate",
339
+
"BriefDescription": "Memory controller PRECHARGE command rate.",
340
+
"MetricExpr": "d_ratio(umc_pchg_cmd.all * 1000, umc_mem_clk)",
341
+
"MetricGroup": "memory_controller",
342
+
"PerPkg": "1",
343
+
"ScaleUnit": "1per_memclk"
344
+
}
345
+
]