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PM / devfreq: exynos: Add the detailed correlation for Exynos5422 bus
This patch adds the detailed corrleation between sub-blocks and power line
for Exynos5422.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
authored by
Chanwoo Choi
and committed by
MyungJoo Ham
a9d1f4e0
19cf91d0
+19
+19
Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+19
Documentation/devicetree/bindings/devfreq/exynos-bus.txt
···
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|--- LCD0
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|--- ISP
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+
- In case of Exynos5422, there are two power line as following:
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VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
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|--- DREX 1
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VDD_INT |--- NoC_Core (parent device)
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|--- G2D
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|--- G3D
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|--- DISP1
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|--- NoC_WCORE
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|--- GSCL
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|--- MSCL
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|--- ISP
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|--- MFC
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|--- GEN
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|--- PERIS
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|--- PERIC
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|--- FSYS
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|--- FSYS2
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Example1:
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Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
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power line (regulator). The MIF (Memory Interface) AXI bus is used to