tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
[ARM] 3151/1: make various assembly local labels actually local (io-*.S)
Patch from Nicolas Pitre
For assembly labels to actually be local they must start with ".L" and
not only "." otherwise they still remain visible in the final link and
clutter kallsyms needlessly, and possibly make for unclear symbolic
backtrace. This patch simply inserts a"L" where appropriate. The code
itself is unchanged.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
authored by
Nicolas Pitre
and committed by
Russell King
a9c4814d
7ba11a9c
+82
-80
+2
-2
arch/arm/lib/io-acorn.S
+2
-2
arch/arm/lib/io-acorn.S
+12
-12
arch/arm/lib/io-readsb.S
+12
-12
arch/arm/lib/io-readsb.S
···
10
10
#include <linux/linkage.h>
11
11
#include <asm/assembler.h>
12
12
13
-
.insb_align: rsb ip, ip, #4
13
+
.Linsb_align: rsb ip, ip, #4
14
14
cmp ip, r2
15
15
movgt ip, r2
16
16
cmp ip, #2
···
21
21
ldrgtb r3, [r0]
22
22
strgtb r3, [r1], #1
23
23
subs r2, r2, ip
24
-
bne .insb_aligned
24
+
bne .Linsb_aligned
25
25
26
26
ENTRY(__raw_readsb)
27
27
teq r2, #0 @ do we have to check for the zero len?
28
28
moveq pc, lr
29
29
ands ip, r1, #3
30
-
bne .insb_align
30
+
bne .Linsb_align
31
31
32
-
.insb_aligned: stmfd sp!, {r4 - r6, lr}
32
+
.Linsb_aligned: stmfd sp!, {r4 - r6, lr}
33
33
34
34
subs r2, r2, #16
35
-
bmi .insb_no_16
35
+
bmi .Linsb_no_16
36
36
37
-
.insb_16_lp: ldrb r3, [r0]
37
+
.Linsb_16_lp: ldrb r3, [r0]
38
38
ldrb r4, [r0]
39
39
ldrb r5, [r0]
40
40
mov r3, r3, put_byte_0
···
69
69
stmia r1!, {r3 - r6}
70
70
71
71
subs r2, r2, #16
72
-
bpl .insb_16_lp
72
+
bpl .Linsb_16_lp
73
73
74
74
tst r2, #15
75
75
LOADREGS(eqfd, sp!, {r4 - r6, pc})
76
76
77
-
.insb_no_16: tst r2, #8
78
-
beq .insb_no_8
77
+
.Linsb_no_16: tst r2, #8
78
+
beq .Linsb_no_8
79
79
80
80
ldrb r3, [r0]
81
81
ldrb r4, [r0]
···
95
95
orr r4, r4, ip, put_byte_3
96
96
stmia r1!, {r3, r4}
97
97
98
-
.insb_no_8: tst r2, #4
99
-
beq .insb_no_4
98
+
.Linsb_no_8: tst r2, #4
99
+
beq .Linsb_no_4
100
100
101
101
ldrb r3, [r0]
102
102
ldrb r4, [r0]
···
108
108
orr r3, r3, r6, put_byte_3
109
109
str r3, [r1], #4
110
110
111
-
.insb_no_4: ands r2, r2, #3
111
+
.Linsb_no_4: ands r2, r2, #3
112
112
LOADREGS(eqfd, sp!, {r4 - r6, pc})
113
113
114
114
cmp r2, #2
+15
-15
arch/arm/lib/io-readsw-armv3.S
+15
-15
arch/arm/lib/io-readsw-armv3.S
···
11
11
#include <asm/assembler.h>
12
12
#include <asm/hardware.h>
13
13
14
-
.insw_bad_alignment:
15
-
adr r0, .insw_bad_align_msg
14
+
.Linsw_bad_alignment:
15
+
adr r0, .Linsw_bad_align_msg
16
16
mov r2, lr
17
17
b panic
18
-
.insw_bad_align_msg:
18
+
.Linsw_bad_align_msg:
19
19
.asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
20
20
.align
21
21
22
-
.insw_align: tst r1, #1
23
-
bne .insw_bad_alignment
22
+
.Linsw_align: tst r1, #1
23
+
bne .Linsw_bad_alignment
24
24
25
25
ldr r3, [r0]
26
26
strb r3, [r1], #1
···
34
34
teq r2, #0 @ do we have to check for the zero len?
35
35
moveq pc, lr
36
36
tst r1, #3
37
-
bne .insw_align
37
+
bne .Linsw_align
38
38
39
-
.insw_aligned: mov ip, #0xff
39
+
.Linsw_aligned: mov ip, #0xff
40
40
orr ip, ip, ip, lsl #8
41
41
stmfd sp!, {r4, r5, r6, lr}
42
42
43
43
subs r2, r2, #8
44
-
bmi .no_insw_8
44
+
bmi .Lno_insw_8
45
45
46
-
.insw_8_lp: ldr r3, [r0]
46
+
.Linsw_8_lp: ldr r3, [r0]
47
47
and r3, r3, ip
48
48
ldr r4, [r0]
49
49
orr r3, r3, r4, lsl #16
···
66
66
stmia r1!, {r3 - r6}
67
67
68
68
subs r2, r2, #8
69
-
bpl .insw_8_lp
69
+
bpl .Linsw_8_lp
70
70
71
71
tst r2, #7
72
72
LOADREGS(eqfd, sp!, {r4, r5, r6, pc})
73
73
74
-
.no_insw_8: tst r2, #4
75
-
beq .no_insw_4
74
+
.Lno_insw_8: tst r2, #4
75
+
beq .Lno_insw_4
76
76
77
77
ldr r3, [r0]
78
78
and r3, r3, ip
···
86
86
87
87
stmia r1!, {r3, r4}
88
88
89
-
.no_insw_4: tst r2, #2
90
-
beq .no_insw_2
89
+
.Lno_insw_4: tst r2, #2
90
+
beq .Lno_insw_2
91
91
92
92
ldr r3, [r0]
93
93
and r3, r3, ip
···
96
96
97
97
str r3, [r1], #4
98
98
99
-
.no_insw_2: tst r2, #1
99
+
.Lno_insw_2: tst r2, #1
100
100
ldrne r3, [r0]
101
101
strneb r3, [r1], #1
102
102
movne r3, r3, lsr #8
+12
-12
arch/arm/lib/io-readsw-armv4.S
+12
-12
arch/arm/lib/io-readsw-armv4.S
···
18
18
#endif
19
19
.endm
20
20
21
-
.insw_align: movs ip, r1, lsl #31
22
-
bne .insw_noalign
21
+
.Linsw_align: movs ip, r1, lsl #31
22
+
bne .Linsw_noalign
23
23
ldrh ip, [r0]
24
24
sub r2, r2, #1
25
25
strh ip, [r1], #2
···
28
28
teq r2, #0
29
29
moveq pc, lr
30
30
tst r1, #3
31
-
bne .insw_align
31
+
bne .Linsw_align
32
32
33
33
stmfd sp!, {r4, r5, lr}
34
34
35
35
subs r2, r2, #8
36
-
bmi .no_insw_8
36
+
bmi .Lno_insw_8
37
37
38
-
.insw_8_lp: ldrh r3, [r0]
38
+
.Linsw_8_lp: ldrh r3, [r0]
39
39
ldrh r4, [r0]
40
40
pack r3, r3, r4
41
41
···
53
53
54
54
subs r2, r2, #8
55
55
stmia r1!, {r3 - r5, ip}
56
-
bpl .insw_8_lp
56
+
bpl .Linsw_8_lp
57
57
58
-
.no_insw_8: tst r2, #4
59
-
beq .no_insw_4
58
+
.Lno_insw_8: tst r2, #4
59
+
beq .Lno_insw_4
60
60
61
61
ldrh r3, [r0]
62
62
ldrh r4, [r0]
···
68
68
69
69
stmia r1!, {r3, r4}
70
70
71
-
.no_insw_4: movs r2, r2, lsl #31
72
-
bcc .no_insw_2
71
+
.Lno_insw_4: movs r2, r2, lsl #31
72
+
bcc .Lno_insw_2
73
73
74
74
ldrh r3, [r0]
75
75
ldrh ip, [r0]
76
76
pack r3, r3, ip
77
77
str r3, [r1], #4
78
78
79
-
.no_insw_2: ldrneh r3, [r0]
79
+
.Lno_insw_2: ldrneh r3, [r0]
80
80
strneh r3, [r1]
81
81
82
82
ldmfd sp!, {r4, r5, pc}
···
93
93
#define pull_hbyte1 lsr #8
94
94
#endif
95
95
96
-
.insw_noalign: stmfd sp!, {r4, lr}
96
+
.Linsw_noalign: stmfd sp!, {r4, lr}
97
97
ldrccb ip, [r1, #-1]!
98
98
bcc 1f
99
99
+13
-12
arch/arm/lib/io-writesb.S
+13
-12
arch/arm/lib/io-writesb.S
···
30
30
#endif
31
31
.endm
32
32
33
-
.outsb_align: rsb ip, ip, #4
33
+
.Loutsb_align: rsb ip, ip, #4
34
34
cmp ip, r2
35
35
movgt ip, r2
36
36
cmp ip, #2
···
41
41
ldrgtb r3, [r1], #1
42
42
strgtb r3, [r0]
43
43
subs r2, r2, ip
44
-
bne .outsb_aligned
44
+
bne .Loutsb_aligned
45
45
46
46
ENTRY(__raw_writesb)
47
47
teq r2, #0 @ do we have to check for the zero len?
48
48
moveq pc, lr
49
49
ands ip, r1, #3
50
-
bne .outsb_align
50
+
bne .Loutsb_align
51
51
52
-
.outsb_aligned: stmfd sp!, {r4, r5, lr}
52
+
.Loutsb_aligned:
53
+
stmfd sp!, {r4, r5, lr}
53
54
54
55
subs r2, r2, #16
55
-
bmi .outsb_no_16
56
+
bmi .Loutsb_no_16
56
57
57
-
.outsb_16_lp: ldmia r1!, {r3, r4, r5, ip}
58
+
.Loutsb_16_lp: ldmia r1!, {r3, r4, r5, ip}
58
59
outword r3
59
60
outword r4
60
61
outword r5
61
62
outword ip
62
63
subs r2, r2, #16
63
-
bpl .outsb_16_lp
64
+
bpl .Loutsb_16_lp
64
65
65
66
tst r2, #15
66
67
LOADREGS(eqfd, sp!, {r4, r5, pc})
67
68
68
-
.outsb_no_16: tst r2, #8
69
-
beq .outsb_no_8
69
+
.Loutsb_no_16: tst r2, #8
70
+
beq .Loutsb_no_8
70
71
71
72
ldmia r1!, {r3, r4}
72
73
outword r3
73
74
outword r4
74
75
75
-
.outsb_no_8: tst r2, #4
76
-
beq .outsb_no_4
76
+
.Loutsb_no_8: tst r2, #4
77
+
beq .Loutsb_no_4
77
78
78
79
ldr r3, [r1], #4
79
80
outword r3
80
81
81
-
.outsb_no_4: ands r2, r2, #3
82
+
.Loutsb_no_4: ands r2, r2, #3
82
83
LOADREGS(eqfd, sp!, {r4, r5, pc})
83
84
84
85
cmp r2, #2
+15
-15
arch/arm/lib/io-writesw-armv3.S
+15
-15
arch/arm/lib/io-writesw-armv3.S
···
11
11
#include <asm/assembler.h>
12
12
#include <asm/hardware.h>
13
13
14
-
.outsw_bad_alignment:
15
-
adr r0, .outsw_bad_align_msg
14
+
.Loutsw_bad_alignment:
15
+
adr r0, .Loutsw_bad_align_msg
16
16
mov r2, lr
17
17
b panic
18
-
.outsw_bad_align_msg:
18
+
.Loutsw_bad_align_msg:
19
19
.asciz "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
20
20
.align
21
21
22
-
.outsw_align: tst r1, #1
23
-
bne .outsw_bad_alignment
22
+
.Loutsw_align: tst r1, #1
23
+
bne .Loutsw_bad_alignment
24
24
25
25
add r1, r1, #2
26
26
···
35
35
teq r2, #0 @ do we have to check for the zero len?
36
36
moveq pc, lr
37
37
tst r1, #3
38
-
bne .outsw_align
38
+
bne .Loutsw_align
39
39
40
-
.outsw_aligned: stmfd sp!, {r4, r5, r6, lr}
40
+
stmfd sp!, {r4, r5, r6, lr}
41
41
42
42
subs r2, r2, #8
43
-
bmi .no_outsw_8
43
+
bmi .Lno_outsw_8
44
44
45
-
.outsw_8_lp: ldmia r1!, {r3, r4, r5, r6}
45
+
.Loutsw_8_lp: ldmia r1!, {r3, r4, r5, r6}
46
46
47
47
mov ip, r3, lsl #16
48
48
orr ip, ip, ip, lsr #16
···
77
77
str ip, [r0]
78
78
79
79
subs r2, r2, #8
80
-
bpl .outsw_8_lp
80
+
bpl .Loutsw_8_lp
81
81
82
82
tst r2, #7
83
83
LOADREGS(eqfd, sp!, {r4, r5, r6, pc})
84
84
85
-
.no_outsw_8: tst r2, #4
86
-
beq .no_outsw_4
85
+
.Lno_outsw_8: tst r2, #4
86
+
beq .Lno_outsw_4
87
87
88
88
ldmia r1!, {r3, r4}
89
89
···
103
103
orr ip, ip, ip, lsl #16
104
104
str ip, [r0]
105
105
106
-
.no_outsw_4: tst r2, #2
107
-
beq .no_outsw_2
106
+
.Lno_outsw_4: tst r2, #2
107
+
beq .Lno_outsw_2
108
108
109
109
ldr r3, [r1], #4
110
110
···
116
116
orr ip, ip, ip, lsl #16
117
117
str ip, [r0]
118
118
119
-
.no_outsw_2: tst r2, #1
119
+
.Lno_outsw_2: tst r2, #1
120
120
121
121
ldrne r3, [r1]
122
122
+13
-12
arch/arm/lib/io-writesw-armv4.S
+13
-12
arch/arm/lib/io-writesw-armv4.S
···
22
22
#endif
23
23
.endm
24
24
25
-
.outsw_align: movs ip, r1, lsl #31
26
-
bne .outsw_noalign
25
+
.Loutsw_align: movs ip, r1, lsl #31
26
+
bne .Loutsw_noalign
27
27
28
28
ldrh r3, [r1], #2
29
29
sub r2, r2, #1
···
33
33
teq r2, #0
34
34
moveq pc, lr
35
35
ands r3, r1, #3
36
-
bne .outsw_align
36
+
bne .Loutsw_align
37
37
38
38
stmfd sp!, {r4, r5, lr}
39
39
40
40
subs r2, r2, #8
41
-
bmi .no_outsw_8
41
+
bmi .Lno_outsw_8
42
42
43
-
.outsw_8_lp: ldmia r1!, {r3, r4, r5, ip}
43
+
.Loutsw_8_lp: ldmia r1!, {r3, r4, r5, ip}
44
44
subs r2, r2, #8
45
45
outword r3
46
46
outword r4
47
47
outword r5
48
48
outword ip
49
-
bpl .outsw_8_lp
49
+
bpl .Loutsw_8_lp
50
50
51
-
.no_outsw_8: tst r2, #4
52
-
beq .no_outsw_4
51
+
.Lno_outsw_8: tst r2, #4
52
+
beq .Lno_outsw_4
53
53
54
54
ldmia r1!, {r3, ip}
55
55
outword r3
56
56
outword ip
57
57
58
-
.no_outsw_4: movs r2, r2, lsl #31
59
-
bcc .no_outsw_2
58
+
.Lno_outsw_4: movs r2, r2, lsl #31
59
+
bcc .Lno_outsw_2
60
60
61
61
ldr r3, [r1], #4
62
62
outword r3
63
63
64
-
.no_outsw_2: ldrneh r3, [r1]
64
+
.Lno_outsw_2: ldrneh r3, [r1]
65
65
strneh r3, [r0]
66
66
67
67
ldmfd sp!, {r4, r5, pc}
···
74
74
#define push_hbyte1 lsl #8
75
75
#endif
76
76
77
-
.outsw_noalign: ldr r3, [r1, -r3]!
77
+
.Loutsw_noalign:
78
+
ldr r3, [r1, -r3]!
78
79
subcs r2, r2, #1
79
80
bcs 2f
80
81
subs r2, r2, #2