tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915: Document which platforms use which sprite registers
Note which sprite registers are valid for which platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-14-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
+11
-8
+11
-8
drivers/gpu/drm/i915/display/intel_sprite_regs.h
+11
-8
drivers/gpu/drm/i915/display/intel_sprite_regs.h
···
6
6
7
7
#include "intel_display_reg_defs.h"
8
8
9
+
/* g4x/ilk/snb video sprite */
9
10
#define _DVSACNTR 0x72180
10
11
#define _DVSBCNTR 0x73180
11
12
#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
···
112
111
#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
113
112
#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
114
113
114
+
/* ivb/hsw/bdw sprite */
115
115
#define _SPRA_CTL 0x70280
116
116
#define _SPRB_CTL 0x71280
117
117
#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
···
142
140
#define SPRITE_TILED REG_BIT(10)
143
141
#define SPRITE_DEST_KEY REG_BIT(2)
144
142
145
-
#define _SPRA_LINOFF 0x70284
146
-
#define _SPRB_LINOFF 0x71284
143
+
#define _SPRA_LINOFF 0x70284 /* ivb */
144
+
#define _SPRB_LINOFF 0x71284 /* ivb */
147
145
#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
148
146
149
147
#define _SPRA_STRIDE 0x70288
···
183
181
#define _SPRB_KEYMAX 0x712a0
184
182
#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
185
183
186
-
#define _SPRA_TILEOFF 0x702a4
187
-
#define _SPRB_TILEOFF 0x712a4
184
+
#define _SPRA_TILEOFF 0x702a4 /* ivb */
185
+
#define _SPRB_TILEOFF 0x712a4 /* ivb */
188
186
#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
189
187
#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
190
188
#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
191
189
#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
192
190
#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
193
191
194
-
#define _SPRA_OFFSET 0x702a4
195
-
#define _SPRB_OFFSET 0x712a4
192
+
#define _SPRA_OFFSET 0x702a4 /* hsw/bdw */
193
+
#define _SPRB_OFFSET 0x712a4 /* hsw/bdw */
196
194
#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
197
195
198
196
#define _SPRA_SURFLIVE 0x702ac
199
197
#define _SPRB_SURFLIVE 0x712ac
200
198
#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
201
199
202
-
#define _SPRA_SCALE 0x70304
203
-
#define _SPRB_SCALE 0x71304
200
+
#define _SPRA_SCALE 0x70304 /* ivb */
201
+
#define _SPRB_SCALE 0x71304 /* ivb */
204
202
#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
205
203
#define SPRITE_SCALE_ENABLE REG_BIT(31)
206
204
#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
···
226
224
#define _SPRB_GAMC17 0x7144c
227
225
#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
228
226
227
+
/* vlv/chv sprite */
229
228
#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
230
229
_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
231
230
#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \