tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amd/display: refactor ddc logic from dc_link_ddc to link_ddc

[why]
1. Move dd_link_ddc functions to link_ddc.
2. Move link ddc functions declaration exposed in dc to link.h
3. Move link ddc functions declaration exposed in dm to dc_link.h
4. Remove i2caux_interface.h file

Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Wenjing Liu and committed by
Alex Deucher a98cdd8c 4370f72e

+566 -638
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 66 66 67 67 #include "ivsrcid/ivsrcid_vislands30.h" 68 68 69 - #include "i2caux_interface.h" 70 69 #include <linux/module.h> 71 70 #include <linux/moduleparam.h> 72 71 #include <linux/types.h>
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
··· 39 39 #include "dc.h" 40 40 #include "dm_helpers.h" 41 41 42 - #include "dc_link_ddc.h" 43 42 #include "dc_link_dp.h" 44 43 #include "ddc_service_types.h" 45 44 #include "dpcd_defs.h" 46 45 47 - #include "i2caux_interface.h" 48 46 #include "dmub_cmd.h" 49 47 #if defined(CONFIG_DEBUG_FS) 50 48 #include "amdgpu_dm_debugfs.h"
+2 -2
drivers/gpu/drm/amd/display/dc/Makefile
··· 64 64 65 65 include $(AMD_DC) 66 66 67 - DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \ 68 - dc_surface.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \ 67 + DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \ 68 + dc_surface.o dc_link_dp.o dc_debug.o dc_stream.o \ 69 69 dc_link_enc_cfg.o dc_link_dpia.o dc_link_dpcd.o 70 70 71 71 DISPLAY_CORE += dc_vm_helper.o
-1
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
··· 33 33 #include "include/gpio_service_interface.h" 34 34 #include "include/grph_object_ctrl_defs.h" 35 35 #include "include/bios_parser_interface.h" 36 - #include "include/i2caux_interface.h" 37 36 #include "include/logger_interface.h" 38 37 39 38 #include "command_table.h"
-1
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
··· 32 32 #include "dc_bios_types.h" 33 33 #include "include/grph_object_ctrl_defs.h" 34 34 #include "include/bios_parser_interface.h" 35 - #include "include/i2caux_interface.h" 36 35 #include "include/logger_interface.h" 37 36 38 37 #include "command_table2.h"
+2 -3
drivers/gpu/drm/amd/display/dc/core/dc.c
··· 33 33 34 34 #include "resource.h" 35 35 36 + #include "gpio_service_interface.h" 36 37 #include "clk_mgr.h" 37 38 #include "clock_source.h" 38 39 #include "dc_bios_types.h" ··· 54 53 #include "link_enc_cfg.h" 55 54 56 55 #include "dc_link.h" 57 - #include "dc_link_ddc.h" 56 + #include "link.h" 58 57 #include "dm_helpers.h" 59 58 #include "mem_input.h" 60 59 ··· 68 67 #include "dce/dce_i2c.h" 69 68 70 69 #include "dmub/dmub_srv.h" 71 - 72 - #include "i2caux_interface.h" 73 70 74 71 #include "dce/dmub_psr.h" 75 72
+184 -16
drivers/gpu/drm/amd/display/dc/core/dc_link.c
··· 34 34 #include "core_status.h" 35 35 #include "dc_link_dp.h" 36 36 #include "dc_link_dpia.h" 37 - #include "dc_link_ddc.h" 37 + #include "link/link_ddc.h" 38 38 #include "link_hwss.h" 39 39 #include "link.h" 40 40 #include "opp.h" ··· 80 80 } 81 81 82 82 if (link->ddc) 83 - dal_ddc_service_destroy(&link->ddc); 83 + link_destroy_ddc_service(&link->ddc); 84 84 85 85 if (link->panel_cntl) 86 86 link->panel_cntl->funcs->destroy(&link->panel_cntl); ··· 277 277 (connector_id == CONNECTOR_ID_EDP) || 278 278 (connector_id == CONNECTOR_ID_USBC)); 279 279 280 - ddc = dal_ddc_service_get_ddc_pin(link->ddc); 280 + ddc = get_ddc_pin(link->ddc); 281 281 282 282 if (!ddc) { 283 283 BREAK_TO_DEBUGGER(); ··· 422 422 return signal; 423 423 } 424 424 425 + static bool i2c_read( 426 + struct ddc_service *ddc, 427 + uint32_t address, 428 + uint8_t *buffer, 429 + uint32_t len) 430 + { 431 + uint8_t offs_data = 0; 432 + struct i2c_payload payloads[2] = { 433 + { 434 + .write = true, 435 + .address = address, 436 + .length = 1, 437 + .data = &offs_data }, 438 + { 439 + .write = false, 440 + .address = address, 441 + .length = len, 442 + .data = buffer } }; 443 + 444 + struct i2c_command command = { 445 + .payloads = payloads, 446 + .number_of_payloads = 2, 447 + .engine = DDC_I2C_COMMAND_ENGINE, 448 + .speed = ddc->ctx->dc->caps.i2c_speed_in_khz }; 449 + 450 + return dm_helpers_submit_i2c( 451 + ddc->ctx, 452 + ddc->link, 453 + &command); 454 + } 455 + 456 + enum { 457 + DP_SINK_CAP_SIZE = 458 + DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1 459 + }; 460 + 461 + static void query_dp_dual_mode_adaptor( 462 + struct ddc_service *ddc, 463 + struct display_sink_capability *sink_cap) 464 + { 465 + uint8_t i; 466 + bool is_valid_hdmi_signature; 467 + enum display_dongle_type *dongle = &sink_cap->dongle_type; 468 + uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE]; 469 + bool is_type2_dongle = false; 470 + int retry_count = 2; 471 + struct dp_hdmi_dongle_signature_data *dongle_signature; 472 + 473 + /* Assume we have no valid DP passive dongle connected */ 474 + *dongle = DISPLAY_DONGLE_NONE; 475 + sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK; 476 + 477 + /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/ 478 + if (!i2c_read( 479 + ddc, 480 + DP_HDMI_DONGLE_ADDRESS, 481 + type2_dongle_buf, 482 + sizeof(type2_dongle_buf))) { 483 + /* Passive HDMI dongles can sometimes fail here without retrying*/ 484 + while (retry_count > 0) { 485 + if (i2c_read(ddc, 486 + DP_HDMI_DONGLE_ADDRESS, 487 + type2_dongle_buf, 488 + sizeof(type2_dongle_buf))) 489 + break; 490 + retry_count--; 491 + } 492 + if (retry_count == 0) { 493 + *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE; 494 + sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK; 495 + 496 + CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf), 497 + "DP-DVI passive dongle %dMhz: ", 498 + DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000); 499 + return; 500 + } 501 + } 502 + 503 + /* Check if Type 2 dongle.*/ 504 + if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID) 505 + is_type2_dongle = true; 506 + 507 + dongle_signature = 508 + (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf; 509 + 510 + is_valid_hdmi_signature = true; 511 + 512 + /* Check EOT */ 513 + if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) { 514 + is_valid_hdmi_signature = false; 515 + } 516 + 517 + /* Check signature */ 518 + for (i = 0; i < sizeof(dongle_signature->id); ++i) { 519 + /* If its not the right signature, 520 + * skip mismatch in subversion byte.*/ 521 + if (dongle_signature->id[i] != 522 + dp_hdmi_dongle_signature_str[i] && i != 3) { 523 + 524 + if (is_type2_dongle) { 525 + is_valid_hdmi_signature = false; 526 + break; 527 + } 528 + 529 + } 530 + } 531 + 532 + if (is_type2_dongle) { 533 + uint32_t max_tmds_clk = 534 + type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK]; 535 + 536 + max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2; 537 + 538 + if (0 == max_tmds_clk || 539 + max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK || 540 + max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) { 541 + *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE; 542 + 543 + CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 544 + sizeof(type2_dongle_buf), 545 + "DP-DVI passive dongle %dMhz: ", 546 + DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000); 547 + } else { 548 + if (is_valid_hdmi_signature == true) { 549 + *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE; 550 + 551 + CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 552 + sizeof(type2_dongle_buf), 553 + "Type 2 DP-HDMI passive dongle %dMhz: ", 554 + max_tmds_clk); 555 + } else { 556 + *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE; 557 + 558 + CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 559 + sizeof(type2_dongle_buf), 560 + "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ", 561 + max_tmds_clk); 562 + 563 + } 564 + 565 + /* Multiply by 1000 to convert to kHz. */ 566 + sink_cap->max_hdmi_pixel_clock = 567 + max_tmds_clk * 1000; 568 + } 569 + sink_cap->is_dongle_type_one = false; 570 + 571 + } else { 572 + if (is_valid_hdmi_signature == true) { 573 + *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE; 574 + 575 + CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 576 + sizeof(type2_dongle_buf), 577 + "Type 1 DP-HDMI passive dongle %dMhz: ", 578 + sink_cap->max_hdmi_pixel_clock / 1000); 579 + } else { 580 + *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE; 581 + 582 + CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 583 + sizeof(type2_dongle_buf), 584 + "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ", 585 + sink_cap->max_hdmi_pixel_clock / 1000); 586 + } 587 + sink_cap->is_dongle_type_one = true; 588 + } 589 + 590 + return; 591 + } 592 + 425 593 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc, 426 594 struct display_sink_capability *sink_cap, 427 595 struct audio_support *audio_support) 428 596 { 429 - dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap); 597 + query_dp_dual_mode_adaptor(ddc, sink_cap); 430 598 431 599 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type, 432 600 audio_support); ··· 1214 1046 else 1215 1047 link->dpcd_sink_count = 1; 1216 1048 1217 - dal_ddc_service_set_transaction_type(link->ddc, 1049 + set_ddc_transaction_type(link->ddc, 1218 1050 sink_caps.transaction_type); 1219 1051 1220 1052 link->aux_mode = 1221 - dal_ddc_service_is_in_aux_transaction_mode(link->ddc); 1053 + link_is_in_aux_transaction_mode(link->ddc); 1222 1054 1223 1055 sink_init_data.link = link; 1224 1056 sink_init_data.sink_signal = sink_caps.signal; ··· 1433 1265 1434 1266 channel = CHANNEL_ID_UNKNOWN; 1435 1267 1436 - ddc = dal_ddc_service_get_ddc_pin(link->ddc); 1268 + ddc = get_ddc_pin(link->ddc); 1437 1269 1438 1270 if (ddc) { 1439 1271 switch (dal_ddc_get_line(ddc)) { ··· 1670 1502 ddc_service_init_data.ctx = link->ctx; 1671 1503 ddc_service_init_data.id = link->link_id; 1672 1504 ddc_service_init_data.link = link; 1673 - link->ddc = dal_ddc_service_create(&ddc_service_init_data); 1505 + link->ddc = link_create_ddc_service(&ddc_service_init_data); 1674 1506 1675 1507 if (!link->ddc) { 1676 1508 DC_ERROR("Failed to create ddc_service!\n"); ··· 1683 1515 } 1684 1516 1685 1517 link->ddc_hw_inst = 1686 - dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc)); 1518 + dal_ddc_get_line(get_ddc_pin(link->ddc)); 1687 1519 1688 1520 1689 1521 if (link->dc->res_pool->funcs->panel_cntl_create && ··· 1820 1652 if (link->panel_cntl != NULL) 1821 1653 link->panel_cntl->funcs->destroy(&link->panel_cntl); 1822 1654 panel_cntl_create_fail: 1823 - dal_ddc_service_destroy(&link->ddc); 1655 + link_destroy_ddc_service(&link->ddc); 1824 1656 ddc_create_fail: 1825 1657 create_fail: 1826 1658 ··· 1878 1710 /* Set indicator for dpia link so that ddc won't be created */ 1879 1711 ddc_service_init_data.is_dpia_link = true; 1880 1712 1881 - link->ddc = dal_ddc_service_create(&ddc_service_init_data); 1713 + link->ddc = link_create_ddc_service(&ddc_service_init_data); 1882 1714 if (!link->ddc) { 1883 1715 DC_ERROR("Failed to create ddc_service!\n"); 1884 1716 goto ddc_create_fail; ··· 2346 2178 value = settings->reg_settings[i].i2c_reg_val; 2347 2179 else { 2348 2180 i2c_success = 2349 - dal_ddc_service_query_ddc_data( 2181 + link_query_ddc_data( 2350 2182 pipe_ctx->stream->link->ddc, 2351 2183 slave_address, &offset, 1, &value, 1); 2352 2184 if (!i2c_success) ··· 2396 2228 value = settings->reg_settings_6g[i].i2c_reg_val; 2397 2229 else { 2398 2230 i2c_success = 2399 - dal_ddc_service_query_ddc_data( 2231 + link_query_ddc_data( 2400 2232 pipe_ctx->stream->link->ddc, 2401 2233 slave_address, &offset, 1, &value, 1); 2402 2234 if (!i2c_success) ··· 2694 2526 } 2695 2527 2696 2528 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2697 - dal_ddc_service_write_scdc_data( 2529 + write_scdc_data( 2698 2530 stream->link->ddc, 2699 2531 stream->phy_pix_clk, 2700 2532 stream->timing.flags.LTE_340MCSC_SCRAMBLE); ··· 2715 2547 stream->phy_pix_clk); 2716 2548 2717 2549 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2718 - dal_ddc_service_read_scdc_data(link->ddc); 2550 + read_scdc_data(link->ddc); 2719 2551 } 2720 2552 2721 2553 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) ··· 4480 4312 unsigned short masked_chip_caps = link->chip_caps & 4481 4313 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 4482 4314 //Need to inform that sink is going to use legacy HDMI mode. 4483 - dal_ddc_service_write_scdc_data( 4315 + write_scdc_data( 4484 4316 link->ddc, 4485 4317 165000,//vbios only handles 165Mhz. 4486 4318 false);
+28
drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
··· 77 77 uint8_t *data; 78 78 }; 79 79 80 + struct aux_payload { 81 + /* set following flag to read/write I2C data, 82 + * reset it to read/write DPCD data */ 83 + bool i2c_over_aux; 84 + /* set following flag to write data, 85 + * reset it to read data */ 86 + bool write; 87 + bool mot; 88 + bool write_status_update; 89 + 90 + uint32_t address; 91 + uint32_t length; 92 + uint8_t *data; 93 + /* 94 + * used to return the reply type of the transaction 95 + * ignored if NULL 96 + */ 97 + uint8_t *reply; 98 + /* expressed in milliseconds 99 + * zero means "use default value" 100 + */ 101 + uint32_t defer_delay; 102 + 103 + }; 104 + #define DEFAULT_AUX_MAX_DATA_SIZE 16 105 + 80 106 struct i2c_payload { 81 107 bool write; 82 108 uint8_t address; ··· 115 89 I2C_COMMAND_ENGINE_SW, 116 90 I2C_COMMAND_ENGINE_HW 117 91 }; 92 + 93 + #define DDC_I2C_COMMAND_ENGINE I2C_COMMAND_ENGINE_SW 118 94 119 95 struct i2c_command { 120 96 struct i2c_payload *payloads;
+114
drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h
··· 1 + /* 2 + * Copyright 2022 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + * Authors: AMD 23 + * 24 + */ 25 + 26 + #ifndef DC_HDMI_TYPES_H 27 + #define DC_HDMI_TYPES_H 28 + 29 + #include "os_types.h" 30 + 31 + /* Address range from 0x00 to 0x1F.*/ 32 + #define DP_ADAPTOR_TYPE2_SIZE 0x20 33 + #define DP_ADAPTOR_TYPE2_REG_ID 0x10 34 + #define DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK 0x1D 35 + /* Identifies adaptor as Dual-mode adaptor */ 36 + #define DP_ADAPTOR_TYPE2_ID 0xA0 37 + /* MHz*/ 38 + #define DP_ADAPTOR_TYPE2_MAX_TMDS_CLK 600 39 + /* MHz*/ 40 + #define DP_ADAPTOR_TYPE2_MIN_TMDS_CLK 25 41 + /* kHZ*/ 42 + #define DP_ADAPTOR_DVI_MAX_TMDS_CLK 165000 43 + /* kHZ*/ 44 + #define DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK 165000 45 + 46 + struct dp_hdmi_dongle_signature_data { 47 + int8_t id[15];/* "DP-HDMI ADAPTOR"*/ 48 + uint8_t eot;/* end of transmition '\x4' */ 49 + }; 50 + 51 + /* DP-HDMI dongle slave address for retrieving dongle signature*/ 52 + #define DP_HDMI_DONGLE_ADDRESS 0x40 53 + static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR"; 54 + #define DP_HDMI_DONGLE_SIGNATURE_EOT 0x04 55 + 56 + 57 + /* SCDC Address defines (HDMI 2.0)*/ 58 + #define HDMI_SCDC_WRITE_UPDATE_0_ARRAY 3 59 + #define HDMI_SCDC_ADDRESS 0x54 60 + #define HDMI_SCDC_SINK_VERSION 0x01 61 + #define HDMI_SCDC_SOURCE_VERSION 0x02 62 + #define HDMI_SCDC_UPDATE_0 0x10 63 + #define HDMI_SCDC_TMDS_CONFIG 0x20 64 + #define HDMI_SCDC_SCRAMBLER_STATUS 0x21 65 + #define HDMI_SCDC_CONFIG_0 0x30 66 + #define HDMI_SCDC_CONFIG_1 0x31 67 + #define HDMI_SCDC_SOURCE_TEST_REQ 0x35 68 + #define HDMI_SCDC_STATUS_FLAGS 0x40 69 + #define HDMI_SCDC_ERR_DETECT 0x50 70 + #define HDMI_SCDC_TEST_CONFIG 0xC0 71 + 72 + union hdmi_scdc_update_read_data { 73 + uint8_t byte[2]; 74 + struct { 75 + uint8_t STATUS_UPDATE:1; 76 + uint8_t CED_UPDATE:1; 77 + uint8_t RR_TEST:1; 78 + uint8_t RESERVED:5; 79 + uint8_t RESERVED2:8; 80 + } fields; 81 + }; 82 + 83 + union hdmi_scdc_status_flags_data { 84 + uint8_t byte; 85 + struct { 86 + uint8_t CLOCK_DETECTED:1; 87 + uint8_t CH0_LOCKED:1; 88 + uint8_t CH1_LOCKED:1; 89 + uint8_t CH2_LOCKED:1; 90 + uint8_t RESERVED:4; 91 + } fields; 92 + }; 93 + 94 + union hdmi_scdc_ced_data { 95 + uint8_t byte[11]; 96 + struct { 97 + uint8_t CH0_8LOW:8; 98 + uint8_t CH0_7HIGH:7; 99 + uint8_t CH0_VALID:1; 100 + uint8_t CH1_8LOW:8; 101 + uint8_t CH1_7HIGH:7; 102 + uint8_t CH1_VALID:1; 103 + uint8_t CH2_8LOW:8; 104 + uint8_t CH2_7HIGH:7; 105 + uint8_t CH2_VALID:1; 106 + uint8_t CHECKSUM:8; 107 + uint8_t RESERVED:8; 108 + uint8_t RESERVED2:8; 109 + uint8_t RESERVED3:8; 110 + uint8_t RESERVED4:4; 111 + } fields; 112 + }; 113 + 114 + #endif /* DC_HDMI_TYPES_H */
+10
drivers/gpu/drm/amd/display/dc/dc_link.h
··· 31 31 #include "grph_object_defs.h" 32 32 33 33 struct link_resource; 34 + enum aux_return_code_type; 34 35 35 36 enum dc_link_fec_state { 36 37 dc_link_fec_not_ready, ··· 592 591 593 592 /* Destruct the mst topology of the link and reset the allocated payload table */ 594 593 bool reset_cur_dp_mst_topology(struct dc_link *link); 594 + 595 + /* Attempt to transfer the given aux payload. This function does not perform 596 + * retries or handle error states. The reply is returned in the payload->reply 597 + * and the result through operation_result. Returns the number of bytes 598 + * transferred,or -1 on a failure. 599 + */ 600 + int dc_link_aux_transfer_raw(struct ddc_service *ddc, 601 + struct aux_payload *payload, 602 + enum aux_return_code_type *operation_result); 595 603 #endif /* DC_LINK_H_ */
+1
drivers/gpu/drm/amd/display/dc/dc_types.h
··· 33 33 #include "fixed31_32.h" 34 34 #include "irq_types.h" 35 35 #include "dc_dp_types.h" 36 + #include "dc_hdmi_types.h" 36 37 #include "dc_hw_types.h" 37 38 #include "dal_types.h" 38 39 #include "grph_object_defs.h"
+1 -1
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
··· 26 26 #ifndef __DAL_AUX_ENGINE_DCE110_H__ 27 27 #define __DAL_AUX_ENGINE_DCE110_H__ 28 28 29 - #include "i2caux_interface.h" 29 + #include "gpio_service_interface.h" 30 30 #include "inc/hw/aux_engine.h" 31 31 32 32 enum aux_return_code_type;
+3 -3
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
··· 62 62 #include "dml/display_mode_vba.h" 63 63 #include "dcn20_dccg.h" 64 64 #include "dcn20_vmid.h" 65 - #include "dc_link_ddc.h" 66 65 #include "dce/dce_panel_cntl.h" 67 66 68 67 #include "navi10_ip_offset.h" ··· 89 90 90 91 #include "amdgpu_socbb.h" 91 92 93 + #include "link.h" 92 94 #define DC_LOGGER_INIT(logger) 93 95 94 96 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL ··· 1214 1214 dcn20_pp_smu_destroy(&pool->base.pp_smu); 1215 1215 1216 1216 if (pool->base.oem_device != NULL) 1217 - dal_ddc_service_destroy(&pool->base.oem_device); 1217 + link_destroy_ddc_service(&pool->base.oem_device); 1218 1218 } 1219 1219 1220 1220 struct hubp *dcn20_hubp_create( ··· 2769 2769 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2770 2770 ddc_init_data.id.enum_id = 0; 2771 2771 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2772 - pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 2772 + pool->base.oem_device = link_create_ddc_service(&ddc_init_data); 2773 2773 } else { 2774 2774 pool->base.oem_device = NULL; 2775 2775 }
+3 -3
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
··· 60 60 #include "dml/display_mode_vba.h" 61 61 #include "dcn30/dcn30_dccg.h" 62 62 #include "dcn10/dcn10_resource.h" 63 - #include "dc_link_ddc.h" 63 + #include "link.h" 64 64 #include "dce/dce_panel_cntl.h" 65 65 66 66 #include "dcn30/dcn30_dwb.h" ··· 1208 1208 dcn_dccg_destroy(&pool->base.dccg); 1209 1209 1210 1210 if (pool->base.oem_device != NULL) 1211 - dal_ddc_service_destroy(&pool->base.oem_device); 1211 + link_destroy_ddc_service(&pool->base.oem_device); 1212 1212 } 1213 1213 1214 1214 static struct hubp *dcn30_hubp_create( ··· 2590 2590 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2591 2591 ddc_init_data.id.enum_id = 0; 2592 2592 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2593 - pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 2593 + pool->base.oem_device = link_create_ddc_service(&ddc_init_data); 2594 2594 } else { 2595 2595 pool->base.oem_device = NULL; 2596 2596 }
+16
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
··· 47 47 48 48 #include "dcn10/dcn10_resource.h" 49 49 50 + #include "link.h" 50 51 #include "dce/dce_abm.h" 51 52 #include "dce/dce_audio.h" 52 53 #include "dce/dce_aux.h" ··· 1126 1125 1127 1126 if (pool->dccg != NULL) 1128 1127 dcn_dccg_destroy(&pool->dccg); 1128 + 1129 + if (pool->oem_device != NULL) 1130 + link_destroy_ddc_service(&pool->oem_device); 1129 1131 } 1130 1132 1131 1133 static void dcn302_destroy_resource_pool(struct resource_pool **pool) ··· 1220 1216 int i; 1221 1217 struct dc_context *ctx = dc->ctx; 1222 1218 struct irq_service_init_data init_data; 1219 + struct ddc_service_init_data ddc_init_data = {0}; 1223 1220 1224 1221 ctx->dc_bios->regs = &bios_regs; 1225 1222 ··· 1501 1496 dc->caps.planes[i] = plane_cap; 1502 1497 1503 1498 dc->cap_funcs = cap_funcs; 1499 + 1500 + if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1501 + ddc_init_data.ctx = dc->ctx; 1502 + ddc_init_data.link = NULL; 1503 + ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1504 + ddc_init_data.id.enum_id = 0; 1505 + ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1506 + pool->oem_device = link_create_ddc_service(&ddc_init_data); 1507 + } else { 1508 + pool->oem_device = NULL; 1509 + } 1504 1510 1505 1511 return true; 1506 1512
+3 -3
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
··· 29 29 30 30 #include "dcn10/dcn10_resource.h" 31 31 32 - #include "dc_link_ddc.h" 32 + #include "link.h" 33 33 34 34 #include "dce/dce_abm.h" 35 35 #include "dce/dce_audio.h" ··· 1054 1054 dcn_dccg_destroy(&pool->dccg); 1055 1055 1056 1056 if (pool->oem_device != NULL) 1057 - dal_ddc_service_destroy(&pool->oem_device); 1057 + link_destroy_ddc_service(&pool->oem_device); 1058 1058 } 1059 1059 1060 1060 static void dcn303_destroy_resource_pool(struct resource_pool **pool) ··· 1421 1421 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1422 1422 ddc_init_data.id.enum_id = 0; 1423 1423 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1424 - pool->oem_device = dal_ddc_service_create(&ddc_init_data); 1424 + pool->oem_device = link_create_ddc_service(&ddc_init_data); 1425 1425 } else { 1426 1426 pool->oem_device = NULL; 1427 1427 }
+3 -3
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
··· 69 69 #include "dml/display_mode_vba.h" 70 70 #include "dcn32/dcn32_dccg.h" 71 71 #include "dcn10/dcn10_resource.h" 72 - #include "dc_link_ddc.h" 72 + #include "link.h" 73 73 #include "dcn31/dcn31_panel_cntl.h" 74 74 75 75 #include "dcn30/dcn30_dwb.h" ··· 1508 1508 dcn_dccg_destroy(&pool->base.dccg); 1509 1509 1510 1510 if (pool->base.oem_device != NULL) 1511 - dal_ddc_service_destroy(&pool->base.oem_device); 1511 + link_destroy_ddc_service(&pool->base.oem_device); 1512 1512 } 1513 1513 1514 1514 ··· 2450 2450 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2451 2451 ddc_init_data.id.enum_id = 0; 2452 2452 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2453 - pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 2453 + pool->base.oem_device = link_create_ddc_service(&ddc_init_data); 2454 2454 } else { 2455 2455 pool->base.oem_device = NULL; 2456 2456 }
+3 -3
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
··· 73 73 #include "dml/display_mode_vba.h" 74 74 #include "dcn32/dcn32_dccg.h" 75 75 #include "dcn10/dcn10_resource.h" 76 - #include "dc_link_ddc.h" 76 + #include "link.h" 77 77 #include "dcn31/dcn31_panel_cntl.h" 78 78 79 79 #include "dcn30/dcn30_dwb.h" ··· 1493 1493 dcn_dccg_destroy(&pool->base.dccg); 1494 1494 1495 1495 if (pool->base.oem_device != NULL) 1496 - dal_ddc_service_destroy(&pool->base.oem_device); 1496 + link_destroy_ddc_service(&pool->base.oem_device); 1497 1497 } 1498 1498 1499 1499 ··· 1991 1991 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1992 1992 ddc_init_data.id.enum_id = 0; 1993 1993 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1994 - pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 1994 + pool->base.oem_device = link_create_ddc_service(&ddc_init_data); 1995 1995 } else { 1996 1996 pool->base.oem_device = NULL; 1997 1997 }
+1 -2
drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
··· 28 28 #include "dm_services.h" 29 29 #include "dm_helpers.h" 30 30 #include "include/hdcp_types.h" 31 - #include "include/i2caux_interface.h" 32 31 #include "include/signal_types.h" 33 32 #include "core_types.h" 34 - #include "dc_link_ddc.h" 33 + #include "link.h" 35 34 #include "link_hwss.h" 36 35 #include "inc/link_dpcd.h" 37 36
+6 -2
drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h
··· 27 27 #define __DAL_AUX_ENGINE_H__ 28 28 29 29 #include "dc_ddc_types.h" 30 - #include "include/i2caux_interface.h" 31 30 32 31 enum aux_return_code_type; 33 32 ··· 80 81 I2CAUX_DEFAULT_I2C_SW_SPEED = 50 81 82 }; 82 83 83 - union aux_config; 84 + union aux_config { 85 + struct { 86 + uint32_t ALLOW_AUX_WHEN_HPD_LOW:1; 87 + } bits; 88 + uint32_t raw; 89 + }; 84 90 85 91 struct aux_engine { 86 92 uint32_t inst;
+37
drivers/gpu/drm/amd/display/dc/inc/link.h
··· 44 44 struct graphics_object_id link_id, 45 45 struct gpio_service *gpio_service); 46 46 47 + struct ddc_service_init_data { 48 + struct graphics_object_id id; 49 + struct dc_context *ctx; 50 + struct dc_link *link; 51 + bool is_dpia_link; 52 + }; 53 + 54 + struct ddc_service *link_create_ddc_service( 55 + struct ddc_service_init_data *ddc_init_data); 56 + 57 + void link_destroy_ddc_service(struct ddc_service **ddc); 58 + 59 + bool link_is_in_aux_transaction_mode(struct ddc_service *ddc); 60 + 61 + bool link_query_ddc_data( 62 + struct ddc_service *ddc, 63 + uint32_t address, 64 + uint8_t *write_buf, 65 + uint32_t write_size, 66 + uint8_t *read_buf, 67 + uint32_t read_size); 68 + 69 + 70 + /* Attempt to submit an aux payload, retrying on timeouts, defers, and busy 71 + * states as outlined in the DP spec. Returns true if the request was 72 + * successful. 73 + * 74 + * NOTE: The function requires explicit mutex on DM side in order to prevent 75 + * potential race condition. DC components should call the dpcd read/write 76 + * function in dm_helpers in order to access dpcd safely 77 + */ 78 + bool link_aux_transfer_with_retries_no_mutex(struct ddc_service *ddc, 79 + struct aux_payload *payload); 80 + 81 + uint32_t link_get_aux_defer_delay(struct ddc_service *ddc); 82 + 83 + 47 84 #endif /* __DC_LINK_HPD_H__ */
+1 -1
drivers/gpu/drm/amd/display/dc/link/Makefile
··· 24 24 # PHY, HPD, DDC and etc). 25 25 26 26 LINK = link_hwss_dio.o link_hwss_dpia.o link_hwss_hpo_dp.o link_dp_trace.o \ 27 - link_hpd.o 27 + link_hpd.o link_ddc.o 28 28 29 29 AMD_DAL_LINK = $(addprefix $(AMDDALPATH)/dc/link/,$(LINK)) 30 30