tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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ARM: at91: add clk_lookup entry for RTT devices

First export the clk32k clk.
Then add clk_lookup entries for RTT devices so that rtc-at91sam9 driver
can retrieve and manipulate the slow clk.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Johan Hovold <johan@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

authored by

Boris BREZILLON and committed by
Nicolas Ferre a9825021 3969eb48

+14 -1
+2
arch/arm/mach-at91/at91sam9260.c
··· 217 217 CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk), 218 218 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk), 219 219 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk), 220 + CLKDEV_CON_DEV_ID(NULL, "rtc-at91sam9.0", &clk32k), 220 221 /* more usart lookup table for DT entries */ 221 222 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), 222 223 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk), ··· 238 237 CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk), 239 238 CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk), 240 239 CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk), 240 + CLKDEV_CON_DEV_ID(NULL, "fffffd20.rtc", &clk32k), 241 241 /* fake hclk clock */ 242 242 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), 243 243 CLKDEV_CON_ID("pioA", &pioA_clk),
+2
arch/arm/mach-at91/at91sam9261.c
··· 192 192 CLKDEV_CON_ID("pioA", &pioA_clk), 193 193 CLKDEV_CON_ID("pioB", &pioB_clk), 194 194 CLKDEV_CON_ID("pioC", &pioC_clk), 195 + CLKDEV_CON_DEV_ID(NULL, "rtc-at91sam9.0", &clk32k), 195 196 /* more lookup table for DT entries */ 196 197 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), 197 198 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk), ··· 210 209 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk), 211 210 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk), 212 211 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk), 212 + CLKDEV_CON_DEV_ID(NULL, "fffffd20.rtc", &clk32k), 213 213 }; 214 214 215 215 static struct clk_lookup usart_clocks_lookups[] = {
+4
arch/arm/mach-at91/at91sam9263.c
··· 201 201 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk), 202 202 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk), 203 203 CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk), 204 + CLKDEV_CON_DEV_ID(NULL, "rtc-at91sam9.0", &clk32k), 205 + CLKDEV_CON_DEV_ID(NULL, "rtc-at91sam9.1", &clk32k), 204 206 /* fake hclk clock */ 205 207 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), 206 208 CLKDEV_CON_ID("pioA", &pioA_clk), ··· 229 227 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk), 230 228 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk), 231 229 CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk), 230 + CLKDEV_CON_DEV_ID(NULL, "fffffd20.rtc", &clk32k), 231 + CLKDEV_CON_DEV_ID(NULL, "fffffd50.rtc", &clk32k), 232 232 }; 233 233 234 234 static struct clk_lookup usart_clocks_lookups[] = {
+2
arch/arm/mach-at91/at91sam9g45.c
··· 254 254 CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk), 255 255 CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk), 256 256 CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk), 257 + CLKDEV_CON_DEV_ID(NULL, "rtc-at91sam9.0", &clk32k), 257 258 /* more usart lookup table for DT entries */ 258 259 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck), 259 260 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk), ··· 281 280 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk), 282 281 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk), 283 282 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk), 283 + CLKDEV_CON_DEV_ID(NULL, "fffffd20.rtc", &clk32k), 284 284 285 285 CLKDEV_CON_ID("pioA", &pioA_clk), 286 286 CLKDEV_CON_ID("pioB", &pioB_clk),
+2
arch/arm/mach-at91/at91sam9rl.c
··· 205 205 CLKDEV_CON_ID("pioB", &pioB_clk), 206 206 CLKDEV_CON_ID("pioC", &pioC_clk), 207 207 CLKDEV_CON_ID("pioD", &pioD_clk), 208 + CLKDEV_CON_DEV_ID(NULL, "rtc-at91sam9.0", &clk32k), 208 209 /* more lookup table for DT entries */ 209 210 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), 210 211 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk), ··· 224 223 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk), 225 224 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk), 226 225 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk), 226 + CLKDEV_CON_DEV_ID(NULL, "fffffd20.rtc", &clk32k), 227 227 CLKDEV_CON_ID("adc_clk", &tsc_clk), 228 228 }; 229 229
+1 -1
arch/arm/mach-at91/clock.c
··· 115 115 * 48 MHz (unless no USB function clocks are needed). The main clock and 116 116 * both PLLs are turned off to run in "slow clock mode" (system suspend). 117 117 */ 118 - static struct clk clk32k = { 118 + struct clk clk32k = { 119 119 .name = "clk32k", 120 120 .rate_hz = AT91_SLOW_CLOCK, 121 121 .users = 1, /* always on */
+1
arch/arm/mach-at91/clock.h
··· 34 34 extern int __init clk_register(struct clk *clk); 35 35 extern struct clk mck; 36 36 extern struct clk utmi_clk; 37 + extern struct clk clk32k; 37 38 38 39 #define CLKDEV_CON_ID(_id, _clk) \ 39 40 { \