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perf vendor events arm64: Add AmpereOne core PMU events
Add JSON files for AmpereOne core PMU events.
Reviewed-by: John Garry <john.g.garry@oracle.com>
Signed-off-by: Doug Rady <dcrady@os.amperecomputing.com>
Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20230427223220.1068356-1-ilkka@os.amperecomputing.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
authored by
Ilkka Koskinen
and committed by
Arnaldo Carvalho de Melo
a9650b7f
40bf1cb0
+1080
+17
tools/perf/pmu-events/arch/arm64/ampere/ampereone/branch.json
+17
tools/perf/pmu-events/arch/arm64/ampere/ampereone/branch.json
+32
tools/perf/pmu-events/arch/arm64/ampere/ampereone/bus.json
+32
tools/perf/pmu-events/arch/arm64/ampere/ampereone/bus.json
···
1
+
[
2
+
{
3
+
"ArchStdEvent": "CPU_CYCLES"
4
+
},
5
+
{
6
+
"ArchStdEvent": "BUS_CYCLES"
7
+
},
8
+
{
9
+
"ArchStdEvent": "BUS_ACCESS_RD"
10
+
},
11
+
{
12
+
"ArchStdEvent": "BUS_ACCESS_WR"
13
+
},
14
+
{
15
+
"ArchStdEvent": "BUS_ACCESS_SHARED"
16
+
},
17
+
{
18
+
"ArchStdEvent": "BUS_ACCESS_NOT_SHARED"
19
+
},
20
+
{
21
+
"ArchStdEvent": "BUS_ACCESS_NORMAL"
22
+
},
23
+
{
24
+
"ArchStdEvent": "BUS_ACCESS_PERIPH"
25
+
},
26
+
{
27
+
"ArchStdEvent": "BUS_ACCESS"
28
+
},
29
+
{
30
+
"ArchStdEvent": "CNT_CYCLES"
31
+
}
32
+
]
+104
tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json
+104
tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json
···
1
+
[
2
+
{
3
+
"ArchStdEvent": "L1D_CACHE_RD"
4
+
},
5
+
{
6
+
"ArchStdEvent": "L1D_CACHE_WR"
7
+
},
8
+
{
9
+
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
10
+
},
11
+
{
12
+
"ArchStdEvent": "L1D_CACHE_INVAL"
13
+
},
14
+
{
15
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"ArchStdEvent": "L1D_TLB_REFILL_RD"
16
+
},
17
+
{
18
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"ArchStdEvent": "L1D_TLB_REFILL_WR"
19
+
},
20
+
{
21
+
"ArchStdEvent": "L2D_CACHE_RD"
22
+
},
23
+
{
24
+
"ArchStdEvent": "L2D_CACHE_WR"
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+
},
26
+
{
27
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"ArchStdEvent": "L2D_CACHE_REFILL_RD"
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+
},
29
+
{
30
+
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
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+
},
32
+
{
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+
"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
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+
},
35
+
{
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+
"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
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+
},
38
+
{
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+
"ArchStdEvent": "L2D_CACHE_INVAL"
40
+
},
41
+
{
42
+
"ArchStdEvent": "L1I_CACHE_REFILL"
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+
},
44
+
{
45
+
"ArchStdEvent": "L1I_TLB_REFILL"
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+
},
47
+
{
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+
"ArchStdEvent": "L1D_CACHE_REFILL"
49
+
},
50
+
{
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"ArchStdEvent": "L1D_CACHE"
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+
},
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+
{
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+
"ArchStdEvent": "L1D_TLB_REFILL"
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+
},
56
+
{
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"ArchStdEvent": "L1I_CACHE"
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+
},
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+
{
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+
"ArchStdEvent": "L2D_CACHE"
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+
},
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+
{
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+
"ArchStdEvent": "L2D_CACHE_REFILL"
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+
},
65
+
{
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+
"ArchStdEvent": "L2D_CACHE_WB"
67
+
},
68
+
{
69
+
"ArchStdEvent": "L1D_TLB"
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+
},
71
+
{
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+
"ArchStdEvent": "L1I_TLB"
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+
},
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+
{
75
+
"ArchStdEvent": "L2D_TLB_REFILL"
76
+
},
77
+
{
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+
"ArchStdEvent": "L2I_TLB_REFILL"
79
+
},
80
+
{
81
+
"ArchStdEvent": "L2D_TLB"
82
+
},
83
+
{
84
+
"ArchStdEvent": "L2I_TLB"
85
+
},
86
+
{
87
+
"ArchStdEvent": "DTLB_WALK"
88
+
},
89
+
{
90
+
"ArchStdEvent": "ITLB_WALK"
91
+
},
92
+
{
93
+
"ArchStdEvent": "L1D_CACHE_LMISS_RD"
94
+
},
95
+
{
96
+
"ArchStdEvent": "L1D_CACHE_LMISS"
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+
},
98
+
{
99
+
"ArchStdEvent": "L1I_CACHE_LMISS"
100
+
},
101
+
{
102
+
"ArchStdEvent": "L2D_CACHE_LMISS_RD"
103
+
}
104
+
]
+698
tools/perf/pmu-events/arch/arm64/ampere/ampereone/core-imp-def.json
+698
tools/perf/pmu-events/arch/arm64/ampere/ampereone/core-imp-def.json
···
1
+
[
2
+
{
3
+
"PublicDescription": "Level 2 prefetch requests, refilled to L2 cache",
4
+
"EventCode": "0x10A",
5
+
"EventName": "L2_PREFETCH_REFILL",
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+
"BriefDescription": "Level 2 prefetch requests, refilled to L2 cache"
7
+
},
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+
{
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+
"PublicDescription": "Level 2 prefetch requests, late",
10
+
"EventCode": "0x10B",
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+
"EventName": "L2_PREFETCH_UPGRADE",
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+
"BriefDescription": "Level 2 prefetch requests, late"
13
+
},
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+
{
15
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"PublicDescription": "Predictable branch speculatively executed that hit any level of BTB",
16
+
"EventCode": "0x110",
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+
"EventName": "BPU_HIT_BTB",
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+
"BriefDescription": "Predictable branch speculatively executed that hit any level of BTB"
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+
},
20
+
{
21
+
"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of BTB",
22
+
"EventCode": "0x111",
23
+
"EventName": "BPU_CONDITIONAL_BRANCH_HIT_BTB",
24
+
"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB"
25
+
},
26
+
{
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+
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor",
28
+
"EventCode": "0x112",
29
+
"EventName": "BPU_HIT_INDIRECT_PREDICTOR",
30
+
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor"
31
+
},
32
+
{
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+
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor",
34
+
"EventCode": "0x113",
35
+
"EventName": "BPU_HIT_RSB",
36
+
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor"
37
+
},
38
+
{
39
+
"PublicDescription": "Predictable unconditional branch speculatively executed that did not hit any level of BTB",
40
+
"EventCode": "0x114",
41
+
"EventName": "BPU_UNCONDITIONAL_BRANCH_MISS_BTB",
42
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"BriefDescription": "Predictable unconditional branch speculatively executed that did not hit any level of BTB"
43
+
},
44
+
{
45
+
"PublicDescription": "Predictable branch speculatively executed, unpredicted",
46
+
"EventCode": "0x115",
47
+
"EventName": "BPU_BRANCH_NO_HIT",
48
+
"BriefDescription": "Predictable branch speculatively executed, unpredicted"
49
+
},
50
+
{
51
+
"PublicDescription": "Predictable branch speculatively executed that hit any level of BTB that mispredict",
52
+
"EventCode": "0x116",
53
+
"EventName": "BPU_HIT_BTB_AND_MISPREDICT",
54
+
"BriefDescription": "Predictable branch speculatively executed that hit any level of BTB that mispredict"
55
+
},
56
+
{
57
+
"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of BTB that (direction) mispredict",
58
+
"EventCode": "0x117",
59
+
"EventName": "BPU_CONDITIONAL_BRANCH_HIT_BTB_AND_MISPREDICT",
60
+
"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB that (direction) mispredict"
61
+
},
62
+
{
63
+
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor that mispredict",
64
+
"EventCode": "0x118",
65
+
"EventName": "BPU_INDIRECT_BRANCH_HIT_BTB_AND_MISPREDICT",
66
+
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor that mispredict"
67
+
},
68
+
{
69
+
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor that mispredict",
70
+
"EventCode": "0x119",
71
+
"EventName": "BPU_HIT_RSB_AND_MISPREDICT",
72
+
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor that mispredict"
73
+
},
74
+
{
75
+
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the overflow/underflow return predictor that mispredict",
76
+
"EventCode": "0x11a",
77
+
"EventName": "BPU_MISS_RSB_AND_MISPREDICT",
78
+
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the overflow/underflow return predictor that mispredict"
79
+
},
80
+
{
81
+
"PublicDescription": "Predictable branch speculatively executed, unpredicted, that mispredict",
82
+
"EventCode": "0x11b",
83
+
"EventName": "BPU_NO_PREDICTION_MISPREDICT",
84
+
"BriefDescription": "Predictable branch speculatively executed, unpredicted, that mispredict"
85
+
},
86
+
{
87
+
"PublicDescription": "Predictable branch speculatively executed, unpredicted, that mispredict",
88
+
"EventCode": "0x11c",
89
+
"EventName": "BPU_BTB_UPDATE",
90
+
"BriefDescription": "Predictable branch speculatively executed, unpredicted, that mispredict"
91
+
},
92
+
{
93
+
"PublicDescription": "Count predict pipe stalls due to speculative return address predictor full",
94
+
"EventCode": "0x11d",
95
+
"EventName": "BPU_RSB_FULL_STALL",
96
+
"BriefDescription": "Count predict pipe stalls due to speculative return address predictor full"
97
+
},
98
+
{
99
+
"PublicDescription": "Macro-ops speculatively decoded",
100
+
"EventCode": "0x11f",
101
+
"EventName": "ICF_INST_SPEC_DECODE",
102
+
"BriefDescription": "Macro-ops speculatively decoded"
103
+
},
104
+
{
105
+
"PublicDescription": "Flushes",
106
+
"EventCode": "0x120",
107
+
"EventName": "GPC_FLUSH",
108
+
"BriefDescription": "Flushes"
109
+
},
110
+
{
111
+
"PublicDescription": "Flushes due to memory hazards",
112
+
"EventCode": "0x121",
113
+
"EventName": "BPU_FLUSH_MEM_FAULT",
114
+
"BriefDescription": "Flushes due to memory hazards"
115
+
},
116
+
{
117
+
"PublicDescription": "ETM extout bit 0",
118
+
"EventCode": "0x141",
119
+
"EventName": "MSC_ETM_EXTOUT0",
120
+
"BriefDescription": "ETM extout bit 0"
121
+
},
122
+
{
123
+
"PublicDescription": "ETM extout bit 1",
124
+
"EventCode": "0x142",
125
+
"EventName": "MSC_ETM_EXTOUT1",
126
+
"BriefDescription": "ETM extout bit 1"
127
+
},
128
+
{
129
+
"PublicDescription": "ETM extout bit 2",
130
+
"EventCode": "0x143",
131
+
"EventName": "MSC_ETM_EXTOUT2",
132
+
"BriefDescription": "ETM extout bit 2"
133
+
},
134
+
{
135
+
"PublicDescription": "ETM extout bit 3",
136
+
"EventCode": "0x144",
137
+
"EventName": "MSC_ETM_EXTOUT3",
138
+
"BriefDescription": "ETM extout bit 3"
139
+
},
140
+
{
141
+
"PublicDescription": "Bus request sn",
142
+
"EventCode": "0x156",
143
+
"EventName": "L2C_SNOOP",
144
+
"BriefDescription": "Bus request sn"
145
+
},
146
+
{
147
+
"PublicDescription": "L2 TXDAT LCRD blocked",
148
+
"EventCode": "0x169",
149
+
"EventName": "L2C_DAT_CRD_STALL",
150
+
"BriefDescription": "L2 TXDAT LCRD blocked"
151
+
},
152
+
{
153
+
"PublicDescription": "L2 TXRSP LCRD blocked",
154
+
"EventCode": "0x16a",
155
+
"EventName": "L2C_RSP_CRD_STALL",
156
+
"BriefDescription": "L2 TXRSP LCRD blocked"
157
+
},
158
+
{
159
+
"PublicDescription": "L2 TXREQ LCRD blocked",
160
+
"EventCode": "0x16b",
161
+
"EventName": "L2C_REQ_CRD_STALL",
162
+
"BriefDescription": "L2 TXREQ LCRD blocked"
163
+
},
164
+
{
165
+
"PublicDescription": "Early mispredict",
166
+
"EventCode": "0xD100",
167
+
"EventName": "ICF_EARLY_MIS_PRED",
168
+
"BriefDescription": "Early mispredict"
169
+
},
170
+
{
171
+
"PublicDescription": "FEQ full cycles",
172
+
"EventCode": "0xD101",
173
+
"EventName": "ICF_FEQ_FULL",
174
+
"BriefDescription": "FEQ full cycles"
175
+
},
176
+
{
177
+
"PublicDescription": "Instruction FIFO Full",
178
+
"EventCode": "0xD102",
179
+
"EventName": "ICF_INST_FIFO_FULL",
180
+
"BriefDescription": "Instruction FIFO Full"
181
+
},
182
+
{
183
+
"PublicDescription": "L1I TLB miss",
184
+
"EventCode": "0xD103",
185
+
"EventName": "L1I_TLB_MISS",
186
+
"BriefDescription": "L1I TLB miss"
187
+
},
188
+
{
189
+
"PublicDescription": "ICF sent 0 instructions to IDR this cycle",
190
+
"EventCode": "0xD104",
191
+
"EventName": "ICF_STALL",
192
+
"BriefDescription": "ICF sent 0 instructions to IDR this cycle"
193
+
},
194
+
{
195
+
"PublicDescription": "PC FIFO Full",
196
+
"EventCode": "0xD105",
197
+
"EventName": "ICF_PC_FIFO_FULL",
198
+
"BriefDescription": "PC FIFO Full"
199
+
},
200
+
{
201
+
"PublicDescription": "Stall due to BOB ID",
202
+
"EventCode": "0xD200",
203
+
"EventName": "IDR_STALL_BOB_ID",
204
+
"BriefDescription": "Stall due to BOB ID"
205
+
},
206
+
{
207
+
"PublicDescription": "Dispatch stall due to LOB entries",
208
+
"EventCode": "0xD201",
209
+
"EventName": "IDR_STALL_LOB_ID",
210
+
"BriefDescription": "Dispatch stall due to LOB entries"
211
+
},
212
+
{
213
+
"PublicDescription": "Dispatch stall due to SOB entries",
214
+
"EventCode": "0xD202",
215
+
"EventName": "IDR_STALL_SOB_ID",
216
+
"BriefDescription": "Dispatch stall due to SOB entries"
217
+
},
218
+
{
219
+
"PublicDescription": "Dispatch stall due to IXU scheduler entries",
220
+
"EventCode": "0xD203",
221
+
"EventName": "IDR_STALL_IXU_SCHED",
222
+
"BriefDescription": "Dispatch stall due to IXU scheduler entries"
223
+
},
224
+
{
225
+
"PublicDescription": "Dispatch stall due to FSU scheduler entries",
226
+
"EventCode": "0xD204",
227
+
"EventName": "IDR_STALL_FSU_SCHED",
228
+
"BriefDescription": "Dispatch stall due to FSU scheduler entries"
229
+
},
230
+
{
231
+
"PublicDescription": "Dispatch stall due to ROB entries",
232
+
"EventCode": "0xD205",
233
+
"EventName": "IDR_STALL_ROB_ID",
234
+
"BriefDescription": "Dispatch stall due to ROB entries"
235
+
},
236
+
{
237
+
"PublicDescription": "Dispatch stall due to flush (6 cycles)",
238
+
"EventCode": "0xD206",
239
+
"EventName": "IDR_STALL_FLUSH",
240
+
"BriefDescription": "Dispatch stall due to flush (6 cycles)"
241
+
},
242
+
{
243
+
"PublicDescription": "Dispatch stall due to WFI",
244
+
"EventCode": "0xD207",
245
+
"EventName": "IDR_STALL_WFI",
246
+
"BriefDescription": "Dispatch stall due to WFI"
247
+
},
248
+
{
249
+
"PublicDescription": "Number of SWOB drains triggered by timeout",
250
+
"EventCode": "0xD208",
251
+
"EventName": "IDR_STALL_SWOB_TIMEOUT",
252
+
"BriefDescription": "Number of SWOB drains triggered by timeout"
253
+
},
254
+
{
255
+
"PublicDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain",
256
+
"EventCode": "0xD209",
257
+
"EventName": "IDR_STALL_SWOB_RAW",
258
+
"BriefDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain"
259
+
},
260
+
{
261
+
"PublicDescription": "Number of SWOB drains triggered by system register write when SWOB full",
262
+
"EventCode": "0xD20A",
263
+
"EventName": "IDR_STALL_SWOB_FULL",
264
+
"BriefDescription": "Number of SWOB drains triggered by system register write when SWOB full"
265
+
},
266
+
{
267
+
"PublicDescription": "Dispatch stall due to L1 instruction cache miss",
268
+
"EventCode": "0xD20B",
269
+
"EventName": "STALL_FRONTEND_CACHE",
270
+
"BriefDescription": "Dispatch stall due to L1 instruction cache miss"
271
+
},
272
+
{
273
+
"PublicDescription": "Dispatch stall due to L1 instruction TLB miss",
274
+
"EventCode": "0xD20C",
275
+
"EventName": "STALL_FRONTEND_TLB",
276
+
"BriefDescription": "Dispatch stall due to L1 instruction TLB miss"
277
+
},
278
+
{
279
+
"PublicDescription": "Dispatch stall due to L1 data cache miss",
280
+
"EventCode": "0xD20D",
281
+
"EventName": "STALL_BACKEND_CACHE",
282
+
"BriefDescription": "Dispatch stall due to L1 data cache miss"
283
+
},
284
+
{
285
+
"PublicDescription": "Dispatch stall due to L1 data TLB miss",
286
+
"EventCode": "0xD20E",
287
+
"EventName": "STALL_BACKEND_TLB",
288
+
"BriefDescription": "Dispatch stall due to L1 data TLB miss"
289
+
},
290
+
{
291
+
"PublicDescription": "Dispatch stall due to lack of any core resource",
292
+
"EventCode": "0xD20F",
293
+
"EventName": "STALL_BACKEND_RESOURCE",
294
+
"BriefDescription": "Dispatch stall due to lack of any core resource"
295
+
},
296
+
{
297
+
"PublicDescription": "Instructions issued by the scheduler",
298
+
"EventCode": "0xD300",
299
+
"EventName": "IXU_NUM_UOPS_ISSUED",
300
+
"BriefDescription": "Instructions issued by the scheduler"
301
+
},
302
+
{
303
+
"PublicDescription": "Any uop issued was canceled for any reason",
304
+
"EventCode": "0xD301",
305
+
"EventName": "IXU_ISSUE_CANCEL",
306
+
"BriefDescription": "Any uop issued was canceled for any reason"
307
+
},
308
+
{
309
+
"PublicDescription": "A load wakeup to the scheduler has been cancelled",
310
+
"EventCode": "0xD302",
311
+
"EventName": "IXU_LOAD_CANCEL",
312
+
"BriefDescription": "A load wakeup to the scheduler has been cancelled"
313
+
},
314
+
{
315
+
"PublicDescription": "The scheduler had to cancel one slow Uop due to resource conflict",
316
+
"EventCode": "0xD303",
317
+
"EventName": "IXU_SLOW_CANCEL",
318
+
"BriefDescription": "The scheduler had to cancel one slow Uop due to resource conflict"
319
+
},
320
+
{
321
+
"PublicDescription": "Uops issued by the scheduler on IXA",
322
+
"EventCode": "0xD304",
323
+
"EventName": "IXU_IXA_ISSUED",
324
+
"BriefDescription": "Uops issued by the scheduler on IXA"
325
+
},
326
+
{
327
+
"PublicDescription": "Uops issued by the scheduler on IXA Par 0",
328
+
"EventCode": "0xD305",
329
+
"EventName": "IXU_IXA_PAR0_ISSUED",
330
+
"BriefDescription": "Uops issued by the scheduler on IXA Par 0"
331
+
},
332
+
{
333
+
"PublicDescription": "Uops issued by the scheduler on IXA Par 1",
334
+
"EventCode": "0xD306",
335
+
"EventName": "IXU_IXA_PAR1_ISSUED",
336
+
"BriefDescription": "Uops issued by the scheduler on IXA Par 1"
337
+
},
338
+
{
339
+
"PublicDescription": "Uops issued by the scheduler on IXB",
340
+
"EventCode": "0xD307",
341
+
"EventName": "IXU_IXB_ISSUED",
342
+
"BriefDescription": "Uops issued by the scheduler on IXB"
343
+
},
344
+
{
345
+
"PublicDescription": "Uops issued by the scheduler on IXB Par 0",
346
+
"EventCode": "0xD308",
347
+
"EventName": "IXU_IXB_PAR0_ISSUED",
348
+
"BriefDescription": "Uops issued by the scheduler on IXB Par 0"
349
+
},
350
+
{
351
+
"PublicDescription": "Uops issued by the scheduler on IXB Par 1",
352
+
"EventCode": "0xD309",
353
+
"EventName": "IXU_IXB_PAR1_ISSUED",
354
+
"BriefDescription": "Uops issued by the scheduler on IXB Par 1"
355
+
},
356
+
{
357
+
"PublicDescription": "Uops issued by the scheduler on IXC",
358
+
"EventCode": "0xD30A",
359
+
"EventName": "IXU_IXC_ISSUED",
360
+
"BriefDescription": "Uops issued by the scheduler on IXC"
361
+
},
362
+
{
363
+
"PublicDescription": "Uops issued by the scheduler on IXC Par 0",
364
+
"EventCode": "0xD30B",
365
+
"EventName": "IXU_IXC_PAR0_ISSUED",
366
+
"BriefDescription": "Uops issued by the scheduler on IXC Par 0"
367
+
},
368
+
{
369
+
"PublicDescription": "Uops issued by the scheduler on IXC Par 1",
370
+
"EventCode": "0xD30C",
371
+
"EventName": "IXU_IXC_PAR1_ISSUED",
372
+
"BriefDescription": "Uops issued by the scheduler on IXC Par 1"
373
+
},
374
+
{
375
+
"PublicDescription": "Uops issued by the scheduler on IXD",
376
+
"EventCode": "0xD30D",
377
+
"EventName": "IXU_IXD_ISSUED",
378
+
"BriefDescription": "Uops issued by the scheduler on IXD"
379
+
},
380
+
{
381
+
"PublicDescription": "Uops issued by the scheduler on IXD Par 0",
382
+
"EventCode": "0xD30E",
383
+
"EventName": "IXU_IXD_PAR0_ISSUED",
384
+
"BriefDescription": "Uops issued by the scheduler on IXD Par 0"
385
+
},
386
+
{
387
+
"PublicDescription": "Uops issued by the scheduler on IXD Par 1",
388
+
"EventCode": "0xD30F",
389
+
"EventName": "IXU_IXD_PAR1_ISSUED",
390
+
"BriefDescription": "Uops issued by the scheduler on IXD Par 1"
391
+
},
392
+
{
393
+
"PublicDescription": "Uops issued by the FSU scheduler",
394
+
"EventCode": "0xD400",
395
+
"EventName": "FSU_ISSUED",
396
+
"BriefDescription": "Uops issued by the FSU scheduler"
397
+
},
398
+
{
399
+
"PublicDescription": "Uops issued by the scheduler on pipe X",
400
+
"EventCode": "0xD401",
401
+
"EventName": "FSU_FSX_ISSUED",
402
+
"BriefDescription": "Uops issued by the scheduler on pipe X"
403
+
},
404
+
{
405
+
"PublicDescription": "Uops issued by the scheduler on pipe Y",
406
+
"EventCode": "0xD402",
407
+
"EventName": "FSU_FSY_ISSUED",
408
+
"BriefDescription": "Uops issued by the scheduler on pipe Y"
409
+
},
410
+
{
411
+
"PublicDescription": "Uops issued by the scheduler on pipe Z",
412
+
"EventCode": "0xD403",
413
+
"EventName": "FSU_FSZ_ISSUED",
414
+
"BriefDescription": "Uops issued by the scheduler on pipe Z"
415
+
},
416
+
{
417
+
"PublicDescription": "Uops canceled (load cancels)",
418
+
"EventCode": "0xD404",
419
+
"EventName": "FSU_CANCEL",
420
+
"BriefDescription": "Uops canceled (load cancels)"
421
+
},
422
+
{
423
+
"PublicDescription": "Count scheduler stalls due to divide/sqrt",
424
+
"EventCode": "0xD405",
425
+
"EventName": "FSU_DIV_SQRT_STALL",
426
+
"BriefDescription": "Count scheduler stalls due to divide/sqrt"
427
+
},
428
+
{
429
+
"PublicDescription": "Number of SWOB drains",
430
+
"EventCode": "0xD500",
431
+
"EventName": "GPC_SWOB_DRAIN",
432
+
"BriefDescription": "Number of SWOB drains"
433
+
},
434
+
{
435
+
"PublicDescription": "GPC detected a Breakpoint instruction match",
436
+
"EventCode": "0xD501",
437
+
"EventName": "BREAKPOINT_MATCH",
438
+
"BriefDescription": "GPC detected a Breakpoint instruction match"
439
+
},
440
+
{
441
+
"PublicDescription": "L1D TLB miss",
442
+
"EventCode": "0xD600",
443
+
"EventName": "L1D_TLB_MISS",
444
+
"BriefDescription": "L1D TLB miss"
445
+
},
446
+
{
447
+
"PublicDescription": "OFB full cycles",
448
+
"EventCode": "0xD601",
449
+
"EventName": "OFB_FULL",
450
+
"BriefDescription": "OFB full cycles"
451
+
},
452
+
{
453
+
"PublicDescription": "Load satisified from store forwarded data",
454
+
"EventCode": "0xD605",
455
+
"EventName": "LD_FROM_ST_FWD",
456
+
"BriefDescription": "Load satisified from store forwarded data"
457
+
},
458
+
{
459
+
"PublicDescription": "L1 prefetcher, load prefetch requests generated",
460
+
"EventCode": "0xD606",
461
+
"EventName": "L1_PFETCH_LD_GEN",
462
+
"BriefDescription": "L1 prefetcher, load prefetch requests generated"
463
+
},
464
+
{
465
+
"PublicDescription": "L1 prefetcher, load prefetch fills into the L1 cache",
466
+
"EventCode": "0xD607",
467
+
"EventName": "L1_PFETCH_LD_FILL",
468
+
"BriefDescription": "L1 prefetcher, load prefetch fills into the L1 cache"
469
+
},
470
+
{
471
+
"PublicDescription": "L1 prefetcher, load prefetch to L2 generated",
472
+
"EventCode": "0xD608",
473
+
"EventName": "L1_PFETCH_L2_REQ",
474
+
"BriefDescription": "L1 prefetcher, load prefetch to L2 generated"
475
+
},
476
+
{
477
+
"PublicDescription": "L1 prefetcher, distance was reset",
478
+
"EventCode": "0xD609",
479
+
"EventName": "L1_PFETCH_DIST_RST",
480
+
"BriefDescription": "L1 prefetcher, distance was reset"
481
+
},
482
+
{
483
+
"PublicDescription": "L1 prefetcher, distance was increased",
484
+
"EventCode": "0xD60A",
485
+
"EventName": "L1_PFETCH_DIST_INC",
486
+
"BriefDescription": "L1 prefetcher, distance was increased"
487
+
},
488
+
{
489
+
"PublicDescription": "L1 prefetcher, table entry is trained",
490
+
"EventCode": "0xD60B",
491
+
"EventName": "L1_PFETCH_ENTRY_TRAINED",
492
+
"BriefDescription": "L1 prefetcher, table entry is trained"
493
+
},
494
+
{
495
+
"PublicDescription": "Store retirement pipe stall",
496
+
"EventCode": "0xD60C",
497
+
"EventName": "LSU_ST_RETIRE_STALL",
498
+
"BriefDescription": "Store retirement pipe stall"
499
+
},
500
+
{
501
+
"PublicDescription": "LSU detected a Watchpoint data match",
502
+
"EventCode": "0xD60D",
503
+
"EventName": "WATCHPOINT_MATCH",
504
+
"BriefDescription": "LSU detected a Watchpoint data match"
505
+
},
506
+
{
507
+
"PublicDescription": "L2 pipeline replay",
508
+
"EventCode": "0xD700",
509
+
"EventName": "L2C_PIPE_REPLAY",
510
+
"BriefDescription": "L2 pipeline replay"
511
+
},
512
+
{
513
+
"PublicDescription": "L2 refill from I-side miss",
514
+
"EventCode": "0xD701",
515
+
"EventName": "L2C_INST_REFILL",
516
+
"BriefDescription": "L2 refill from I-side miss"
517
+
},
518
+
{
519
+
"PublicDescription": "L2 refill from D-side miss",
520
+
"EventCode": "0xD702",
521
+
"EventName": "L2C_DATA_REFILL",
522
+
"BriefDescription": "L2 refill from D-side miss"
523
+
},
524
+
{
525
+
"PublicDescription": "L2 prefetcher, load prefetch requests generated",
526
+
"EventCode": "0xD703",
527
+
"EventName": "L2_PREFETCH_REQ",
528
+
"BriefDescription": "L2 prefetcher, load prefetch requests generated"
529
+
},
530
+
{
531
+
"PublicDescription": "L2D OTB allocate",
532
+
"EventCode": "0xD800",
533
+
"EventName": "MMU_D_OTB_ALLOC",
534
+
"BriefDescription": "L2D OTB allocate"
535
+
},
536
+
{
537
+
"PublicDescription": "DTLB Translation cache hit on S1L2 walk cache entry",
538
+
"EventCode": "0xD801",
539
+
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L2_WALK",
540
+
"BriefDescription": "DTLB Translation cache hit on S1L2 walk cache entry"
541
+
},
542
+
{
543
+
"PublicDescription": "DTLB Translation cache hit on S1L1 walk cache entry",
544
+
"EventCode": "0xD802",
545
+
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L1_WALK",
546
+
"BriefDescription": "DTLB Translation cache hit on S1L1 walk cache entry"
547
+
},
548
+
{
549
+
"PublicDescription": "DTLB Translation cache hit on S1L0 walk cache entry",
550
+
"EventCode": "0xD803",
551
+
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L0_WALK",
552
+
"BriefDescription": "DTLB Translation cache hit on S1L0 walk cache entry"
553
+
},
554
+
{
555
+
"PublicDescription": "DTLB Translation cache hit on S2L2 walk cache entry",
556
+
"EventCode": "0xD804",
557
+
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L2_WALK",
558
+
"BriefDescription": "DTLB Translation cache hit on S2L2 walk cache entry"
559
+
},
560
+
{
561
+
"PublicDescription": "DTLB Translation cache hit on S2L1 walk cache entry",
562
+
"EventCode": "0xD805",
563
+
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L1_WALK",
564
+
"BriefDescription": "DTLB Translation cache hit on S2L1 walk cache entry"
565
+
},
566
+
{
567
+
"PublicDescription": "DTLB Translation cache hit on S2L0 walk cache entry",
568
+
"EventCode": "0xD806",
569
+
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L0_WALK",
570
+
"BriefDescription": "DTLB Translation cache hit on S2L0 walk cache entry"
571
+
},
572
+
{
573
+
"PublicDescription": "D-side S1 Page walk cache lookup",
574
+
"EventCode": "0xD807",
575
+
"EventName": "MMU_D_S1_WALK_CACHE_LOOKUP",
576
+
"BriefDescription": "D-side S1 Page walk cache lookup"
577
+
},
578
+
{
579
+
"PublicDescription": "D-side S1 Page walk cache refill",
580
+
"EventCode": "0xD808",
581
+
"EventName": "MMU_D_S1_WALK_CACHE_REFILL",
582
+
"BriefDescription": "D-side S1 Page walk cache refill"
583
+
},
584
+
{
585
+
"PublicDescription": "D-side S2 Page walk cache lookup",
586
+
"EventCode": "0xD809",
587
+
"EventName": "MMU_D_S2_WALK_CACHE_LOOKUP",
588
+
"BriefDescription": "D-side S2 Page walk cache lookup"
589
+
},
590
+
{
591
+
"PublicDescription": "D-side S2 Page walk cache refill",
592
+
"EventCode": "0xD80A",
593
+
"EventName": "MMU_D_S2_WALK_CACHE_REFILL",
594
+
"BriefDescription": "D-side S2 Page walk cache refill"
595
+
},
596
+
{
597
+
"PublicDescription": "D-side Stage1 tablewalk fault",
598
+
"EventCode": "0xD80B",
599
+
"EventName": "MMU_D_S1_WALK_FAULT",
600
+
"BriefDescription": "D-side Stage1 tablewalk fault"
601
+
},
602
+
{
603
+
"PublicDescription": "D-side Stage2 tablewalk fault",
604
+
"EventCode": "0xD80C",
605
+
"EventName": "MMU_D_S2_WALK_FAULT",
606
+
"BriefDescription": "D-side Stage2 tablewalk fault"
607
+
},
608
+
{
609
+
"PublicDescription": "D-side Tablewalk steps or descriptor fetches",
610
+
"EventCode": "0xD80D",
611
+
"EventName": "MMU_D_WALK_STEPS",
612
+
"BriefDescription": "D-side Tablewalk steps or descriptor fetches"
613
+
},
614
+
{
615
+
"PublicDescription": "L2I OTB allocate",
616
+
"EventCode": "0xD900",
617
+
"EventName": "MMU_I_OTB_ALLOC",
618
+
"BriefDescription": "L2I OTB allocate"
619
+
},
620
+
{
621
+
"PublicDescription": "ITLB Translation cache hit on S1L2 walk cache entry",
622
+
"EventCode": "0xD901",
623
+
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L2_WALK",
624
+
"BriefDescription": "ITLB Translation cache hit on S1L2 walk cache entry"
625
+
},
626
+
{
627
+
"PublicDescription": "ITLB Translation cache hit on S1L1 walk cache entry",
628
+
"EventCode": "0xD902",
629
+
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L1_WALK",
630
+
"BriefDescription": "ITLB Translation cache hit on S1L1 walk cache entry"
631
+
},
632
+
{
633
+
"PublicDescription": "ITLB Translation cache hit on S1L0 walk cache entry",
634
+
"EventCode": "0xD903",
635
+
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L0_WALK",
636
+
"BriefDescription": "ITLB Translation cache hit on S1L0 walk cache entry"
637
+
},
638
+
{
639
+
"PublicDescription": "ITLB Translation cache hit on S2L2 walk cache entry",
640
+
"EventCode": "0xD904",
641
+
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L2_WALK",
642
+
"BriefDescription": "ITLB Translation cache hit on S2L2 walk cache entry"
643
+
},
644
+
{
645
+
"PublicDescription": "ITLB Translation cache hit on S2L1 walk cache entry",
646
+
"EventCode": "0xD905",
647
+
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L1_WALK",
648
+
"BriefDescription": "ITLB Translation cache hit on S2L1 walk cache entry"
649
+
},
650
+
{
651
+
"PublicDescription": "ITLB Translation cache hit on S2L0 walk cache entry",
652
+
"EventCode": "0xD906",
653
+
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L0_WALK",
654
+
"BriefDescription": "ITLB Translation cache hit on S2L0 walk cache entry"
655
+
},
656
+
{
657
+
"PublicDescription": "I-side S1 Page walk cache lookup",
658
+
"EventCode": "0xD907",
659
+
"EventName": "MMU_I_S1_WALK_CACHE_LOOKUP",
660
+
"BriefDescription": "I-side S1 Page walk cache lookup"
661
+
},
662
+
{
663
+
"PublicDescription": "I-side S1 Page walk cache refill",
664
+
"EventCode": "0xD908",
665
+
"EventName": "MMU_I_S1_WALK_CACHE_REFILL",
666
+
"BriefDescription": "I-side S1 Page walk cache refill"
667
+
},
668
+
{
669
+
"PublicDescription": "I-side S2 Page walk cache lookup",
670
+
"EventCode": "0xD909",
671
+
"EventName": "MMU_I_S2_WALK_CACHE_LOOKUP",
672
+
"BriefDescription": "I-side S2 Page walk cache lookup"
673
+
},
674
+
{
675
+
"PublicDescription": "I-side S2 Page walk cache refill",
676
+
"EventCode": "0xD90A",
677
+
"EventName": "MMU_I_S2_WALK_CACHE_REFILL",
678
+
"BriefDescription": "I-side S2 Page walk cache refill"
679
+
},
680
+
{
681
+
"PublicDescription": "I-side Stage1 tablewalk fault",
682
+
"EventCode": "0xD90B",
683
+
"EventName": "MMU_I_S1_WALK_FAULT",
684
+
"BriefDescription": "I-side Stage1 tablewalk fault"
685
+
},
686
+
{
687
+
"PublicDescription": "I-side Stage2 tablewalk fault",
688
+
"EventCode": "0xD90C",
689
+
"EventName": "MMU_I_S2_WALK_FAULT",
690
+
"BriefDescription": "I-side Stage2 tablewalk fault"
691
+
},
692
+
{
693
+
"PublicDescription": "I-side Tablewalk steps or descriptor fetches",
694
+
"EventCode": "0xD90D",
695
+
"EventName": "MMU_I_WALK_STEPS",
696
+
"BriefDescription": "I-side Tablewalk steps or descriptor fetches"
697
+
}
698
+
]
+44
tools/perf/pmu-events/arch/arm64/ampere/ampereone/exception.json
+44
tools/perf/pmu-events/arch/arm64/ampere/ampereone/exception.json
···
1
+
[
2
+
{
3
+
"ArchStdEvent": "EXC_UNDEF"
4
+
},
5
+
{
6
+
"ArchStdEvent": "EXC_SVC"
7
+
},
8
+
{
9
+
"ArchStdEvent": "EXC_PABORT"
10
+
},
11
+
{
12
+
"ArchStdEvent": "EXC_DABORT"
13
+
},
14
+
{
15
+
"ArchStdEvent": "EXC_IRQ"
16
+
},
17
+
{
18
+
"ArchStdEvent": "EXC_FIQ"
19
+
},
20
+
{
21
+
"ArchStdEvent": "EXC_HVC"
22
+
},
23
+
{
24
+
"ArchStdEvent": "EXC_TRAP_PABORT"
25
+
},
26
+
{
27
+
"ArchStdEvent": "EXC_TRAP_DABORT"
28
+
},
29
+
{
30
+
"ArchStdEvent": "EXC_TRAP_OTHER"
31
+
},
32
+
{
33
+
"ArchStdEvent": "EXC_TRAP_IRQ"
34
+
},
35
+
{
36
+
"ArchStdEvent": "EXC_TRAP_FIQ"
37
+
},
38
+
{
39
+
"ArchStdEvent": "EXC_TAKEN"
40
+
},
41
+
{
42
+
"ArchStdEvent": "EXC_RETURN"
43
+
}
44
+
]
+89
tools/perf/pmu-events/arch/arm64/ampere/ampereone/instruction.json
+89
tools/perf/pmu-events/arch/arm64/ampere/ampereone/instruction.json
···
1
+
[
2
+
{
3
+
"ArchStdEvent": "SW_INCR"
4
+
},
5
+
{
6
+
"ArchStdEvent": "ST_RETIRED"
7
+
},
8
+
{
9
+
"ArchStdEvent": "OP_SPEC"
10
+
},
11
+
{
12
+
"ArchStdEvent": "LD_SPEC"
13
+
},
14
+
{
15
+
"ArchStdEvent": "ST_SPEC"
16
+
},
17
+
{
18
+
"ArchStdEvent": "LDST_SPEC"
19
+
},
20
+
{
21
+
"ArchStdEvent": "DP_SPEC"
22
+
},
23
+
{
24
+
"ArchStdEvent": "ASE_SPEC"
25
+
},
26
+
{
27
+
"ArchStdEvent": "VFP_SPEC"
28
+
},
29
+
{
30
+
"ArchStdEvent": "PC_WRITE_SPEC"
31
+
},
32
+
{
33
+
"ArchStdEvent": "BR_IMMED_RETIRED"
34
+
},
35
+
{
36
+
"ArchStdEvent": "BR_RETURN_RETIRED"
37
+
},
38
+
{
39
+
"ArchStdEvent": "CRYPTO_SPEC"
40
+
},
41
+
{
42
+
"ArchStdEvent": "ISB_SPEC"
43
+
},
44
+
{
45
+
"ArchStdEvent": "DSB_SPEC"
46
+
},
47
+
{
48
+
"ArchStdEvent": "DMB_SPEC"
49
+
},
50
+
{
51
+
"ArchStdEvent": "RC_LD_SPEC"
52
+
},
53
+
{
54
+
"ArchStdEvent": "RC_ST_SPEC"
55
+
},
56
+
{
57
+
"ArchStdEvent": "INST_RETIRED"
58
+
},
59
+
{
60
+
"ArchStdEvent": "CID_WRITE_RETIRED"
61
+
},
62
+
{
63
+
"ArchStdEvent": "PC_WRITE_RETIRED"
64
+
},
65
+
{
66
+
"ArchStdEvent": "INST_SPEC"
67
+
},
68
+
{
69
+
"ArchStdEvent": "TTBR_WRITE_RETIRED"
70
+
},
71
+
{
72
+
"ArchStdEvent": "BR_RETIRED"
73
+
},
74
+
{
75
+
"ArchStdEvent": "BR_MIS_PRED_RETIRED"
76
+
},
77
+
{
78
+
"ArchStdEvent": "OP_RETIRED"
79
+
},
80
+
{
81
+
"ArchStdEvent": "OP_SPEC"
82
+
},
83
+
{
84
+
"PublicDescription": "Operation speculatively executed, NOP",
85
+
"EventCode": "0x100",
86
+
"EventName": "NOP_SPEC",
87
+
"BriefDescription": "Speculatively executed, NOP"
88
+
}
89
+
]
+14
tools/perf/pmu-events/arch/arm64/ampere/ampereone/intrinsic.json
+14
tools/perf/pmu-events/arch/arm64/ampere/ampereone/intrinsic.json
+44
tools/perf/pmu-events/arch/arm64/ampere/ampereone/memory.json
+44
tools/perf/pmu-events/arch/arm64/ampere/ampereone/memory.json
···
1
+
[
2
+
{
3
+
"ArchStdEvent": "LD_RETIRED"
4
+
},
5
+
{
6
+
"ArchStdEvent": "MEM_ACCESS_RD"
7
+
},
8
+
{
9
+
"ArchStdEvent": "MEM_ACCESS_WR"
10
+
},
11
+
{
12
+
"ArchStdEvent": "UNALIGNED_LD_SPEC"
13
+
},
14
+
{
15
+
"ArchStdEvent": "UNALIGNED_ST_SPEC"
16
+
},
17
+
{
18
+
"ArchStdEvent": "UNALIGNED_LDST_SPEC"
19
+
},
20
+
{
21
+
"ArchStdEvent": "LD_ALIGN_LAT"
22
+
},
23
+
{
24
+
"ArchStdEvent": "ST_ALIGN_LAT"
25
+
},
26
+
{
27
+
"ArchStdEvent": "MEM_ACCESS"
28
+
},
29
+
{
30
+
"ArchStdEvent": "MEMORY_ERROR"
31
+
},
32
+
{
33
+
"ArchStdEvent": "LDST_ALIGN_LAT"
34
+
},
35
+
{
36
+
"ArchStdEvent": "MEM_ACCESS_CHECKED"
37
+
},
38
+
{
39
+
"ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
40
+
},
41
+
{
42
+
"ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
43
+
}
44
+
]
+23
tools/perf/pmu-events/arch/arm64/ampere/ampereone/pipeline.json
+23
tools/perf/pmu-events/arch/arm64/ampere/ampereone/pipeline.json
···
1
+
[
2
+
{
3
+
"ArchStdEvent": "STALL_FRONTEND"
4
+
},
5
+
{
6
+
"ArchStdEvent": "STALL_BACKEND"
7
+
},
8
+
{
9
+
"ArchStdEvent": "STALL"
10
+
},
11
+
{
12
+
"ArchStdEvent": "STALL_SLOT_BACKEND"
13
+
},
14
+
{
15
+
"ArchStdEvent": "STALL_SLOT_FRONTEND"
16
+
},
17
+
{
18
+
"ArchStdEvent": "STALL_SLOT"
19
+
},
20
+
{
21
+
"ArchStdEvent": "STALL_BACKEND_MEM"
22
+
}
23
+
]
+14
tools/perf/pmu-events/arch/arm64/ampere/ampereone/spe.json
+14
tools/perf/pmu-events/arch/arm64/ampere/ampereone/spe.json