Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Pull drm fixes from Dave Airlie:
"One qxl 32-bit warning fix, the rest is a bunch of radeon fixes from
Alex for some issues we've been seeing."

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/qxl: fix build warnings on 32-bit
radeon: use max_bus_speed to activate gen2 speeds
drm/radeon: narrow scope of Apple re-POST hack
drm/radeon: don't check crtcs in card_posted() on cards without DCE
drm/radeon: fix card_posted check for newer asics
drm/radeon: fix typo in cu_per_sh on verde
drm/radeon: UVD block on SUMO2 is the same as on SUMO

Linus Torvalds 13 years ago a93cb29a 4203afc3

+32 -42

7 changed files

expand all

drivers

gpu

drm

qxl

qxl_ioctl.c

qxl_kms.c

radeon

evergreen.c

r600.c

radeon_device.c

rv770.c

si.c

+2 -2

drivers/gpu/drm/qxl/qxl_ioctl.c

··· 151 151 struct qxl_bo *cmd_bo; 152 152 int release_type; 153 153 struct drm_qxl_command *commands = 154 - (struct drm_qxl_command *)execbuffer->commands; 154 + (struct drm_qxl_command *)(uintptr_t)execbuffer->commands; 155 155 156 156 if (DRM_COPY_FROM_USER(&user_cmd, &commands[cmd_num], 157 157 sizeof(user_cmd))) ··· 193 193 194 194 for (i = 0 ; i < user_cmd.relocs_num; ++i) { 195 195 if (DRM_COPY_FROM_USER(&reloc, 196 - &((struct drm_qxl_reloc *)user_cmd.relocs)[i], 196 + &((struct drm_qxl_reloc *)(uintptr_t)user_cmd.relocs)[i], 197 197 sizeof(reloc))) { 198 198 qxl_bo_list_unreserve(&reloc_list, true); 199 199 qxl_release_unreserve(qdev, release);

+5 -4

drivers/gpu/drm/qxl/qxl_kms.c

··· 128 128 129 129 qdev->vram_mapping = io_mapping_create_wc(qdev->vram_base, pci_resource_len(pdev, 0)); 130 130 qdev->surface_mapping = io_mapping_create_wc(qdev->surfaceram_base, qdev->surfaceram_size); 131 - DRM_DEBUG_KMS("qxl: vram %p-%p(%dM %dk), surface %p-%p(%dM %dk)\n", 132 - (void *)qdev->vram_base, (void *)pci_resource_end(pdev, 0), 131 + DRM_DEBUG_KMS("qxl: vram %llx-%llx(%dM %dk), surface %llx-%llx(%dM %dk)\n", 132 + (unsigned long long)qdev->vram_base, 133 + (unsigned long long)pci_resource_end(pdev, 0), 133 134 (int)pci_resource_len(pdev, 0) / 1024 / 1024, 134 135 (int)pci_resource_len(pdev, 0) / 1024, 135 - (void *)qdev->surfaceram_base, 136 - (void *)pci_resource_end(pdev, 1), 136 + (unsigned long long)qdev->surfaceram_base, 137 + (unsigned long long)pci_resource_end(pdev, 1), 137 138 (int)qdev->surfaceram_size / 1024 / 1024, 138 139 (int)qdev->surfaceram_size / 1024); 139 140

+3 -7

drivers/gpu/drm/radeon/evergreen.c

··· 4999 4999 5000 5000 void evergreen_pcie_gen2_enable(struct radeon_device *rdev) 5001 5001 { 5002 - u32 link_width_cntl, speed_cntl, mask; 5003 - int ret; 5002 + u32 link_width_cntl, speed_cntl; 5004 5003 5005 5004 if (radeon_pcie_gen2 == 0) 5006 5005 return; ··· 5014 5015 if (ASIC_IS_X2(rdev)) 5015 5016 return; 5016 5017 5017 - ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 5018 - if (ret != 0) 5019 - return; 5020 - 5021 - if (!(mask & DRM_PCIE_SPEED_50)) 5018 + if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && 5019 + (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) 5022 5020 return; 5023 5021 5024 5022 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

+2 -7

drivers/gpu/drm/radeon/r600.c

··· 4631 4631 { 4632 4632 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4633 4633 u16 link_cntl2; 4634 - u32 mask; 4635 - int ret; 4636 4634 4637 4635 if (radeon_pcie_gen2 == 0) 4638 4636 return; ··· 4649 4651 if (rdev->family <= CHIP_R600) 4650 4652 return; 4651 4653 4652 - ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 4653 - if (ret != 0) 4654 - return; 4655 - 4656 - if (!(mask & DRM_PCIE_SPEED_50)) 4654 + if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && 4655 + (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) 4657 4656 return; 4658 4657 4659 4658 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

+16 -11

drivers/gpu/drm/radeon/radeon_device.c

··· 467 467 { 468 468 uint32_t reg; 469 469 470 + /* required for EFI mode on macbook2,1 which uses an r5xx asic */ 470 471 if (efi_enabled(EFI_BOOT) && 471 - rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) 472 + (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 473 + (rdev->family < CHIP_R600)) 472 474 return false; 473 475 476 + if (ASIC_IS_NODCE(rdev)) 477 + goto check_memsize; 478 + 474 479 /* first check CRTCs */ 475 - if (ASIC_IS_DCE41(rdev)) { 480 + if (ASIC_IS_DCE4(rdev)) { 476 481 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 477 482 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 478 - if (reg & EVERGREEN_CRTC_MASTER_EN) 479 - return true; 480 - } else if (ASIC_IS_DCE4(rdev)) { 481 - reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 482 - RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | 483 - RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 484 - RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | 485 - RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 486 - RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 483 + if (rdev->num_crtc >= 4) { 484 + reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 485 + RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 486 + } 487 + if (rdev->num_crtc >= 6) { 488 + reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 489 + RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 490 + } 487 491 if (reg & EVERGREEN_CRTC_MASTER_EN) 488 492 return true; 489 493 } else if (ASIC_IS_AVIVO(rdev)) { ··· 504 500 } 505 501 } 506 502 503 + check_memsize: 507 504 /* then check MEM_SIZE, in case the crtcs are off */ 508 505 if (rdev->family >= CHIP_R600) 509 506 reg = RREG32(R600_CONFIG_MEMSIZE);

+3 -10

drivers/gpu/drm/radeon/rv770.c

··· 862 862 chip_id = 0x0100000b; 863 863 break; 864 864 case CHIP_SUMO: 865 - chip_id = 0x0100000c; 866 - break; 867 865 case CHIP_SUMO2: 868 - chip_id = 0x0100000d; 866 + chip_id = 0x0100000c; 869 867 break; 870 868 case CHIP_PALM: 871 869 chip_id = 0x0100000e; ··· 2111 2113 { 2112 2114 u32 link_width_cntl, lanes, speed_cntl, tmp; 2113 2115 u16 link_cntl2; 2114 - u32 mask; 2115 - int ret; 2116 2116 2117 2117 if (radeon_pcie_gen2 == 0) 2118 2118 return; ··· 2125 2129 if (ASIC_IS_X2(rdev)) 2126 2130 return; 2127 2131 2128 - ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 2129 - if (ret != 0) 2130 - return; 2131 - 2132 - if (!(mask & DRM_PCIE_SPEED_50)) 2132 + if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && 2133 + (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) 2133 2134 return; 2134 2135 2135 2136 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");

+1 -1

drivers/gpu/drm/radeon/si.c

··· 2616 2616 default: 2617 2617 rdev->config.si.max_shader_engines = 1; 2618 2618 rdev->config.si.max_tile_pipes = 4; 2619 - rdev->config.si.max_cu_per_sh = 2; 2619 + rdev->config.si.max_cu_per_sh = 5; 2620 2620 rdev->config.si.max_sh_per_se = 2; 2621 2621 rdev->config.si.max_backends_per_se = 4; 2622 2622 rdev->config.si.max_texture_channel_caches = 4;