tjh.dev / kernel
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drm/amdgpu/vce4: move mm table constructions functions into mmsch header file

Move mm table construction functions into mmsch header file so that
UVD can reuse it.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Frank Min and committed by
Alex Deucher a92f5ec0 b53b8cda

+103 -97
+57
drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
··· 84 84 uint32_t reg_value; 85 85 }; 86 86 87 + static inline void mmsch_v1_0_insert_direct_wt(struct mmsch_v1_0_cmd_direct_write *direct_wt, 88 + uint32_t *init_table, 89 + uint32_t reg_offset, 90 + uint32_t value) 91 + { 92 + direct_wt->cmd_header.reg_offset = reg_offset; 93 + direct_wt->reg_value = value; 94 + memcpy((void *)init_table, direct_wt, sizeof(struct mmsch_v1_0_cmd_direct_write)); 95 + } 96 + 97 + static inline void mmsch_v1_0_insert_direct_rd_mod_wt(struct mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt, 98 + uint32_t *init_table, 99 + uint32_t reg_offset, 100 + uint32_t mask, uint32_t data) 101 + { 102 + direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; 103 + direct_rd_mod_wt->mask_value = mask; 104 + direct_rd_mod_wt->write_data = data; 105 + memcpy((void *)init_table, direct_rd_mod_wt, 106 + sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)); 107 + } 108 + 109 + static inline void mmsch_v1_0_insert_direct_poll(struct mmsch_v1_0_cmd_direct_polling *direct_poll, 110 + uint32_t *init_table, 111 + uint32_t reg_offset, 112 + uint32_t mask, uint32_t wait) 113 + { 114 + direct_poll->cmd_header.reg_offset = reg_offset; 115 + direct_poll->mask_value = mask; 116 + direct_poll->wait_value = wait; 117 + memcpy((void *)init_table, direct_poll, sizeof(struct mmsch_v1_0_cmd_direct_polling)); 118 + } 119 + 120 + #define MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \ 121 + mmsch_v1_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \ 122 + init_table, (reg), \ 123 + (mask), (data)); \ 124 + init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \ 125 + table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \ 126 + } 127 + 128 + #define MMSCH_V1_0_INSERT_DIRECT_WT(reg, value) { \ 129 + mmsch_v1_0_insert_direct_wt(&direct_wt, \ 130 + init_table, (reg), \ 131 + (value)); \ 132 + init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \ 133 + table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \ 134 + } 135 + 136 + #define MMSCH_V1_0_INSERT_DIRECT_POLL(reg, mask, wait) { \ 137 + mmsch_v1_0_insert_direct_poll(&direct_poll, \ 138 + init_table, (reg), \ 139 + (mask), (wait)); \ 140 + init_table += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \ 141 + table_size += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \ 142 + } 143 + 87 144 #endif
+46 -97
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
··· 49 49 static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev); 50 50 static void vce_v4_0_set_irq_funcs(struct amdgpu_device *adev); 51 51 52 - static inline void mmsch_insert_direct_wt(struct mmsch_v1_0_cmd_direct_write *direct_wt, 53 - uint32_t *init_table, 54 - uint32_t reg_offset, 55 - uint32_t value) 56 - { 57 - direct_wt->cmd_header.reg_offset = reg_offset; 58 - direct_wt->reg_value = value; 59 - memcpy((void *)init_table, direct_wt, sizeof(struct mmsch_v1_0_cmd_direct_write)); 60 - } 61 - 62 - static inline void mmsch_insert_direct_rd_mod_wt(struct mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt, 63 - uint32_t *init_table, 64 - uint32_t reg_offset, 65 - uint32_t mask, uint32_t data) 66 - { 67 - direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; 68 - direct_rd_mod_wt->mask_value = mask; 69 - direct_rd_mod_wt->write_data = data; 70 - memcpy((void *)init_table, direct_rd_mod_wt, 71 - sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)); 72 - } 73 - 74 - static inline void mmsch_insert_direct_poll(struct mmsch_v1_0_cmd_direct_polling *direct_poll, 75 - uint32_t *init_table, 76 - uint32_t reg_offset, 77 - uint32_t mask, uint32_t wait) 78 - { 79 - direct_poll->cmd_header.reg_offset = reg_offset; 80 - direct_poll->mask_value = mask; 81 - direct_poll->wait_value = wait; 82 - memcpy((void *)init_table, direct_poll, sizeof(struct mmsch_v1_0_cmd_direct_polling)); 83 - } 84 - 85 - #define INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \ 86 - mmsch_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \ 87 - init_table, (reg), \ 88 - (mask), (data)); \ 89 - init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \ 90 - table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \ 91 - } 92 - 93 - #define INSERT_DIRECT_WT(reg, value) { \ 94 - mmsch_insert_direct_wt(&direct_wt, \ 95 - init_table, (reg), \ 96 - (value)); \ 97 - init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \ 98 - table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \ 99 - } 100 - 101 - #define INSERT_DIRECT_POLL(reg, mask, wait) { \ 102 - mmsch_insert_direct_poll(&direct_poll, \ 103 - init_table, (reg), \ 104 - (mask), (wait)); \ 105 - init_table += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \ 106 - table_size += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \ 107 - } 108 - 109 52 /** 110 53 * vce_v4_0_ring_get_rptr - get read pointer 111 54 * ··· 223 280 init_table += header->vce_table_offset; 224 281 225 282 ring = &adev->vce.ring[0]; 226 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), lower_32_bits(ring->gpu_addr)); 227 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); 228 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), ring->ring_size / 4); 283 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), 284 + lower_32_bits(ring->gpu_addr)); 285 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), 286 + upper_32_bits(ring->gpu_addr)); 287 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), 288 + ring->ring_size / 4); 229 289 230 290 /* BEGING OF MC_RESUME */ 231 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x398000); 232 - INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), ~0x1, 0); 233 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0); 234 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0); 235 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0); 291 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x398000); 292 + MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), ~0x1, 0); 293 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0); 294 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0); 295 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0); 236 296 237 297 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 238 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), 239 - adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); 240 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), 241 - adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); 242 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), 243 - adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); 298 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), 299 + adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); 300 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), 301 + adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); 302 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), 303 + adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); 244 304 } else { 245 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), 246 - adev->vce.gpu_addr >> 8); 247 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), 248 - adev->vce.gpu_addr >> 8); 249 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), 250 - adev->vce.gpu_addr >> 8); 305 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), 306 + adev->vce.gpu_addr >> 8); 307 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), 308 + adev->vce.gpu_addr >> 8); 309 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), 310 + adev->vce.gpu_addr >> 8); 251 311 } 252 312 253 313 offset = AMDGPU_VCE_FIRMWARE_OFFSET; 254 314 size = VCE_V4_0_FW_SIZE; 255 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), offset & 0x7FFFFFFF); 256 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size); 315 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 316 + offset & 0x7FFFFFFF); 317 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size); 257 318 258 319 offset += size; 259 320 size = VCE_V4_0_STACK_SIZE; 260 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), offset & 0x7FFFFFFF); 261 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size); 321 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), 322 + offset & 0x7FFFFFFF); 323 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size); 262 324 263 325 offset += size; 264 326 size = VCE_V4_0_DATA_SIZE; 265 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), offset & 0x7FFFFFFF); 266 - INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size); 327 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), 328 + offset & 0x7FFFFFFF); 329 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size); 267 330 268 - INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0); 269 - INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), 270 - 0xffffffff, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); 331 + MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0); 332 + MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), 333 + 0xffffffff, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); 271 334 272 335 /* end of MC_RESUME */ 273 - INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 274 - VCE_STATUS__JOB_BUSY_MASK, ~VCE_STATUS__JOB_BUSY_MASK); 275 - INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 276 - ~0x200001, VCE_VCPU_CNTL__CLK_EN_MASK); 277 - INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 278 - ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, 0); 336 + MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 337 + VCE_STATUS__JOB_BUSY_MASK, ~VCE_STATUS__JOB_BUSY_MASK); 338 + MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 339 + ~0x200001, VCE_VCPU_CNTL__CLK_EN_MASK); 340 + MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 341 + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, 0); 279 342 280 - INSERT_DIRECT_POLL(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 281 - VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK, 282 - VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK); 343 + MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 344 + VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK, 345 + VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK); 283 346 284 347 /* clear BUSY flag */ 285 - INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 286 - ~VCE_STATUS__JOB_BUSY_MASK, 0); 348 + MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 349 + ~VCE_STATUS__JOB_BUSY_MASK, 0); 287 350 288 351 /* add end packet */ 289 352 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));